QUESTION 1:

Five types of engineers in electronic company:

1. Test/Measurement engineer
2. Wafer Fabrication Process engineer
3. Design engineer
4. Media Process engineer
5. Manufacturing engineer

QUESTION 2:
Full forms for the common abbreviation in electronic industry below
1. On the Job Training (OJT)
2. Integrated Device Manufacturer (IDM)
3. Voluntary Separation Scheme (VSS)
4. Multinational Corporation (MNC)
5. Complementary Metal Oxide Semiconductor (CMOS)

QUESTION 3:
Five Multinational Companies for electronic sector in Penang

1. Pen Fabric Sdn Bhd

2. Jabil Circuit Sdn Bhd
3. ASE Electronics (M) Sdn Bhd
4. ALTERA Corporation (M) Sdn Bhd
5. INTEL Technology (M) Sdn Bhd

QUESTION 4:
One electronic MNC company in Malaysia and write a summary about it. (i.e. Headquarters, CEO
name, product, number of employees, revenue, etc)

ASE Electronics (M) Sdn. Bhd. established in 1991 and located in Penang, Malaysia. A
semiconductor manufacturing service provider of assembly packaging and testing solutions to
global semiconductor companies. ASE Malaysia is part of Advanced Semiconductor
Engineering (ASE) Group, the worlds largest provider of independent semiconductor
manufacturing services in assembly and test. As a global leader, ASE provides a complete
scope of services for the semiconductor market; driven by superior technologies,
breakthrough innovations, and advanced development program.
In 2012, ASE Group generated sales revenue of US$4.4 billion and employs over 50,000
people. For now, Lee Kwai Mun is the president of ASE Electronic for South East Asia.

QUESTION 5:
The flow chart for product development
For product development, it has four levels. At, first electrical design, must know the
definition of design and then think about the design concept. After complete description of the
idea or concept design, implement design, and can continue with the Simulation. Complete
with electrical design, we can do the physical design. It is in the physical design physical
verification and parasitic extraction. Physical verification is a process where the layout of the
integrated circuit (IC layout) design EDA software tool checked through to see if it meets
certain criteria. Validation involves the design rule check (DRC), layout versus schematic
(LVS), electrical rules checking (ERC), XOR (exclusive OR), and check the antenna.
Parasitic extraction is the calculation of the effect of the parasite in both devices designed and
wiring interconnects needed for electronic circuits, the parasitic capacitance, parasitic
resistance and parasitic inductances, usually called parasitic devices, parasitic components, or
just parasites. The main objective is to create a parasitic extraction exact model of analog
circuits, so that detailed simulations can emulate real answers digital and analog circuits.
Digital circuits answer often used to fill the database for signal delay and a lot of loading,
such as analysis of the time; circuit simulation; and signal integrity analysis. Analog circuits
often run on the test bench in detail to indicate if additional parasitic extracted will still allow
the circuit designed to work. Then, do the fabrication and testing.