Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
ise 5
May 2, 2017
1 Introdu
tion
This lab exer
ise seeks to implement a pipelined pro
essor implementation of a subset of the MIPS instru
tion
set that is
apable of dealing with RAW data hazards.
2 Spe
i
ations
The pro
essor implementation should be
ompliant to the MIPS instru
tion set, but any ex
eptions to the
programming model will be spe
ied in the spe
i
ations. We will also follow the MIPS
onvention of having
register 0 in the register le as a
onstant 0 whi
h
annot be written. All other registers
an be written to.
This se
tion denes the
ore instru
tions supported in stage 1, the interfa
e of the pro
essor, and the memory
models that will be used in simulation.
Table 1 shows the instru
tions that must be supported by the pro
essor. The rs, rt, and rd elds
orrespond
to register addresses (for the register le), while the imm eld, whi
h is 16-bits long,
orrespond to a 16-bit
onstant whi
h is en
oded in signed 2's-
omplement notation. For details on the exe
ution of ea
h of the rst
7 instru
tions (from a programming point of view), refer to lab exer
ise 3 and the
lass web page.
Jump instru
tions (J, JAL, and JR) bran
h un
onditionally to a
ertain instru
tion memory address. For
the J instru
tion, the PC is
hanged to a value of {PC[31:28, imm[25:0, 2'b00} instead of the normal PC+4.
JAL is identi
al to J, but it also writes the return address (instru
tion after JAL) to register 31. The JR
instru
tion repla
es the PC with the value stored in register rs.
In
ases where the instru
tion en
oding does not mat
h any of the supported instru
tions, the pro
essor
simply performs a NOP (No Operation) and does not
hange the pro
essor state (no writes to register le and
memory), ex
ept for the PC whi
h is in
remented normallly.
Table 2 lists the external interfa
e of the pro
essor. A global
lo
k signal,
lk, will govern all of the operations
in the pro
essor. An a
tive-low reset signal, rst_n, will also be present. Setting rst_n to 0 will reset the PC
and all registers in the register le to 0. The proto
ol and timing of these signals should follow spe
i
ations
1
set in lab exer
ise 4. You are also required to set the module name to pipelined_mips, for automated
he
king
purposes.
lk input 1
rst_n input 1
inst_addr output 32
inst input 32
data_addr output 32
data_in input 32
data_out output 32
data_wr output 1
p
_IF output 32
p
_ID output 32
p
_EXE output 32
p
_MEM output 32
p
_WB output 32
Both instru
tion and data memories will have syn
hronous read paths. On
e the address is issued, its
orre-
sponding
ontents are displayed immediately after next rising edge of the
lo
k. All writes are registered. The
memory element will be updated upon the next
lo
k edge after issuing the write (by asserting the write enable
signal). The memory model will be byte-addressable, but will have word-length read and write ports. Memory
organization is assumed to be big-endian. Whenever a byte-address X is issued, the
orreponding
ontents of
address X, X+1, X+2, and X+3 are pla
ed in the read port of the memory, with the rst byte (address X) as
the leftmost byte (MSB). For writes, bits [31:24 of the write port are written to address X, [23:16 to address
X+1, [15:8 to address X+2, and [7:0 to address X+3. Take note that for the instru
tion memory, we will only
have read ports.
Figure 1 shows an example of a read and write operation performed on the memory model. It assumes
that the following bytes are initially stored in memory: 0xAB at address 0x20, 0xCD at address 0x21, 0x12 at
address 0x22, 0x34 at address 0x23, and 0x56 at address 0x24. The rst read is word-aligned, while the se
ond
read and the write is not word-aligned. After the write, the state of the memory is: 0xAB at address 0x20,
0x11 at address 0x21, 0x11 at address 0x22, 0x11 at address 0x23, and 0x11 at address 0x24.
You are required to implement the pro
essor in 5 pipeline stages. Fun
tionality should follow spe
i
ations set
in lab exer
ise 4.
Figure 2 shows an example of two instru
tions (SW and ADDI) being exe
uted in the pipeline. Their
individual addresses in memory are pre-appended. Only
lk, inst_addr, inst, data_wr, PC_exe, and PC_mem
are required signals, as dis
ussed earlier. The other signals are internal signals whi
h you may
hoose to
implement or not.
Exe
ution starts with IF, where the inst_addr is set to the address of the instru
tion being fet
hed. One
lo
k
y
le after, the instru
tion is now at the memory output (inst) and
an already be de
oded. Being at the
2
ID stage, this is ree
ted by RF addr A (register le rst sour
e operand) being set to the appropriate value rs
of the instru
tion.
After another
lo
k
y
le, the instru
tion must now be in the EXE stage. In the example, this is shown
by the appropriate operation's result being found at the output of the ALU (ALU result). The instru
tion
then pro
eeds to the next stage, MEM, where memory writes are done by the SW instru
tion as shown by the
assertion of the data_wr signal.
Lastly, writes to the register le are done at the WB by the ADDI instru
tion as shown by the assertion of
the register le write enable signal (RF wr_en). Only after this
lo
k
y
le should the result be found in the
register le.
The PC_exe and PC_mem signals show at whi
h stage ea
h instru
tion is in the pipeline. For example,
PC_exe has a value of 16 at the
lo
k
y
le when the ALU result is the address
omputation of the memory
address for SW. This means that during that
lo
k
y
le, the SW instru
tion is at the EXE stage.
The pro
essor should be able to handle RAW data hazards that arise from dependent instru
tions. At the very
least, the pro
essor should stall a dependent instru
tion at the ID stage until the instru
tion that produ
es its
result nishes its WB stage. Due to the syn
hronous nature of memory a
ess, 3 stall
y
les will be inserted
when
onse
utive instru
tions have a RAW hazard, as shown in gure 3. Only 2 stall
y
les are inserted for the
last ADD instru
tion in the example sin
e the instru
tion it is dependent to has another instru
tion before the
last ADD.
Full data forwarding implementations
ompletely eliminate stalls from RAW hazards arising from non-load
instru
tions. The previous example now exe
utes in the manner shown in gure 4. Stall
y
les for the last ADD
instru
tion are
ompletely eliminated by a forwarding path from the EXE stage pipeline register to the EXE
stage. Take note that RAW hazards arising from load instru
tions
annot be settled by using forwarding sin
e
the operand has to go through the MEM stage. For purposes of
he
king, forwarding will only be veried for
non-load instru
tions. Any RAW hazards resulting from load instru
tions must be dealt with by inserting stall
y
les.
3
Figure 4: RAW hazard forwarding
The pro
essor should be synthesized using the generi
90nm standard
ell library provided in
lass. The
synthesized designs should operate at a
lo
k period of 20ns. The maximum input delay for all input pins
should be set to 25% of the
lo
k period. The maximum output delay for all output pins should be set to 25%
of the
lo
k period. Also, make sure to name your mapped Verilog le as pipelined_mips_mapped.v and your
SDF le as pipelined_mips_mapped.sdf (for automated
he
king purposes).
3 Submission
Grading will be broken down as follows:
5% LW, SW
5% LW, SW
All other instru
tions will only be graded if both LW and SW instru
tions are fully fun
tional.
Deadline for submission of this lab exer
ise will be on May 25, 11:59PM. The pro
essor will be veried using
an automated
he
ker testben
h. Make sure that your
odes are working before having them
he
ked. Submit
your
odes within in the deadline date by e-mail to
hris.densingeee.upd.edu.ph, with the e-mail subje
t
set to CoE 113 lab 5 submission. Send all sour
e Verilog les, the synthesized (mapped) Verilog le, and
the synthesized (mapped) SDF le ar
hived in single ZIP, TAR or TAR.GZ le, with lename in the format
[SURNAME_[FIRSTNAME (ex. densing_
hrisvin
ent.tar). Make sure that all the les within the ar
hive
are lo
ated in a at stru
ture, with no subdire
tories/folders
ontaining the required les. Appropriate demerits
will be given to those who fail to follow instru
tions.