Voltage

V DD

Logic value 1

V 1,min

Undefined

V 0,max

Logic value 0

V SS (Gnd)

Figure 3.1. Logic values as voltage levels.

 x = "low" x = "high"

(a) A simple switch controlled by the input x

Gate

Source Drain
Substrate (Body)

(b) NMOS transistor

VG

VS VD

(c) Simplified symbol for an NMOS transistor

Figure 3.2. NMOS transistor as a switch.

 x = "high" x = "low"

(a) A switch with the opposite behavior of Figure 3.2 a

Gate

Drain Source
VDD
Substrate (Body)

(b) PMOS transistor

VG

VS VD

(c) Simplified symbol for a PMOS transistor

Figure 3.3. PMOS transistor as a switch.

 VD VD = 0 V VD

VG

VS = 0 V
Closed switch Open switch
whenVG = VDD whenVG = 0 V

(a) NMOS transistor

VS = VDD VDD VDD

VG

VD VD VD = VDD
Open switch Closed switch
whenVG = VDD whenVG = 0 V

(b) PMOS transistor

Figure 3.4. NMOS and PMOS transistors in logic circuits.

 VDD

R R
+
5V
- Vf Vf

Vx Vx

(a) Circuit diagram (b) Simplified circuit diagram

x f x f

(c) Graphical symbols

Figure 3.5. A NOT gate built using NMOS technology.

 VDD

Vf

Vx
1

x1 x2 f

0 0 1
Vx
2 0 1 1
1 0 1
1 1 0

(a) Circuit (b) Truth table

x1 x1
f f
x2 x2

(c) Graphical symbols

Figure 3.6. NMOS realization of a NAND gate.

 V DD

x1 x2 f
Vf
0 0 1
Vx Vx 0 1 0
1 2
1 0 0
1 1 0

(a) Circuit (b) Truth table

x1 x1
x2 f x2 f

(c) Graphical symbols

Figure 3.7. NMOS realization of a NOR gate.

 VDD VDD

Vf

A
Vx
1

x1 x2 f

Vx 0 0 0
2
0 1 0
1 0 0
1 1 1

(a) Circuit (b) Truth table

x1 x1
f f
x2 x2

(c) G
Graphical
ap ca sysymbols
bo s

Figure 3.8. NMOS realization of an AND gate.

 V DD V DD

Vf

x1 x2 f

0 0 0
Vx Vx 0 1 1
1 2

1 0 1
1 1 1

((a)) Circuit ((b)) Truth table

x1 x1
x2 f x2 f

( )G
(c) Graphical
hi l symbols
b l

Figure 3.9. NMOS realization of an OR gate.

 V DD

Vf

Vx
1
Pull-down
P ll d network
t k
(PDN)
Vx
n

Figure 3.10. Structure of an NMOS circuit.

 V DD

Pull-up network
(PUN)

Vf

Vx
1
Pull-down network
(PDN)
Vx
n

Figure 3.11. Structure of a CMOS circuit.

 VDD

T1

Vx Vf
x T1 T2 f
T2
0 on off 1
1 off on 0

(a) Circuit (b) Truth table and transistor states

Figure 3.12.
3 12 CMOS realization of a NOT gate.
gate
 V DD

T1 T2

Vf

Vx T3 x1 x2 T1 T2 T3 T4 f
1

0 0 on on off off 1
0 1 on off off on 1
Vx T4 off on on off
2 1 0 1
1 1 off off on on 0

(a) Circuit (b) Truth table and transistor states

Figure 3.13. CMOS realization of a NAND gate.

 V DD

Vx T1
1

Vx T2
2

x1 x2 T1 T2 T3 T4 f
Vf
0 0 on on off off 1
T3 T4 0 1 on off off on 0
1 0 off on on off 0
1 1 off off on on 0

(a) Circuit (b) Truth table and transistor states

Figure 3.14. CMOS realization of a NOR gate.

 V DD V DD

Vf

Vx
1

Vx
2

Figure 3.15. CMOS realization of an AND gate.

 V DD

Vf

Vx
1

Vx
2

Vx
3
 V DD

Vf

Vx
1

Vx
2

Vx
3

Vx
4
 x1 x2 f

0 0 1 x1
0 1 1 f
x2
1 0 1
1 1 0

(a) Positive logic truth table and gate symbol

x1 x2 f

1 1 0 x1
1 0 0 f
x2
0 1 0
0 0 1

((b)) Negative
g logic
g truth table and g
gate symbol
y

Figure 3.19. Interpretation of the circuit in Figure

3.18.
The function provided by each 7400-series device is fixed and each chip only provides a
few logic gates These limitations make use of these chips inefficient for building large
circuits
It is possible to fabricate chips with a large amount of circuitry (gates) but with a
structure (interconnection) that is not fixed Called programmable logic devices (PLDs)

Logic gates
Inputs and Outputs
(logic variables) programmable (logic functions)
switches

Programmable logic device as a black box.

A PLD is a general purpose chip for implementing logic circuitry
Contains a collection of logic circuit elements that can be customized in different ways
Can be viewed as a black box containing logic gates and programmable switches that
allow for different connections between the logic elements
Can implement whatever logic circuit is needed subject to limitations of the devices

The first PLD developed was the programmable logic array (PLA)
Based on the premise that any function can be written in SOP form, a PLA consists
of Input buffers and inverters that provide the true and complement form for each
input variable
A collection of AND gates, with inputs that are selectable (programmable)
A collection of OR gates, with inputs that are selectable (programmable)
 x1 x2 xn

Input buffers
and
inverters

x1 x1 xn xn

P1

AND plane OR plane

Pk

f1 fm

Figure 3.25. General structure of a PLA.

 x1 x2 x3

Programmable
connections

OR plane
P1

P2

P3

P4

AND plane

f1 f2
Figure 3.26. Gate-level diagram of a
PLA
 x1 x2 x3

OR plane
P1

P2

P3

P4

AND plane

f1 f2

Figure 3.27. Customary schematic for the PLA in Figure 3.26.

x1 x2 x3

P1

f1
P2

P3

f2
P4

AND plane

Figure 3.28. An example of a PLA.