Bangladesh University of Engineering and Technology (BUET)

Dept. of Electrical and Electronic Engineering (EEE)

Lecture Schedule
Course Code EEE 303 Title: Digital Electronics
Section A/B/C

Teachers Prof. Dr. Pran Kanai Saha, Dept. of EEE, BUET.

Dr. Apratim Roy, Assistant Professor, Dept. of EEE, BUET.
Gobinda Saha, Assistant Professor, Dept. of EEE, BUET.

Text Book Fundamentals of Digital Logic with Verilog Design (2nd Edition)
Authors- Stephen Brown, Zvonko Vranesic

Helping books: Digital Logic and Computer Design By Morris Mano

Digital Fundamentals By Floyd, Floyd Thomas L

Quiz There will be a least four quizzes (15-20 minutes long each). The best three will be
taken
Test Policy If you are absent from a test, and you have not spoken to me personally
before hand, your grade for the test will be zero.
Objectives:
1. To teach students and fundamentals of digital electronic circuits.
2. To teach students how to model and analyze digital circuits.
3. To study different kinds of digital logic circuits.
4. To learn the use of Verilog Hardware description language (HDL) for circuit design.

Learning Outcomes
1. Students will understand the basics of digital logic circuit design.
2. Students will be able to use Verilog HDL to design digital logic circuits.
3. Student will demonstrate their ability to modify and design circuit parameters, in order to
improve circuit performance.

Course Content
Introduction to number systems and codes. Analysis and synthesis of digital logic circuits: Basic
logic functions, Boolean algebra, combinational logic design, minimization of combinational logic.
Implementation of basic static logic gates in CMOS and BiCMOS: DC characteristics, noise
margin and power dissipation. Power optimization of basic gates and combinational logic circuits.
Modular combinational circuit design: pass transistor, pass gates, multiplexer, demultiplexer and
their implementation in CMOS, decoder, encoder, comparators, binary arithmetic elements and
ALU design. Programmable logic devices: logic arrays, field programmable logic arrays and
programmable read only memory. Sequential circuits: different types of latches, flip-flops and
their design using ASM approach, timing analysis and power optimization of sequential circuits.
Modular sequential logic circuit design: shift registers, counters and their applications.
Tentative Class Schedule
Week Topics
Variables and Functions: Inversion, Truth Table, Logic Gates and Networks,
Analysis of a Logic Network, Boolean Algebra, Notation and Terminology,
Precedence of Operations, Synthesis Using NAD, OR, and NOT Gates, Sum-of-
1 Products and Product-of-Sums Forms, NAND and NOR Logic Networks, Design
Examples, Three-Way Light Control, Multiplexer Circuit, Introduction to Verilog,
Structural Specification of Logic Circuits, Behavioral Specification of Logic
Circuits
Implementation Technology: Transistor Switches, NMOS Logic Gates, CMOS
Logic Gates, Speed of Logic Gate Circuits, Negative Logic System, Standard
Chips, 7400-Series Standard Chips, Programmable Logic Devices, Programmable
2,3 Logic Array (PLA), Programmable Array Logic (PAL), Complex Programmable
Logic Devices (CPLDs), Field-Programmable Gate Arrays, Practical Aspects, Fan-
in and Fan-out in Logic Gates, Exclusive-OR Gates (using AND-OR-NOT Gates)
Optimized Implementation of Logic Function: Karnaugh Map, Strategy for
Minimization, Terminology, Minimization Procedure, Minimization of Product-of-
4,5 Sums Forms, Incompletely Specified Functions, Multiple-Output Circuits,
Multilevel NAND and NOR Circuits
Number Representation and Arithmetic Circuits: Positional Number
Representation, Unsigned Numbers, Conversion between Decimal and Binary
Systems, Octal and Hexadecimal Representations, Addition of Unsigned Numbers,
Decomposed Full-Adder, Ripple-Carry Adder, Design Example, Singed Numbers,
Negative Numbers, Addition and Subtraction, Adder and Subtractor Unit,
Arithmetic Overflow, Performance Issues, Design of Arithmetic Circuits Using
6,7,8 CAD Tools, Design of Arithmetic Circuits Using Verilog, Using Vectored Signals,
Using a Generic Specification, Nets and Variables in Verilog, Arithmetic
Assignment Statements, Representation of Numbers in Verilog Code, Other
Number Representations, Fixed-Point Numbers, Floating-Point Numbers, Binary-
Coded-Decimal Representation.
Combinational-Circuit Building Blocks: Multiplexers, Synthesis of Logic
Functions Using Multiplexers, Multiplexer Synthesis Using Shannons Expansion
(before Shannons Theorem), Decoders, Demultiplexers, Encoders, Binary
Encoders, Priority Encoders, Code Converters, Arithmetic Comparison Circuits,
9, 10 Verilog for Combinational Circuits, The Conditional Operator, The If-Else
Statement, The Case Statement, The For Loop, Verilog Operators, The Generate
Construct, Tasks and Functions.
Flip-Flops, Registers, Counters, and a Simple Processor: Basic Latch, Gated
SR Latch, Gated SR Latch with NAND Gates, Gated D Latch, Effects of
Propagation Delays, Master-Slave and Edge-Triggered D Flip-Flops, Master-Slave
D Flip-Flop, Edge-Triggered D Flip-Flop, D Flip-Flops with Clear and Preset, T
Flip-Flop, Configurable Flip-Flops, JK Flip-Flop, Registers, Shift Register,
Parallel-Access Shift Register, Counters, Asynchronous Counters, Synchronous
11,12,13 Counters, Counters with Parallel Load, Reset Synchronization, Other Types of
Counters, BCD Counter, Ring Counter, Johnson Counter, Using Storage Elements
with CAD Tools, Using Verilog Constructs for Storage Elements, Blocking and
Non-Blocking Statements, Non-Blocking Assignments for Combinational Circuits,
Flip-Flops with Clear Capability, Using Registers and Counters with CAD Tools,
Using Verilog Construct for Registers and Counters.
Topics will be covered:
Chapter 2: Introduction to Logic Circuits
2.1 Variables and Functions
2.2 Inversion
2.3 Truth Table
2.4 Logic Gates and Networks
2.4.1 Analysis of a Logic Network
2.5 Boolean Algebra
2.5.2 Notation and Terminology
2.5.3 Precedence of Operations
2.6 Synthesis Using AND, OR, and NOT Gates
2.6.1 Sum-of-Products and Product-of-Sums Forms
2.7 NAND and NOR Logic Networks
2.8 Design Examples
2.8.1 Three-Way Light Control
2.8.2 Multiplexer Circuit

Chapter 4: Optimized Implementation of Logic Function

4.1 Karnaugh Map
4.2 Strategy for Minimization
4.2.1 Terminology
4.3 Minimization of Product-of-Sums Forms
4.4 Incompletely Specified Functions
4.5 Multiple-Output Circuits

4.6.3 Multilevel NAND and NOR Circuits

2.10 Introduction to Verilog

2.10.1 Structural Specification of Logic Circuits
2.10.2 Behavioral Specification of Logic Circuits

Chapter 5: Number Representation and Arithmetic Circuits

5.1 Positional Number Representation
5.1.1 Unsigned Numbers
5.1.2 Conversion between Decimal and Binary Systems
5.1.3 Octal and Hexadecimal Representations
5.2 Addition of Unsigned Numbers
5.2.1 Decomposed Full-Adder
5.2.2 Ripple-Carry Adder
5.2.3 Design Example
5.3 Singed Numbers
5.3.1 Negative Numbers
5.3.2 Addition and Subtraction
5.3.3 Adder and Subtractor Unit
5.3.5 Arithmetic Overflow
5.3.6 Performance Issues

5.5.2 Design of Arithmetic Circuits Using Verilog

5.5.3 Using Vectored Signals
5.5.4 Using a Generic Specification
5.5.5 Nets and Variables in Verilog
5.5.6 Arithmetic Assignment Statements
 5.5.7 Representation of Numbers in Verilog Code
5.7 Other Number Representations
5.7.1 Fixed-Point Numbers
5.7.2 Floating-Point Numbers
5.7.3 Binary-Coded-Decimal Representation

Chapter 6: Combinational-Circuit Building Blocks

6.1 Multiplexers
6.1.1 Synthesis of Logic Functions Using Multiplexers
6.1.2 Multiplexer Synthesis Using Shannons Expansion (before Shannons Theorem)
6.2 Decoders
6.2.1 Demultiplexers
6.3 Encoders
6.3.1 Binary Encoders
6.3.2 Priority Encoders
6.4 Code Converters
6.5 Arithmetic Comparison Circuits
6.6 Verilog for Combinational Circuits
6.6.1 The Conditional Operator
6.6.2 The If-Else Statement
6.6.3 The Case Statement
6.6.4 The For Loop
6.6.5 Verilog Operators
6.6.6 The Generate Construct
6.6.7 Tasks and Functions

Chapter 7: Flip-Flops, Registers, Counters, and a Simple Processor

7.1 Basic Latch
7.2 Gated SR Latch
7.2.1 Gated SR Latch with NAND Gates
7.3 Gated D Latch
7.3.1 Effects of Propagation Delays
7.4 Master-Slave and Edge-Triggered D Flip-Flops
7.4.1 Master-Slave D Flip-Flop
7.4.2 Edge-Triggered D Flip-Flop
7.4.3 D Flip-Flops with Clear and Preset
7.5 T Flip-Flop
7.5.1 Configurable Flip-Flops
7.6 JK Flip-Flop
7.8 Registers
7.8.1 Shift Register
7.8.2 Parallel-Access Shift Register
7.9 Counters
7.9.1 Asynchronous Counters
7.9.2 Synchronous Counters
7.9.3 Counters with Parallel Load
7.10 Reset Synchronization
7.11 Other Types of Counters
7.11.1 BCD Counter
7.11.2 Ring Counter
7.11.3 Johnson Counter
7.12 Using Storage Elements with CAD Tools
7.12.2 Using Verilog Constructs for Storage Elements
7.12.3 Blocking and Non-Blocking Statements
7.12.4 Non-Blocking Assignments for Combinational Circuits
7.12.5 Flip-Flops with Clear Capability
7.13 Using Registers and Counters with CAD Tools
7.13.2 Using Library Modules in Verilog Code
7.13.3 Using Verilog Construct for Registers and Counters

Chapter 3: Implementation Technology

3.1 Transistor Switches
3.2 NMOS Logic Gates
3.3 CMOS Logic Gates
3.3.1 Speed of Logic Gate Circuits
3.4 Negative Logic System
3.5 Standard Chips
3.5.1 7400-Series Standard Chips
3.6 Programmable Logic Devices
3.6.1 Programmable Logic Array (PLA)
3.6.2 Programmable Array Logic (PAL)
3.6.4 Complex Programmable Logic Devices (CPLDs)
3.6.5 Field-Programmable Gate Arrays
3.7 Custom Chips, Standard Cells, and Gate Arrays
3.8 Practical Aspects
3.8.1 MOSFET Fabrication and Behavior
3.8.2 MOSFET On Resistance
3.8.3 Voltage Levels in Logic Gates
3.8.4 Noise Margin
3.8.5 Dynamic Operation of Logic Gates
3.8.6 Power Dissipation Logic Gates
3.8.7 Passing 1s and 0s Through Transistor Switches
3.8.8 Fan-in and Fan-out in Logic Gates
3.9 Transmission Gates
3.9.1 Exclusive-OR Gates (using AND-OR-NOT Gates)
3.9.2 Multiplexer Circuit