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Alright, in need of your major help and hoping you allow yourselves to feel good enough
to help me.Alright allow me to get to it.
land your next job.
Writing a program code for a multifunction calculator system using a CPLD and VHDL.
4 additional functions need to be added to the calculator by using '0' as a shift function.
The function +, -, /, x.
So far all the code written up is as follows.Feel good enough to check it and help me add to it, thank you very much.
DEBOUNCING BEHAVIOR
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:35:19 02/01/2009
-- Design Name:
-- Module Name: debounce - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity debounce is
Port ( clock : in std_logic;
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Using CPLD and VHDL to write a code for a multifunction Calculator | Physics Forums - The Fusion of Science and Community 30/4/17, 4)41 am
begin
milli_s_period: process(clock)
variable cnt: std_logic_vector (14 downto 0);
begin
if rising_edge(clock) then
end if;
end process;
debounce: process(clk)
begin
if rising_edge(clk) then
keyout <= keyin;
end if;
end process;
end behaviour;
DISPLAYING TEXT
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:23:33 02/01/2009
-- Design Name:
-- Module Name: display - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity display is
Port (
input : in STD_LOGIC_VECTOR (3 downto 0);
output : out STD_LOGIC_VECTOR (6 downto 0));
end display;
architecture a of display is
begin
process(input)
begin
-- if rising_edge(clk) then
case input is
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Using CPLD and VHDL to write a code for a multifunction Calculator | Physics Forums - The Fusion of Science and Community 30/4/17, 4)41 am
end case;
-- end if;
end process;
end a;
DISPLAYING TB.VHDL[1]
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:38:01 02/09/2009
-- Design Name:
-- Module Name: L:/calcutator/keypad/display_tb.vhd
-- Project Name: keypad
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: display
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY display_tb IS
END display_tb;
COMPONENT display
PORT(
input : IN std_logic_vector(3 downto 0);
output : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
--Inputs
signal input : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal output : std_logic_vector(6 downto 0);
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BEGIN
<clock>_process :process
begin
<clock> <= '0';
wait for <clock>_period/2;
<clock> <= '1';
wait for <clock>_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100ms.
wait for 100ms;
wait;
end process;
END;
KEYPAD[1]
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:36:44 02/01/2009
-- Design Name:
-- Module Name: keypad - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
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Using CPLD and VHDL to write a code for a multifunction Calculator | Physics Forums - The Fusion of Science and Community 30/4/17, 4)41 am
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY keypad IS
PORT(
clk : IN STD_LOGIC;
resetn : IN STD_LOGIC;
row : IN STD_LOGIC_VECTOR(3 downto 0);
col : OUT STD_LOGIC_VECTOR(3 downto 0);
keyvalue_registered : OUT STD_LOGIC_VECTOR(3 downto 0);
keyvalid : OUT STD_LOGIC
);
END keypad;
BEGIN
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Using CPLD and VHDL to write a code for a multifunction Calculator | Physics Forums - The Fusion of Science and Community 30/4/17, 4)41 am
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Using CPLD and VHDL to write a code for a multifunction Calculator | Physics Forums - The Fusion of Science and Community 30/4/17, 4)41 am
-- states to enable the output register to load the detected key on the
-- next rising edge of the clock
when Latch0 =>
state <= Capture0;
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Using CPLD and VHDL to write a code for a multifunction Calculator | Physics Forums - The Fusion of Science and Community 30/4/17, 4)41 am
-- states when the detected key value is loaded into output register
when Capture0 =>
state <= KeyReleaseAssert;
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Using CPLD and VHDL to write a code for a multifunction Calculator | Physics Forums - The Fusion of Science and Community 30/4/17, 4)41 am
END CASE;
END IF;
END PROCESS;
-- enable the counter reset in the state before the counter is to be used
WITH state SELECT
count_resetn <=
'0' WHEN Start_State,
'0' WHEN KeyDetect,
'0' WHEN PrepareDrive,
'0' when Detect1,
'0' when Detect2,
'0' when Detect3,
'0' when Detect4,
'0' when Capture0,
'0' when Capture1,
'0' when Capture2,
'0' when Capture3,
'0' when Capture4,
'0' when Capture5,
'0' when Capture6,
'0' when Capture7,
'0' when Capture8,
'0' when Capture9,
'0' when Capture10,
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Using CPLD and VHDL to write a code for a multifunction Calculator | Physics Forums - The Fusion of Science and Community 30/4/17, 4)41 am
-- assert the register load signal in the state before the keyvalue is to be
-- latched into the output register
with state select
register_load <=
'1' when latch0,
'1' when latch1,
'1' when latch2,
'1' when latch3,
'1' when latch4,
'1' when latch5,
'1' when latch6,
'1' when latch7,
'1' when latch8,
'1' when latch9,
'1' when latch10,
'1' when latch11,
'1' when latch12,
'1' when latch13,
'1' when latch14,
'1' when latch15,
'1' when capture0,
'1' when capture1,
'1' when capture2,
'1' when capture3,
'1' when capture4,
'1' when capture5,
'1' when capture6,
'1' when capture7,
'1' when capture8,
'1' when capture9,
'1' when capture10,
'1' when capture11,
'1' when capture12,
'1' when capture13,
'1' when capture14,
'1' when capture15,
'0' when others;
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Using CPLD and VHDL to write a code for a multifunction Calculator | Physics Forums - The Fusion of Science and Community 30/4/17, 4)41 am
END mixed;
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Using CPLD and VHDL to write a code for a multifunction Calculator | Physics Forums - The Fusion of Science and Community 30/4/17, 4)41 am
KEYPAD TB.VHDL[1]
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:49:31 02/10/2009
-- Design Name:
-- Module Name: L:/calcutator/keypad/keypad_tb.vhd
-- Project Name: keypad
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: keypad
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY keypad_tb IS
END keypad_tb;
COMPONENT keypad
PORT(
clk : IN std_logic;
resetn : IN std_logic;
row : IN std_logic_vector(3 downto 0);
col : OUT std_logic_vector(3 downto 0);
keyvalue_registered : OUT std_logic_vector(3 downto 0);
keyvalid : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal resetn : std_logic := '0';
signal row : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal col : std_logic_vector(3 downto 0);
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BEGIN
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100ms.
wait for 100ms;
wait;
end process;
END;
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