State University of New York at Stony Brook

Department of Electrical and Computer Engineering

ESE 211 Electronics Laboratory A

Lab 11. MOSFET differential amplifier

1. Objectives
Measurements of the frequency response, differential gain, and common mode rejection ratio for
a MOSFET differential amplifier stage with resistive and active loads.

2. Introduction
MOSFETs and BJTs have different amplification principles however their output and transfer
characteristics are similar. Indeed, the MOSFET output current saturates over a wide range of
drain-source voltages; the enhancement mode MOSFETs in the lab kit have a typical threshold
voltage of VT = 0.7 V. In contrast to BJTs, MOSFETs have negligible DC input current, so that
the MOSFET DC current gain can be on the order of millions. A small AC input current exists
due to charging and discharging the device input capacitance. The ability to control the drain
saturation current with the gate-source voltage is described by the transconductance, gm:
I Dsat i
gm = = D (VGS > VT) (1)
VGS vGS
The voltage gain for a MOSFET gain stage with a COMMON SOURCE (CS) configuration is
similar to the COMMON EMITTER configuration for a BJT gain stage:
vOUT
AV = = g m R LOAD (2)
v IN
The minus sign indicates that the output (drain-to-source) voltage is out of phase with respect to
the input (gate-to-source) voltage. The CS differential amplifier to be studied in this experiment
is shown in Figure 1.

R2 V1
5Vdc
AC current
Vout
D
M1 M2 G

n-MOS S
V2
5Vdc
R1 0

Vin

Figure 1.
Resistor R1 and DC voltage source V2 make a constant bias current1: IDsat1 +IDsat2 = const. The
input voltage is applied between the gates. It increases the drain current in one MOSFET at the
expense of the drain current in another MOSFET: IDsat1 = - IDsat2
In the previous experiment with the BJT gain stage you had a resistor in the emitter path to
stabilize the DC current (bias). This resistor was bypassed with a capacitor to obtain a large
voltage gain. The differential stage offers large voltage gain without using the bypassing
capacitor from the source or emitter to ground: the AC current is directed to another transistor
instead. In the circuit in Figure 1, the redistribution of current between M1 and M2 due to the
differential input signal does not change the total current through R1, and the voltage at the
MOSFET sources does not change with the input signal. Thus, the bypassing capacitor is
eliminated and its function is performed by another transistor.
One can place a ground on the gate of the left MOSFET in Figure 1. The output AC voltage will
be out of phase with respect to vIN in accordance with equation (2), i.e the gate of the right
MOSFET in Figure 1 is an inverting input V-.
One can place the ground on the inverting input, then Vout = - IDsat2R2 = +IDsat1R2.
vOUT
= + g m R2 (VGS2 = const) (3)
v IN
In this case the output AC voltage is in phase with vIN , the gate of the left MOSFET is a non-
inverting input V+.
If the same voltage is applied to both inputs simultaneously as shown in Figure 2, the output
voltage should not change. This is one of the most important advantages of the differential
structural design suppression of the common mode signal. It is characterized by the common
mode rejection ratio (CMRR):
vOUT
0 (VIN = V+ = V-) (4)
v IN

R2 V1
5Vdc

Vout

V
M1 M2

Vin n-MOS
1V 0
V2
R1 5Vdc
0

Figure 2.

Thus, the differential gain stage amplifies the voltage difference between the inputs.

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This DC bias current splits equally between transistors M1 and M2 due to their identical parameters. Load resistor
R2 makes almost no difference because of drain current saturation.
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Both parameters, the differential gain and the common mode rejection ratio, are improved by
replacing resistors R1 and R2 with active loads MOSFETs - whose output characteristics show a
large differential resistance in the saturation region.
V DS V
r0 = = A , (5)
I D I Dsat
here VA is the Early voltage parameter.
In this experiment resistor R2 will be replaced with the active load as shown in Figure 3.
Transistor M3 provides a constant bias voltage at the gate of M4.

p-MOS S V1
5Vdc

D
M3 M4 Vout

V
M1 M2

V+ n-MOS V-
1V 0
V2
R1 5Vdc
0 0

Figure 3.
The amplifier with the active load in Figure 3 has the following voltage gain in the differential
mode2
vOUT r
AD = = gm 0 (6)
v+ v 2
Thus, the voltage gain for the stage with the active load in Figure 3 is much larger than one for
the stage with the resistive load in Figure 1.

3. Prelab

Sketch the chip layout and show the wiring connections based on the block diagram and pin
configuration at the end of the assignment.
You must show the prelab work to the TA before starting the experiment.

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The division by 2 originates from the parallel connection of the differential output resistances of M2 and M4 which
are both assumed to be equal to r0. The voltages at both M2 and M4 sources are constant so that they represent an AC
ground.
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 4. Experiment
1. Assemble the circuit in Figure 1 using R1 = 1k and R2 = 2k. Using the DMM
perform measurements of the MOSFET terminal voltages3. From the voltage
measurements find the DC drain current. Show the results to the TA.
2. Measure the dependence of the output AC voltage on input AC voltage at 1 kHz.
Plot the graph and show in to the TA. Determine the range where this dependence
is linear and write down the maximum amplitude of undistorted output voltage.
Do not exceed this value in the frequency response measurements.
3. Perform measurement of the small signal gain in the differential mode at 1 kHz.
Make sure the output AC voltage does not saturate. Use a snap-on 20 dB
attenuator to divide the amplitude of the signal generator. Measure the differential
gain at the following frequencies:
50 kHz, 100 kHz, 200 kHz, 400 kHz, 800 kHz, 1.6 MHz, 3.2 MHz
Use the measured gain data to sketch a Bode magnitude plot. Determine the -3dB
cut-off frequency. Observe the gain decrease with frequency above the cut-off
point at the rate of 6 dB/octave. Calculate the gain-bandwidth product. Show the
result to the TA.
4. Perform measurement of the CMRR with a signal generator voltage of 100 mVpp
at 1 kHz. Measure the CMRR at the frequencies listed in part 3. Calculate the
CMRR in dB. Obtain the Bode plot for CMRR. Make a conclusion about the
change of the CMRR with frequency.
5. Assemble the circuit in Figure 3. Perform the measurements listed in part 3 and
compare the results for the gain stages with the resistive and active loads.
4. Report
The report should include the lab goals, a short description of the work, the experimental
data presented in plots and tables, the data analysis and comparison followed by
conclusions. A summary Bode plot showing the gain frequency response of the
configurations with the resistive and active loads on the same graph may be illuminating.

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the source voltage should be -31V, the voltage at the interconnection of R2 and the drain of the right MOSFET
should be +31V. If your reading is +5 V, -5 V or zero - check the circuit for floating nodes or other problems.
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