MC34071,2,4,A

MC33071,2,4,A

Single Supply 3.0 V to 44 V

Operational Amplifiers
Quality bipolar fabrication with innovative design concepts are
employed for the MC33071/72/74, MC34071/72/74 series of http://onsemi.com
monolithic operational amplifiers. This series of operational
amplifiers offer 4.5 MHz of gain bandwidth product, 13 V/s slew rate
and fast settling time without the use of JFET device technology.
PDIP8
Although this series can be operated from split supplies, it is P SUFFIX
particularly suited for single supply operation, since the common 8
CASE 626
1
mode input voltage range includes ground potential (VEE). With a
Darlington input stage, this series exhibits high input resistance, low
input offset voltage and high gain. The all NPN output stage, SOIC8
characterized by no deadband crossover distortion and large output D SUFFIX
8
voltage swing, provides high capacitance drive capability, excellent CASE 751
phase and gain margins, low open loop high frequency output 1
impedance and symmetrical source/sink AC frequency response.
The MC33071/72/74, MC34071/72/74 series of devices are
available in standard or prime performance (A Suffix) grades and are
specified over the commercial, industrial/vehicular or military PDIP14
temperature ranges. The complete series of single, dual and quad P SUFFIX
CASE 646
operational amplifiers are available in plastic DIP, SOIC and TSSOP 14
surface mount packages. 1

Features SOIC14
D SUFFIX
Wide Bandwidth: 4.5 MHz 14
CASE 751A
High Slew Rate: 13 V/s 1

Fast Settling Time: 1.1 s to 0.1%

Wide Single Supply Operation: 3.0 V to 44 V TSSOP14
Wide Input Common Mode Voltage Range: Includes Ground (VEE) 14
DTB SUFFIX
CASE 948G
Low Input Offset Voltage: 3.0 mV Maximum (A Suffix) 1

Large Output Voltage Swing: 14.7 V to +14 V (with 15 V

Supplies) ORDERING INFORMATION
Large Capacitance Drive Capability: 0 pF to 10,000 pF See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
Low Total Harmonic Distortion: 0.02%
Excellent Phase Margin: 60 DEVICE MARKING INFORMATION
Excellent Gain Margin: 12 dB See general marking information in the device marking
section on page 18 of this data sheet.
Output Short Circuit Protection
ESD Diodes/Clamps Provide Input Protection for Dual and Quad
PbFree Packages are Available

Semiconductor Components Industries, LLC, 2004 1 Publication Order Number:

April, 2004 Rev. 8 MC34071/D
 MC34071,2,4,A MC33071,2,4,A

PIN CONNECTIONS

CASE 626/CASE 751 CASE 646/CASE 751A/CASE 948G

Offset Null 1 8 NC Output 1 1 14 Output 4

2 7 VCC 13
2 1 4
Inputs Inputs 1
Inputs 4
3 + 6 Output + +
3 12
VEE 4 5 Offset Null
VCC 4 11 VEE
(Single, Top View) 3
5
+ 2 + 10
Inputs 2 Inputs 3
Output 1 1 8 VCC 6 9

2

7 Output 2 Output 2 7 8 Output 3
Inputs 1 3
+
6

+ Inputs 2 (Quad, Top View)
VEE 4 5

(Dual, Top View)

VCC
Q3 Q4 Q5 Q6 Q7
Q1
Q17
Q2
R1 C1 R2
D2 Q18
Bias R6 R7
Q8 Q9 Q10 Q11
Output
Inputs R8
+ C2 D3
Q19

Base Q13 Q14 Q15 Q16

Current
Cancellation Q12
Current
D1 Limit
R5

R3 R4

VEE/GND
Offset Null
(MC33071, MC34071 only)

Figure 1. Representative Schematic Diagram

(Each Amplifier)

MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage (from VEE to VCC) VS +44 V
Input Differential Voltage Range VIDR (Note 1) V
Input Voltage Range VIR (Note 1) V
Output Short Circuit Duration (Note 2) tSC Indefinite Sec
Operating Junction Temperature TJ +150 C
Storage Temperature Range Tstg 60 to +150 C
1. Either or both input voltages should not exceed the magnitude of VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 2).

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 MC34071,2,4,A MC33071,2,4,A

ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = 15 V, RL = connected to ground, unless otherwise noted. See Note 3 for
TA = Tlow to Thigh)
A Suffix NonSuffix
Characteristics Symbol Min Typ Max Min Typ Max Unit
Input Offset Voltage (RS = 100 , VCM = 0 V, VO = 0 V) VIO mV

VCC = +15 V, VEE = 15 V, TA = +25C 0.5 3.0 1.0 5.0
VCC = +5.0 V, VEE = 0 V, TA = +25C 0.5 3.0 1.5 5.0
VCC = +15 V, VEE = 15 V, TA = Tlow to Thigh 5.0 7.0
Average Temperature Coefficient of Input Offset
VIO/
T 10 10 V/C
Voltage
RS = 10 , VCM = 0 V, VO = 0 V,
TA = Tlow to Thigh
Input Bias Current (VCM = 0 V, VO = 0 V) IIB nA
TA = +25C 100 500 100 500
TA = Tlow to Thigh 700 700
Input Offset Current (VCM = 0 V, VO = 0V) IIO nA
TA = +25C 6.0 50 6.0 75
TA = Tlow to Thigh 300 300
Input Common Mode Voltage Range VICR V
TA = +25C VEE to (VCC 1.8) VEE to (VCC 1.8)
TA = Tlow to Thigh VEE to (VCC 2.2) VEE to (VCC 2.2)

Large Signal Voltage Gain (VO = 10 V, RL = 2.0 k) AVOL V/mV

TA = +25C 50 100 25 100
TA = Tlow to Thigh 25 20
Output Voltage Swing (VID = 1.0 V) VOH V
VCC = +5.0 V, VEE = 0 V, RL = 2.0 k, TA = +25C 3.7 4.0 3.7 4.0
VCC = +15 V, VEE = 15 V, RL = 10 k, TA = +25C 13.6 14 13.6 14
VCC = +15 V, VEE = 15 V, RL = 2.0 k, 13.4 13.4
TA = Tlow to Thigh

VCC = +5.0 V, VEE = 0 V, RL = 2.0 k, TA = +25C VOL 0.1 0.3 0.1 0.3 V

VCC = +15 V, VEE = 15 V, RL = 10 k, TA = +25C 14.7 14.3 14.7 14.3

VCC = +15 V, VEE = 15 V, RL = 2.0 k, 13.5 13.5

TA = Tlow to Thigh
Output Short Circuit Current (VID = 1.0 V, VO = 0 V, ISC mA
TA = 25C)
Source 10 30 10 30
Sink 20 30 20 30
Common Mode Rejection CMR 80 97 70 97 dB
RS 10 k, VCM = VICR, TA = 25C

Power Supply Rejection (RS = 100 ) PSR 80 97 70 97 dB

VCC/VEE = +16.5 V/16.5 V to +13.5 V/13.5 V,
TA = 25C
Power Supply Current (Per Amplifier, No Load) ID mA
VCC = +5.0 V, VEE = 0 V, VO = +2.5 V, TA = +25C 1.6 2.0 1.6 2.0
VCC = +15 V, VEE = 15 V, VO = 0 V, TA = +25C 1.9 2.5 1.9 2.5
VCC = +15 V, VEE = 15 V, VO = 0 V, 2.8 2.8
TA = Tlow to Thigh
3. Tlow = 40C for MC33071, 2, 4, /A Thigh = +85C for MC33071, 2, 4, /A
= 0C for MC34071, 2, 4, /A = +70C for MC34071, 2, 4, /A
= 40C for MC34072, 4/V = +125C for MC34072, 4/V

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 MC34071,2,4,A MC33071,2,4,A

AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = 15 V, RL = connected to ground. TA = +25C, unless otherwise noted.)
A Suffix NonSuffix
Characteristics Symbol Min Typ Max Min Typ Max Unit
Slew Rate (Vin = 10 V to +10 V, RL = 2.0 k, CL = 500 pF) SR V/s
AV = +1.0 8.0 10 8.0 10
AV = 1.0 13 13
Setting Time (10 V Step, AV = 1.0) ts s
To 0.1% (+1/2 LSB of 9Bits) 1.1 1.1
To 0.01% (+1/2 LSB of 12Bits) 2.2 2.2
Gain Bandwidth Product (f = 100 kHz) GBW 3.5 4.5 3.5 4.5 MHz
Power Bandwidth BW 160 160 kHz
AV = +1.0, RL = 2.0 k, VO = 20 Vpp, THD = 5.0%

Phase margin fm Deg

RL = 2.0 k 60 60
RL = 2.0 k, CL = 300 pF 40 40
Gain Margin Am dB
RL = 2.0 k 12 12
RL = 2.0 k, CL = 300 pF 4.0 4.0
Equivalent Input Noise Voltage en 32 32 nV/ Hz
RS = 100 , f = 1.0 kHz

Equivalent Input Noise Current in 0.22 0.22 pA/ Hz

f = 1.0 kHz

Differential Input Resistance Rin 150 150 M

VCM = 0 V

Differential Input Capacitance Cin 2.5 2.5 pF

VCM = 0 V

Total Harmonic Distortion THD 0.02 0.02 %

AV = +10, RL = 2.0 k, 2.0 Vpp VO 20 Vpp, f = 10 kHz

Channel Separation (f = 10 kHz) 120 120 dB

Open Loop Output Impedance (f = 1.0 MHz) |ZO| 30 30 W

Single Supply Split Supplies

3.0 V to 44 V VCC+|VEE|44 V VCC

VCC VCC
7
2

1 VCC 1 6
3 5
+
2 2 1
4

3 3
10 k

4 VEE 4 VEE

VEE VEE Offset nulling range is approximately 80 mV with a 10 k

potentiometer (MC33071, MC34071 only).

Figure 2. Power Supply Configurations Figure 3. Offset Null Circuit

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 MC34071,2,4,A MC33071,2,4,A

2400
D MAXIMUM POWER DISSIPATION (mW) 4.0 VCC = +15 V

V IO INPUT OFFSET VOLTAGE (mV)

2000 VEE = 15 V
VCM = 0
2.0
1600
SOIC14 Pkg 8 & 14 Pin Plastic Pkg
1200 0

800
2.0
SOIC8 Pkg
400

V
,
4.0
P


,

0
55 40 20 0 20 40 60 80 100 120 140 160 55 25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (C) TA, AMBIENT TEMPERATURE (C)

Figure 4. Maximum Power Dissipation versus Figure 5. Input Offset Voltage versus
Temperature for Package Types Temperature for Representative Units

ICR INPUT COMMON MODE VOLTAGE RANGE (V)

VCC 1.3

IB INPUT BIAS CURRENT (NORMALIZED)

VCC VCC/VEE = +1.5 V/ 1.5 V to +22 V/ 22 V VCC = +15 V
1.2 VEE = 15 V
VCC 0.8
VCM = 0
1.1
VCC 1.6
1.0
VCC 2.4
0.9

VEE +0.01 0.8

VEE
I,
V


,

VEE 0.7
55 25 0 25 50 75 100 125 55 25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (C) TA, AMBIENT TEMPERATURE (C)

Figure 6. Input Common Mode Voltage Figure 7. Normalized Input Bias Current
Range versus Temperature versus Temperature
IB INPUT BIAS CURRENT (NORMALIZED)

1.4 50
VCC = +15 V RL Connected
VO, OUTPUT VOLTAGE SWING (Vpp )

VEE = 15 V to Ground TA = 25C

40
1.2 TA = 25C

30
RL = 10 k RL = 2.0 k
1.0
20

0.8
10
I,

0.6 0
12 8.0 4.0 0 4.0 8.0 12 0 5.0 10 15 20 25
VIC, INPUT COMMON MODE VOLTAGE (V) VCC, |VEE|, SUPPLY VOLTAGE (V)

Figure 8. Normalized Input Bias Current versus Figure 9. Split Supply Output Voltage
Input Common Mode Voltage Swing versus Supply Voltage

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 MC34071,2,4,A MC33071,2,4,A

VCC VCC
Vsat , OUTPUT SATURATION VOLTAGE (V)

Vsat , OUTPUT SATURATION VOLTAGE (V)

VCC/VEE = +5.0 V/ 5.0 V to +22 V/ 22 V VCC
VCC TA = 25C
VCC 1.0 VCC2.0
VCC = +15 V
Source RL = GND
VCC 2.0 VCC4.0 TA = 25C

VEE +2.0 0.2

VEE +1.0 Sink 0.1

VEE GND
VEE 0
0 5.0 10 15 20 100 1.0 k 10 k 100 k
IL, LOAD CURRENT ( mA) RL, LOAD RESISTANCE TO GROUND ()

Figure 10. Single Supply Output Saturation Figure 11. Split Supply Output Saturation
versus Load Resistance to VCC versus Load Current

0 60
Vsat , OUTPUT SATURATION VOLTAGE (V)

VCC
50

SC OUTPUT CURRENT (mA)

0.4 Sink
40
0.8
Source
30
2.0
VCC = +15 V 20
RL to VCC VCC = +15 V
TA = 25C
I

,

1.0 VEE = 15 V
10
GND RL 0.1 

Vin = 1.0 V
0
100 1.0 k 10 k 100 k 55 25 0 25 50 75 100 125
RL, LOAD RESISTANCE TO VCC () TA, AMBIENT TEMPERATURE (C)

Figure 12. Single Supply Output Saturation Figure 13. Output Short Circuit Current
versus Load Resistance to Ground versus Temperature

50 28
VCC = +15 V
VCC = +15 V
VO, OUTPUT VOLTAGE SWING (Vpp )

VEE = 15 V 24
O OUTPUT IMPEDANCE ()

40 VEE = 15 V

VCM = 0
VO = 0 AV = +1.0
20

IO = 0.5 mA RL = 2.0 k
30 TA = 25C THD 1.0%
16 TA = 25C

20 12

AV = 1000 AV = 100 AV = 10 AV = 1.0 8.0

10
Z
,

4.0

0 0
1.0 k 10 k 100 1.0 M 10 M 3.0 k 10 k 30 k 100 k 300 k 1.0 M 3.0 M
f, FREQUENCY (Hz) f, FREQUENCY (Hz)

Figure 14. Output Impedance Figure 15. Output Voltage Swing

versus Frequency versus Frequency

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 MC34071,2,4,A MC33071,2,4,A

0.4 4.0
THD, TOTAL HARMONIC DISTORTION (%)

THD, TOTAL HARMONIC DISTORTION (%)

AV = 1000 VCC = +15 V
VEE = 15 V
0.3 3.0 AV = 1000 RL = 2.0 k
TA = 25C
VCC = +15 V
VEE = 15 V
0.2 VO = 2.0 Vpp 2.0
RL = 2.0 k
TA = 25C AV = 100
AV = 100
0.1 1.0 AV = 10
AV = 10
AV = 1.0
AV = 1.0
0 0
10 100 1.0 k 10 k 100 k 0 4.0 8.0 12 16 20
f, FREQUENCY (Hz) VO, OUTPUT VOLTAGE SWING (Vpp)

Figure 16. Total Harmonic Distortion Figure 17. Total Harmonic Distortion
versus Frequency versus Output Voltage Swing

116 100
VOL OPEN LOOP VOLTAGE GAIN (dB)

VOL OPEN LOOP VOLTAGE GAIN (dB)

0
VCC = +15 V

, EXCESS PHASE (DEGREES)

112 80
VEE = 15 V Gain
VO= 10 V to +10 V Phase 45
108 RL = 10 k 60
f 10Hz Phase
Margin 90
104 40 = 60
VCC = +15 V 135
VEE = 15 V
100 20 VO = 0 V
A


,

A


,

RL = 2.0 k
180
TA = 25C
96 0
55 25 0 25 50 75 100 125 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M
TA, AMBIENT TEMPERATURE (C) f, FREQUENCY (Hz)

Figure 18. Open Loop Voltage Gain Figure 19. Open Loop Voltage Gain and
versus Temperature Phase versus Frequency
GBW, GAIN BANDWIDTH PRODUCT (NORMALIED)

20 1.15
VOL OPEN LOOP VOLTAGE GAIN (dB)

1 100
Phase VCC = +15 V
10 Margin = 60 1.1 VEE = 15 V
, EXCESS PHASE (DEGREES)

Gain 120 RL = 2.0 k

0 Margin = 12 dB
1.05
140
10 1.0
1. Phase RL = 2.0 k
160
2. Phase RL = 2.0 k, CL = 300 pF 3
20 3. Gain RL = 2.0 k 0.95
4. Gain RL = 2.0 k, CL = 300 pF 180
4
30 VCC = +15 V
A


,

0.9
VEE = 15 V 2
VO = 0 VTA = 25C
40 0.85
1.0 2.0 3.0 5.0 7.0 10 20 30 55 25 0 25 50 75 100 125
f, FREQUENCY (MHz) TA, AMBIENT TEMPERATURE (C)

Figure 20. Open Loop Voltage Gain and Figure 21. Normalized Gain Bandwidth
Phase versus Frequency Product versus Temperature

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 MC34071,2,4,A MC33071,2,4,A

100 70
VCC = +15 V

m , PHASE MARGIN (DEGREES)

60 VCC = +15 V
80 VEE = 15 V VEE = 15 V
PERCENT OVERSHOOT

RL = 2.0 k AV = +1.0
50
VO = 10 V to +10 V RL = 2.0 k to

60 TA = 25C VO = 10 V to +10 V
40
TA = 25C
30
40
20
20
10

0 0
10 100 1.0 k 10 k 10 100 1.0 k 10 k
CL, LOAD CAPACITANCE (pF) CL, LOAD CAPACITANCE (pF)

Figure 22. Percent Overshoot versus Figure 23. Phase Margin versus
Load Capacitance Load Capacitance

14 80

m , PHASE MARGIN (DEGREES)

12 VCC = +15 V
CL = 10 pF
VEE = 15 V
m GAIN MARGIN (dB)

AV = +1.0 60 CL = 100 pF
10
RL = 2.0 k to
VO = 10 V to +10 V
8.0 TA = 25C VCC = +15 V
40 VEE = 15 V
6.0 AV = +1.0
RL = 2.0 k to
A,

4.0 CL = 1,000 pF VO = 10 V to +10 V

20
2.0 CL = 10,000 pF

0 0
10 100 1.0 k 10 k 55 25 0 25 50 75 100 125
CL, LOAD CAPACITANCE (pF) TA, AMBIENT TEMPERATURE (C)

Figure 24. Gain Margin versus Load Capacitance Figure 25. Phase Margin versus Temperature

16 12 70
VCC = +15 V
m , PHASE MARGIN (DEGREES)
10 60
CL = 10 pF Gain
m GAIN MARGIN (dB)

m GAIN MARGIN (dB)

12 VEE = 15 V 8.0 50
AV = +1.0 R1
VO
RL = 2.0 k to
6.0 + 40
VO = 10 V to +10 V CL = 100 pF
8.0 R2
4.0 30
VCC = +15 V
VEE = 15 V
A,

CL = 10,000 pF
A,

2.0 RT = R1 + R2 20
4.0 CL = 1,000 pF Phase
AV = +100
0 VO = 0 V 10
TA = 25C
0 0
55 25 0 25 50 75 100 125 1.0 10 100 1.0 k 10 k 100 k
TA, AMBIENT TEMPERATURE (C) RT, DIFFERENTIAL SOURCE RESISTANCE ()

Figure 26. Gain Margin versus Temperature Figure 27. Phase Margin and Gain Margin
versus Differential Source Resistance

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 MC34071,2,4,A MC33071,2,4,A

O OUTPUT VOLTAGE SWING FROM 0 V (V)

1.15 10
VCC = +15 V VCC = +15 V
1.0 mV
SR, SLEW RATE (NORMALIZED)
1.1 VEE = 15 V 10 mV 1.0 mV VEE = 15 V
AV = +1.0 5.0 AV = 1.0
RL = 2.0 k TA = 25C
1.05
CL = 500 pF
Compensated
1.0 0
Uncompensated
0.95
5.0 1.0 mV
0.9 10 mV
1.0 mV

V,
0.85 10
55 25 0 25 50 75 100 125 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
TA, AMBIENT TEMPERATURE (C) ts, SETTLING TIME (s)

Figure 28. Normalized Slew Rate Figure 29. Output Settling Time
versus Temperature

VCC = +15 V
VEE = 15 V
AV = +1.0
RL = 2.0 k
50 mV/DIV

CL = 300 pF
5.0 V/DIV

0 0 TA = 25C
VCC = +15 V
VEE = 15 V
AV = +1.0
RL = 2.0 k
CL = 300 pF
TA = 25C

2.0 s/DIV 1.0 s/DIV

Figure 30. Small Signal Transient Response Figure 31. Large Signal Transient Response

100 100
CMR, COMMON MODE REJECTION (dB)

TA = 125C VCC = +15 V

PSR, POWER SUPPLY REJECTION (dB)

VCC = +15 V
TA = 25C VEE = 15 V VEE = 15 V
80 VCM = 0 V 80 TA = 25C
TA = 55C
VCM = 1.5 V
VCC
(
VCC = +1.5 V)
60 60 ADM
VO
+

VEE
40 40
VO/ADM
+PSR

VCM ADM
VO +PSR = 20 Log
+
VCC
20 20

VCM
VO/ADM
CMR = 20 Log x ADM PSR = 20 Log PSR

VO
VEE (
VEE = +1.5 V)
0 0
0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz) f, FREQUENCY (Hz)

Figure 32. Common Mode Rejection Figure 33. Power Supply Rejection
versus Frequency versus Frequency

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 MC34071,2,4,A MC33071,2,4,A

9.0 105

PSR, POWER SUPPLY REJECTION (dB)

PSR (
VEE = +1.5 V) VCC = +15 V
TA = 55C
CC , SUPPLY CURRENT (mA)

8.0 VEE = 15 V
95

7.0 +PSR (
VCC = +1.5 V)

TA = 25C
85
6.0
VCC

VO/ADM
TA = 125C +PSR = 20 Log

VCC ADM
VO
75
I

+
5.0
VO/ADM
PSR = 20 Log
VEE

VEE
4.0 65
0 5.0 10 15 20 25 55 25 0 25 50 75 100 125
VCC, |VEE|, SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (C)

Figure 34. Supply Current versus Figure 35. Power Supply Rejection
Supply Voltage versus Temperature

120 70 2.8

n INPUT NOICE VOLTAGE ( nV Hz
)

n INPUT NOISE CURRENT (pA Hz )

VCC = +15 V
100 VCC = +15 V 60 VEE = 15 V 2.4
CHANNEL SEPARATION (dB)

VEE = 15 V VCM = 0
TA = 25C 50 TA = 25C 2.0
80
40 1.6
60 Voltage
30 1.2
40
20 Current 0.8
20 10 0.4
e

,

i,
0 0 0
10 20 30 50 70 100 200 300 10 100 1.0 k 10 k 100 k
f, FREQUENCY (kHz) f, FREQUENCY (kHz)

Figure 36. Channel Separation versus Frequency Figure 37. Input Noise versus Frequency

APPLICATIONS INFORMATION
CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of the up to approximately 5.0 mA of current from VEE through
MC34071 amplifier series are similar to op amp products either inputs clamping diode without damage or latching,
utilizing JFET input devices, these amplifiers offer other although phase reversal may again occur.
additional distinct advantages as a result of the PNP If one or both inputs exceed the upper common mode
transistor differential input stage and an all NPN transistor voltage limit, the amplifier output is readily predictable and
output stage. may be in a low or high state depending on the existing input
Since the input common mode voltage range of this input bias conditions.
stage includes the VEE potential, single supply operation is Since the input capacitance associated with the small
feasible to as low as 3.0 V with the common mode input geometry input device is substantially lower (2.5 pF) than
voltage at ground potential. the typical JFET input gate capacitance (5.0 pF), better
The input stage also allows differential input voltages up frequency response for a given input source resistance can
to 44 V, provided the maximum input voltage range is not be achieved using the MC34071 series of amplifiers. This
exceeded. Specifically, the input voltages must range performance feature becomes evident, for example, in fast
between VEE and VCC supply voltages as shown by the settling DtoA current to voltage conversion applications
maximum rating table. In practice, although not where the feedback resistance can form an input pole with
recommended, the input voltages can exceed the VCC the input capacitance of the op amp. This input pole creates
voltage by approximately 3.0 V and decrease below the VEE a 2nd order system with the single pole op amp and is
voltage by 0.3 V without causing product damage, although therefore detrimental to its settling time. In this context,
output phase reversal may occur. It is also possible to source lower input capacitance is desirable especially for higher

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 MC34071,2,4,A MC33071,2,4,A
values of feedback resistances (lower current DACs). This
input pole can be compensated for by creating a feedback
zero with a capacitance across the feedback resistance, if
necessary, to reduce overshoot. For 2.0 k of feedback
resistance, the MC34071 series can settle to within 1/2 LSB
of 8bits in 1.0 s, and within 1/2 LSB of 12bits in 2.2 s
for a 10 V step. In a inverting unity gain fast settling
configuration, the symmetrical slew rate is 13 V/s. In the
classic noninverting unity gain configuration, the output
positive slew rate is +10 V/s, and the corresponding
negative slew rate will exceed the positive slew rate as a
function of the fall time of the input waveform.
Since the bipolar input device matching characteristics
are superior to that of JFETs, a low untrimmed maximum
offset voltage of 3.0 mV prime and 5.0 mV downgrade can
be economically offered with high frequency performance
characteristics. This combination is ideal for low cost
precision, high speed quad op amp applications.
The all NPN output stage, shown in its basic form on the
equivalent circuit schematic, offers unique advantages over
the more conventional NPN/PNP transistor Class AB output
stage. A 10 k load resistance can swing within 1.0 V of the
positive rail (VCC), and within 0.3 V of the negative rail
(VEE), providing a 28.7 Vpp swing from 15 V supplies.
This large output swing becomes most noticeable at lower
supply voltages.
The positive swing is limited by the saturation voltage of
the current source transistor Q7, and VBE of the NPN pull up
transistor Q17, and the voltage drop associated with the short
circuit resistance, R7. The negative swing is limited by the
saturation voltage of the pulldown transistor Q16, the
voltage drop ILR6, and the voltage drop associated with
resistance R7, where IL is the sink load current. For small
valued sink currents, the above voltage drops are negligible,
allowing the negative swing voltage to approach within
millivolts of VEE. For large valued sink currents (>5.0 mA),
diode D3 clamps the voltage across R6, thus limiting the
negative swing to the saturation voltage of Q16, plus the
forward diode drop of D3 (VEE +1.0 V). Thus for a given
supply voltage, unprecedented peaktopeak output voltage
swing is possible as indicated by the output swing
specifications.
If the load resistance is referenced to VCC instead of
ground for single supply applications, the maximum
possible output swing can be achieved for a given supply
voltage. For light load currents, the load resistance will pull
the output to VCC during the positive swing and the output
will pull the load resistance near ground during the negative
swing. The load resistance value should be much less than
that of the feedback resistance to maximize pull up
capability.
Because the PNP output emitterfollower transistor has
been eliminated, the MC34071 series offers a 20 mA
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11
minimum current sink capability, typically to an output
voltage of (VEE +1.8 V). In single supply applications the
output can directly source or sink base current from a
common emitter NPN transistor for fast high current
switching applications.
In addition, the all NPN transistor output stage is
inherently fast, contributing to the bipolar amplifiers high
gain bandwidth product and fast settling capability. The
associated high frequency low output impedance (30  typ
@ 1.0 MHz) allows capacitive drive capability from 0 pF to
10,000 pF without oscillation in the unity closed loop gain
configuration. The 60 phase margin and 12 dB gain margin
as well as the general gain and phase characteristics are
virtually independent of the source/sink output swing
conditions. This allows easier system phase compensation,
since output swing will not be a phase consideration. The
high frequency characteristics of the MC34071 series also
allow excellent high frequency active filter capability,
especially for low voltage single supply applications.
Although the single supply specifications is defined at
5.0 V, these amplifiers are functional to 3.0 V @ 25C
although slight changes in parametrics such as bandwidth,
slew rate, and DC gain may occur.
If power to this integrated circuit is applied in reverse
polarity or if the IC is installed backwards in a socket, large
unlimited current surges will occur through the device that
may result in device destruction.
Special static precautions are not necessary for these
bipolar amplifiers since there are no MOS transistors on the
die.
As with most high frequency amplifiers, proper lead
dress, component placement, and PC board layout should be
exercised for optimum frequency performance. For
example, long unshielded input or output leads may result in
unwanted inputoutput coupling. In order to preserve the
relatively low input capacitance associated with these
amplifiers, resistors connected to the inputs should be
immediately adjacent to the input pin to minimize additional
stray input capacitance. This not only minimizes the input
pole for optimum frequency response, but also minimizes
extraneous pick up at this node. Supply decoupling with
adequate capacitance immediately adjacent to the supply pin
is also important, particularly over temperature, since many
types of decoupling capacitors exhibit great impedance
changes over temperature.
The output of any one amplifier is current limited and thus
protected from a direct short to ground. However, under
such conditions, it is important not to allow the device to
exceed the maximum junction temperature rating. Typically
for 15 V supplies, any one output can be shorted
continuously to ground without exceeding the maximum
temperature rating.
 MC34071,2,4,A MC33071,2,4,A

(Typical Single Supply Applications VCC = 5.0 V)

VCC

5.1 M VO
0 3.7 Vpp
VCC 0 3.7 Vpp

20 k 1.0 M 100 k
Cin
+ CO VO
MC34071
68 k
+
36.6 mVpp Cin 10 k MC34071 VO
Vin 100 k CO
10 k 10 k
RL 100 k RL
Vin 370 mVpp
1.0 k AV = 101
BW (3.0 dB) = 45 kHz AV = 10 BW (3.0 dB) = 450 kHz

Figure 38. AC Coupled Noninverting Amplifier Figure 39. AC Coupled Inverting Amplifier

VO
4.75 Vpp VCC
2.63 V
91 k
5.1 k
RL
5.1 k
+ 2.5 V
MC34071 VO
100 k
0 0 to 10,000 pF
Vin + MC54/74XX
1.0 M MC34071
Cable TTL Gate
Vin AV = 10
BW (3.0 dB) = 450 kHz

Figure 40. DC Coupled Inverting Amplifier Figure 41. Unity Gain Buffer TTL Driver
Maximum Output Swing

C R3
0.047 2.2 k
R1
Vin
1.1 k C MC34071 VO
R2 0.047 +
VCC
Vin 0.2 Vdc 5.6 k fo = 30 kHz
VO Ho = 10
MC34071
0.4 VCC Ho = 1.0
R R
Vin + Given fo = Center Frequency
16 k 16 k AO = Gain at Center Frequency
C Choose Value fo, Q, Ao, C
0.01
Then: Q R3 R1 R3
R3 =  R1 =  R2 =
fo = 1.0 kHz foC 2Ho 4Q2R1R3
32 k 2.0 R
1 Qofo
fo = For less than 10% error from operational amplifier < 0.1
4RC GBW
2.0 C 2.0 C where fo and GBW are expressed in Hz.
0.02 0.02 GBW = 4.5 MHz Typ.

Figure 42. Active HighQ Notch Filter Figure 43. Active Bandpass Filter

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 MC34071,2,4,A MC33071,2,4,A

CF Vin

2.0 V
RF Vin
+ VO
5.0 k 5.0 k 5.0 k MC34071 t
VO
MC34071 2.0 k VO
10 k 10 k 10 k + VCC RL
1.0 V 0.2 s
4.0 V Delay
Bit 13 V/s
Switches 25 V/s
(R2R) Ladder Network
0.1 t
Settling Time Delay
1.0 s (8Bits, 1/2 LSB) 1.0 s

Figure 44. Low Voltage Fast D/A Converter Figure 45. High Speed Low Voltage Comparator

VCC
ON"
Vin < Vref
VCC
VCC

Vin + RL
MC34071
+ +
Vref MC34071 MC34071

ON"
Vin > Vref RL

(A) PNP (B) NPN

Figure 46. LED Driver Figure 47. Transistor Driver

ILoad

RF
+
MC34071 VO

Ground Current RS
Sense Resistor ICell
R1 MC34071 VO
+
R2 R1
VO = ILoad RS 1+
R2
For VO > 0.1V
VCell = 0 V
R2 VO = ICell RF
BW ( 3.0 dB) = GBW
R1+R2 VO > 0.1 V

Figure 48. AC/DC Ground Current Monitor Figure 49. Photovoltaic Cell Amplifier

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 MC34071,2,4,A MC33071,2,4,A

VO Hysteresis
R2

Vref R1 VOH
+ Iout
MC34071 VOL
Vin
Vin +
Vin
VinL VinH MC34071
R1 Vref
VinL = (VOLVref)+Vref
R1+R2
R1
VinH = (VOHVref)+Vref
R1+R2
R1 VinVIO R
VH = (VOH VOL) Iout =
R1+R R

Figure 50. Low Input Voltage Comparator Figure 51. High Compliance Voltage to
with Hysteresis Sink Current Converter

R1 R2
R4 +Vref
RF
1/2 R3
1/2 R R
MC34072 VO
+V1 + MC34072
VO
+ MC34071
+V2 R +
R =
R
R2 R4
= (Critical to CMRR)
R1 R3

R RF
R4 R4 VO = Vref
VO = 1 + V2V1 RF 2R2
R3 R3
R < < R
For (V2 V1), V > 0 RF > > R (VO 0.1 V)

Figure 52. High Input Impedance Figure 53. Bridge Current Amplifier
Differential Amplifier

fOSC  0.85
RC + IB +
V
ISC
VP 0 t
Vin
+ VO = Vin (pk) t Base Charge
MC34071
Removal

Iout

1/2 R + 1/2
+ MC34072 MC34072
RL VP 10,000 pF C + IB

V+ 100 k
100 k VP Pulse Width
Vin 47 k Control Group
VP

OSC Comparator High Current

t Output

Figure 54. Low Voltage Peak Detector Figure 55. High Frequency Pulse
Width Modulation

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 MC34071,2,4,A MC33071,2,4,A

GENERAL ADDITIONAL APPLICATIONS INFORMATION VS = 15.0 V

C2 C2 R1
0.02 0.05 C1 46.1 k
1.0
R2
R1 R3 5.6 k C1 MC34071
560 510
1.0 R2 + fo = 100 Hz
1.1 k Ho = 20
MC34071
C1 fo = 1.0 kHz
0.44 +
Ho = 10 Ho+0.5
Choose: fo, Ho, C1 Then: R1 =
Choose: fo, Ho, C2 foC1 2
2
Then: C1 = 2C2 (Ho+1) R2 =
2foC1 (1/Ho+2)
2 R2 R2 C
R2 = R3 = R1 = C2 =
4foC2 Ho+1 Ho Ho

Figure 56. Second Order LowPass Active Filter Figure 57. Second Order HighPass Active Filter

CF*

VO = 10 V
RF Step

2.0 k

+

MC34071 VO
MC34071 VO R1
RL
+
I Vin R2
ts = 1.0 s
Uncompensated
to 1/2 LSB (8Bits)
ts = 2.2 s VO
High Speed Compensated R2 R1
DAC to 1/2 LSB (12Bits) = BW (3.0 dB) = GBW
Vin R1 R1 +R2

*Optional Compensation SR = 13 V/s SR = 13 V/s

Figure 58. Fast Settling Inverter Figure 59. Basic Inverting Amplifier

+
MC34071 VO

Vin
R2 Vin +
MC34071 VO
RL

R1
VO R2
= 1+
Vin R1
BWp = 200 kHz
R1 VO = 20 Vpp
BW (3.0 dB) = GBW
R1 +R2 SR = 10 V/s

Figure 60. Basic Noninverting Amplifier Figure 61. Unity Gain Buffer (AV = +1.0)

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 MC34071,2,4,A MC33071,2,4,A

+ R
R
MC34074

R

RE MC34074 VO

R +

R Example:
MC34074
Let: R = RE = 12 k R
+ Then: AV = 3.0 AV = 1 +
2
R BW = 1.5 MHz RE

Figure 62. High Impedance Differential Amplifier

+VO

+
+ +
MC34074
100 k RL
10 10
+10

MC34074
220 pF +
100 k
10
+
+ RL
+ 10
MC34074
RL +VO VO 100 k 10
18.93 18.78
10 k 18 18
VO
5.0 k 15.4 15.4

Figure 63. Dual Voltage Doubler

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 MC34071,2,4,A MC33071,2,4,A

ORDERING INFORMATION
Op Amp Operating
Function Device Temperature Range Package Shipping
MC34071P PDIP8 50 Units / Rail
MC34071AP PDIP8 50 Units / Rail
MC34071D SOIC8 98 Units / Rail
Single TA = 0 to +70C
MC34071AD SOIC8 98 Units / Rail
MC34071DR2 SOIC8 2500 Units / Tape & Reel
MC34071ADR2 SOIC8 2500 Units / Tape & Reel
MC34072P PDIP8 50 Units / Rail
MC34072PG PDIP8 50 Units / Rail
(PbFree)
MC34072AP PDIP8 50 Units / Rail
MC34072D SOIC8 98 Units / Rail
MC34072DG SOIC8 98 Units / Rail
(PbFree)
TA = 0 to +70C
MC34072AD SOIC8 98 Units / Rail
MC34072DR2 SOIC8 2500 Units / Tape & Reel
MC34072DR2G SOIC8 2500 Units / Tape & Reel
(PbFree)
MC34072ADR2 SOIC8 2500 Units / Tape & Reel
MC34072ADR2G SOIC8 2500 Units / Tape & Reel
Dual (PbFree)
MC33072P PDIP8 1000 Units / Rail
MC33072PG PDIP8 1000 Units / Tube
(PbFree)
MC33072AP PDIP8 50 Units / Rail
MC33072D SOIC8 98 Units / Rail
TA = 40
40 to +85C
MC33072AD SOIC8 98 Units / Rail
MC33072DR2 SOIC8 2500 Units / Tape & Reel
MC33072DR2G SOIC8 2500 Units / Tape & Reel
(PbFree)
MC33072ADR2 SOIC8 2500 Units / Tape & Reel
MC34072VD SOIC8 98 Units / Rail
MC34072VDR2 TA = 40
0 to
o +125C
5C SOIC8 2500 Units / Tape & Reel
MC34072VP PDIP8 50 Units / Rail
MC34074P PDIP14 25 Units / Rail
MC34074AP PDIP14 25 Units / Rail
MC34074D SOIC14 55 Units / Rail
MC34074AD SOIC14 55 Units / Rail
TA = 0 to +70C
MC34074DR2 SOIC14 2500 Units / Tape & Reel
MC34074DR2G SOIC14 2500 Units / Tape & Reel
(PbFree)
MC34074ADR2 SOIC14 2500 Units / Tape & Reel
Quad
MC33074P PDIP14 25 Units / Rail
MC33074AP PDIP14 25 Units / Rail
MC33074D, MC33074AD SOIC14 55 Units / Rail
MC33074DR2 SOIC14 2500 Units / Tape & Reel
MC33074ADR2 TA = 40 to +85C SOIC14 2500 Units / Tape & Reel
MC33074DTB TSSOP14 96 Units / Rail
(PbFree)
MC33074ADTB TSSOP14 96 Units / Rail
(PbFree)

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 MC34071,2,4,A MC33071,2,4,A

Op Amp Operating
Function Device Temperature Range Package Shipping
MC33074DTBR2 TSSOP14 2500 Units / Tape & Reel
(PbFree)
TA = 40
40 to +85C
MC33074ADTBR2 TSSOP14 2500 Units / Tape & Reel
(PbFree)
Quad MC34074VD SOIC14 55 Units / Rail
MC34074VDG SOIC14 55 Units / Rail
TA = 40
40 to +125C
+125 C (PbFree)
MC34074VDR2 SOIC14 2500 Units / Tape & Reel
MC34074VP PDIP14 25 Units / Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

MARKING DIAGRAMS

PPDIP8
P SUFFIX
CASE 626
8 8 8 8 8
MC3x071P MC3x071AP MC3x072P MC3x072AP MC34072VP
AWL AWL AWL AWL AWL
YYWW YYWW YYWW YYWW YYWW

1 1 1 1 1

SOIC8
D SUFFIX
CASE 751
8 8 8 8 8

3x071 3x071 3x072 3x072 3x072

ALYW ALYWA ALYW ALYWA ALYWV

1 1 1 1 1

PPDIP14
P SUFFIX
CASE 646
14 14 14

MC3x074P MC3x074AP MC34074VP

AWLYYWW AWLYYWW AWLYYWW

1 1 1

SOIC14 TSSOP14
D SUFFIX DTB SUFFIX
CASE 751A CASE 948G
14 14 14 14 14

MC3x074D MC3x074AD MC34074VD MC33 MC33

AWLYWW AWLYWW AWLYWW 074 074A
ALYW ALYW
1 1 1
1 1

x = 3 or 4
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week

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 MC34071,2,4,A MC33071,2,4,A

PACKAGE DIMENSIONS

PDIP8
P SUFFIX
CASE 62605
ISSUE L

NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
8 5 2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
B Y14.5M, 1982.

1 4 MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240 0.260
F C 3.94 4.45 0.155 0.175
D 0.38 0.51 0.015 0.020
NOTE 2 A F 1.02 1.78 0.040 0.070
L G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
K 2.92 3.43 0.115 0.135
C L 7.62 BSC 0.300 BSC
M 10
10

J N 0.76 1.01 0.030 0.040
T
SEATING N
PLANE
M
D K
H G
0.13 (0.005) M T A M B M

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 MC34071,2,4,A MC33071,2,4,A

PACKAGE DIMENSIONS

SOIC8
D SUFFIX
CASE 75107
ISSUE AB

X NOTES:
1. DIMENSIONING AND TOLERANCING PER
A ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
8 5
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
B S 0.25 (0.010) M Y M 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 PROTRUSION SHALL BE 0.127 (0.005) TOTAL
4 IN EXCESS OF THE D DIMENSION AT
Y K MAXIMUM MATERIAL CONDITION.
6. 75101 THRU 75106 ARE OBSOLETE. NEW
STANDARD IS 75107.
G
MILLIMETERS INCHES
C N X 45
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
SEATING
PLANE B 3.80 4.00 0.150 0.157
Z C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
0.10 (0.004) G 1.27 BSC 0.050 BSC
H M J H 0.10 0.25 0.004 0.010
D J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0
8
0
8

0.25 (0.010) M Z Y S X S
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244

SOLDERING FOOTPRINT*

1.52
0.060

7.0 4.0
0.275 0.155

0.6 1.270
0.024 0.050

SCALE 6:1 inches

mm 

*For additional information on our PbFree strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 MC34071,2,4,A MC33071,2,4,A

PACKAGE DIMENSIONS

PDIP14
P SUFFIX
CASE 64606
ISSUE M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14 8 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 7 5. ROUNDED CORNERS OPTIONAL.

INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 18.80
F L B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
N F 0.040 0.070 1.02 1.78
C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
T J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
SEATING
PLANE L 0.290 0.310 7.37 7.87
K J M 10
10

H G D 14 PL M N 0.015 0.039 0.38 1.01

0.13 (0.005) M

SOIC14
D SUFFIX
CASE 751A03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
A Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14 8 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
B P 7 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 7
0.25 (0.010) M B M PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS INCHES
G R X 45
F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
T F 0.40 1.25 0.016 0.049
SEATING K M J G 1.27 BSC 0.050 BSC
D 14 PL
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0
7
0
7

P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

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 MC34071,2,4,A MC33071,2,4,A

PACKAGE DIMENSIONS

TSSOP14
DTB SUFFIX
CASE 948G01
ISSUE O

14X K REF NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
0.10 (0.004) M T U S V S
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
N OR GATE BURRS SHALL NOT EXCEED 0.15
0.25 (0.010) (0.006) PER SIDE.
14 8
2X L/2 4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
M PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE DAMBAR
PIN 1
U N PROTRUSION. ALLOWABLE DAMBAR
IDENT. PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
F EXCESS OF THE K DIMENSION AT MAXIMUM
7 MATERIAL CONDITION.
1 DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE W.
0.15 (0.006) T U S
A K

MILLIMETERS INCHES
V K1 DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
J J1 C 1.20 0.047
D 0.05 0.15 0.002 0.006
SECTION NN F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
W J1 0.09 0.16 0.004 0.006
C K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
0.10 (0.004) L 6.40 BSC 0.252 BSC
T SEATING M 0
8
0
8

PLANE D G H DETAIL E

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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For additional information, please contact your
local Sales Representative.

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22
This datasheet has been download from:

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