ENGINEERING REPORTS

A Transistor Ladder Voltage-Controlled Filter

Implemented on a Field Programmable
Analog Array

STEPHEN H. NEASE , AARON D. LANTERMAN , AND JENNIFER O. HASLER

(stephen.nease@gatech.edu) (lanterma@ece.gatech.edu) (jennifer.hasler@ece.gatech.edu)

School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332

Before fast, inexpensive digital electronics became commonplace, analog techniques domi-
nated the field of music synthesis. Over time, much of the art has moved to the digital domain,
which allows for greater flexibility than traditional analog systems. Many enthusiasts still ar-
gue that the warmth of analog systems is difficult to recreate digitally. Recent developments
concerning Field-Programmable Analog Arrays may permit the creation of analog synthe-
sizers that enjoy the ease of rapid reconfigurability previously associated only with digital
synthesizers, allowing musicians to characterize individual circuit elements and try different
topologies. This paper presents an implementation of a particularly famous voltage-controlled
filter design, namely, the transistor ladder filter. The original formulation, which was based on
BJTs, readily maps to MOSFETs operating in the subthreshold region. The implementation is
aided by the use of high-level software design tools in Simulink.

0 INTRODUCTION by Robert Moog [1], originally implemented as a ladder

Music production is one of the few areas of technology
where analog signal generation and processing techniques
continue to capture the imagination of the public. This is in
sharp contrast with consumer products such as cell phones
and televisions, where most users would not be surprised
at finding most processing being conducted using digital
techniques, to the extent that end users think about such
matters at all. Companies such as Korg, Moog, and Nova-
tion continue to produce analog music synthesizers. Electric
guitarists help keep vacuum tubes in production, and some
mixing console manufacturers continue to use discrete op
amps instead of their more cost effective integrated circuit
(IC) counterparts. The allure of vintage audio gear has
lead to computer software plug-ins that attempt to imi-
tate classic pieces of analog equipment with digital signal
processing, often deliberately including the nonlinearities
that the original designers generally strove to remove. Such
software emulations have improved over the years, but de-
mand for true analog sound remainsand the price of
this sound remains high, due to the large number of dis-
crete components typically involved.
Modern field programmable analog arrays (FPAAs) of-
fer the potential of implementing analog designs that pro-
vide musicians with greater flexibility at reduced cost. As
an illustration, this paper demonstrates how the lowpass
voltage-controlled filter (VCF) developed and popularized
consisting of discrete bipolar junction transistors (BJTs),
naturally maps to an FPAA with metal-oxide semiconduc-
tor field-effect transistors (MOSFETs) operating in the sub-
threshold region.
0.1 Music Synthesis with Analog Circuits
Almost all music synthesizers developed in the 1960s
and 1970s consisted primarily of analog circuitry [2]. Even
when microprocessors became commonplace in synthe-
sizers in the 1980s, the audio generation and processing
remained analog in instruments such as the seminal Se-
quential Circuits Prophet 5, with the processor reading
front panel controls and using Digital-to-Analog Convert-
ers (DACs) to generate control voltages for the analog cir-
cuitry. A typical subtractive synthesis chain consisted of a
voltage-controlled oscillator (VCO), a VCF, and a voltage-
controlled amplifier (VCA), with pitch, timbre, and volume
control voltages generated by slowly varying envelopes and
low-frequency oscillators. Some synthesizers that boasted
digital oscillators, such as the Palm Products GmbH Wave
2.3 and the Sequential Circuits Prophet VS, retained ana-
log filters and amplifiers. These instruments arose in an
era in which oscillators could be readily constructed with
digital counters driving look-up tables of single-cycle wave-
forms, whereas the digital multipliers needed to implement
real-time digital filters were cost prohibitive. Whether the

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NEASE ET AL.
Fig. 1. Two methods of analog music synthesis. Currently, many
discrete components must be obtained and soldered together on
a printed circuit board (PCB). This process is costly and time-
consuming. The Field Programmable Analog Array, however,
offers an analog platform that can be quickly and easily re-
programmed to connect many different analog circuit elements
for fast prototyping. The elements are controllable at a single-
transistor level or a large circuit level, enabling fine-grained con-
trol over the desired sound.
oscillator itself is primarily analog or digital, the distinc-
tive essence of many classic synthesizers lies in their VCF
implementations.
The affordability of polyphonic analog instruments in
the late 1970s and early 1980s depended on the availability
of custom music synthesis ICs. Although many of these
were fairly simple for instance, the SSM2040 consists of
just four operational transconductance amplifiers (OTAs),
four voltage buffers, and an exponential current-to-voltage
converter these ICs significantly simplified the design
and lowered the cost of such instruments. Unfortunately,
most of these dedicated music ICs have been long out of
production.
Although the idea of field-programmable analog arrays
has been around for some time, it is only in recent years
that they have become powerful enough to be considered
for facilitating complex analog music synthesis. As shown
in Fig. 1, a single modern FPAA chip could potentially
replace dozens of low-scale integration analog ICs from the
1980s, and their rapid reprogrammability could potentially
provide musicians with architectural flexibility along the
lines of the original modular synthesizers pioneered by
Robert Moog and Donald Buchla in the 1960s.
0.2 Field-Programmable Analog Arrays
Our implementations of FPAAs are mixed-signal Com-
plementary Metal-Oxide Semiconductor (CMOS) chips
that allow analog components to be connected together in
an arbitrary fashion, allowing for rapid testing and mea-
surement of many different circuit designs.
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ENGINEERING REPORTS
The FPAA explored in this paper is organized into three
functional blocks. The first is the Computational Ana-
log Block (CAB), which is a physical grouping of ana-
log circuits that act as computational elements. These el-
ements include n and p channel field-effect transistors
(nFETs and pFETs), operational transconductance ampli-
fiers (OTAs), capacitors, Gilbert multipliers, and more. A
simple schematic depiction of the connectivity of CABs is
shown on the right side of Fig. 2 a. These CAB compo-
nents can be connected together to form more complicated
subcircuits, which can be further interconnected to create
arbitrary analog systems. This paper illustrates the imple-
mentation of a VCF on such an FPAA.
The interconnection of CAB components is accom-
plished with the FPAAs second functional block, the switch
matrix (SM). A SM and its connection to a CAB is shown
in Fig. 2 a. A SM is a collection of floating-gate pFETs that
connect rows and columns of routing lines. A floating-gate
FET is a transistor whose gate has no DC path to ground.
The SMs are arranged such that they allow local routing
between elements inside a single CAB as well as global
routing between CABs. A depiction of the global routing
scheme is shown in the overall system block diagram in
Fig. 2 b.
The third functional block is the programmer (also de-
picted in Fig. 2 b), which selects a floating-gate device in
the switch matrix and controls the processes of tunneling
and injection to add or remove charge to the floating gate.
This allows each device to be turned completely on, turned
completely off, or operated somewhere in-between. This
flexibility means that switch elements can be used for com-
putation as well as routing. This is especially beneficial in
audio applications, since transistors set to a constant bias
are often necessary. A die photo of the fabricated chip is
shown in Fig. 2 c.
0.3 FPAA Test Platform and High-Level Tools
All measurements in this paper were taken on a PCB
designed to test various circuits compiled on the FPAA [3].
This system is depicted schematically in Fig. 2 b. The board
consists of DACs, analog to digital converters, and several
other peripherals, which are controlled by an Atmel micro-
controller. It also contains audio jacks for communicating
audio between standard analog audio sources. The Atmel
chip receives commands from a PCB running MATLAB
via a USB connection.
Over the years, our lab has developed tools that make
the design of circuits on FPAAs easier. Programming of
the FPAA is controlled through a suite of MATLAB soft-
ware that interfaces to the microcontroller. We developed
a Simulink frontend to the programming scripts called
Sim2Spice [4]. Users first create a Simulink block diagram
containing components of the FPAA connected together to
create the desired circuit. Sim2Spice then parses the dia-
gram and generates a netlist that the programming scripts
can target to the FPAA.
One advantage of Sim2Spice is that users can create their
own Simulink blocks that represent higher-level collections
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ENGINEERING REPORTS A TRANSISTOR LADDER VOLTAGE-CONTROLLED FILTER IMPLEMENTED ON A FIELD PROGRAMMABLE ANALOG ARRAY

(a) CAB and SM detail (b) Basic block diagram (c) Die Photo

Fig. 2. (a) Basic block diagram of experimental setup. The entire system is controlled by MATLAB running on a PC. This communicates
with a microcontroller which sends commands to the devices on the board. The FPAA consists of Computational Analog Blocks (CABs)
interconnected by local and global Switch Matrices (SMs). (b) Detail of a portion of a Computational Analog Block. (c) Die photo of
the RASP 2.9a.

of circuits. These blocks can also be paramaterized so that
users can change aspects of the circuit from the higher-level
interface.
1 TRANSISTOR LADDER VCF
IMPLEMENTATION
This study used one of our most recent FPAA designs,
RASP 2.9a. It is a larger version of RASP 2.8b [5], and
closely related to RASP 2.9v [6].
A conceptual schematic of our FPAA implementation
of the transistor ladder filter is shown in Fig. 3, and its
Simulink implementation is shown in Fig. 4. The original
circuit was implemented with bipolar circuit technology,
so it had to be retooled for CMOS technology. nFETs are
most naturally analogous to NPN BJTs, and pFETs are most
naturally analogous to PNP BJTs.
We chose to implement the ladder using CAB pFETs.
We decided to use CAB elements (rather than floating-gate
elements) because they allow for a rapid exploration of the
parameter space in a prototyping context. In future versions
of the ladder, the CAB pFETs can be replaced with floating-
gate pFETs. The benefit of floating-gate FETs is that their
biases are stored in a nonvolatile manner through floating-
gate programming, so no explicit gate potentials need to be
applied from external circuits. This enables a wide variety
of different biasing conditions across a single chip. The
downside in this context is that developing the calibration
procedure for a ladder based on floating-gate elements can
take longer to accomplish. Since we were testing topology
and not calibration, CAB pFETs were deemed sufficient
for our purposes. We chose CAB pFETs (rather than CAB
nFETs) because only pFETs are present in floating-gate
form on our target FPAA, and we would like to use floating-
gate devices in this circuit eventually. The floating-gate
implementation and calibration procedure are left as future
work.
The original transistor ladder filter exploited the dynamic
resistance of BJTs; we similarly exploit the dynamic resis-
tance of MOSFETs, with the Vcutoff controlling the bias cur-
rent produced by the topmost transistor in Fig. 3. This bias
current varies the dynamic resistance of the MOSFETs and
hence the effective cutoff frequency of the filter stages, just
as in the original BJT-based filter. Most implementations
of the transistor ladder filter, both commercial and hobby-
ist, have used NPN transistors; implementations using PNP
transistors exist, but are relatively rare. Hence, our ladder
schematic may look upside down relative to the transis-
tor ladder schematics most enthusiasts are accustomed to
seeing.
We used a simple two-OTA attenuator at the input to
reduce the audio signal to a level such that the filter acts
approximately linearly.1 Our experiments used a similar
two-OTA amplifier at the output to compensate for this
initial attenuation.
The transfer function for this topology has been derived
in detail elsewhere [7]. In that analysis, BJTs were used
rather than MOSFETs. Fortunately, MOSFETs acting in the
subthreshold2 regime have exponential current-to-voltage
(I-V) characteristics, similar to BJTs. For a pFET in satura-
tion with terminals referenced to the bulk and drain effects
ignored, this characteristic simplifies to
I = I0 e(Vs Vg )/UT , (1)
1
Pushing the input level to a point that the filter slightly distorts
the signal is not necessarily bad, as subtle nonlinear effects are
commonly thought to contribute to the fatness of the transistor
ladder filter sound.
2
MOSFETs are most commonly thought of as having square-
law, instead of exponential, I-V characteristics. Unfortunately,
some undergraduate electronics textbooks mischaracterize the
subthreshold regime, which is so useful in many low-power IC
designs, as simply being off.

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NEASE ET AL.
Fig. 3. Conceptual schematic of an implementation of ladder filter tailored for pFETs operating in the subthreshold regime. An input is
fed into the left side of the filter, and it passes through four filter stages. A differential output is taken between the left and right side of
the ladder with a negative feedback gain of K. In our implementation, feedback was achieved using a two-OTA voltage amplifier. We
also attenuated the signal before applying to the input to avoid distortion, and then amplified the output.
where I0 is a grouping of physical constants, Vs is the source
voltage, Vg is the gate voltage, is a physical constant
representing the gate to channel coupling, and UT is the
thermal voltage. Typical values for are around 0.7.
The transfer function is developed as in [7] by small-
signal analysis of these devices. The input pair converts an
input voltage into current through its transconductance
I
gm = = I, (2)
Vg UT
where I is the bias current. The ladders gates are at fixed
potentials, but their source voltages are changing as the
input changes, so the source conductance is modeled as:
I 1
gs = = I. (3)
Vs UT
Developing as in [7], the closed-loop transfer function is
H (s) =  4 . (4)
2sC
+ 1 + k
gs
Changing the bias current will modulate gs and therefore
change the cutoff frequency.
The k factor determines the amount of negative feedback
from the output of the four stages back to the input. Each
stage approximately buffers the next, so when k = 0, the
response is that of a cascade of four identical single-pole
sections. Each section provides a 45 degree phase shift at
its half-power cutoff frequency, for a total phase shift of
180 degrees. Moogs insight [1] was that negative feedback
could result in a musically useful enhancement around the
cutoff frequency, with the DC gain decreasing with increas-
ing k. A root locus analysis [8] shows that for k = 0, the
four poles lie at the same place on the real axis; as k is
increased, the poles run along diagonal paths, with the two
rightmost poles hitting the imaginary axis and theoretically
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ENGINEERING REPORTS
inducing self-oscillation at k = 4. The ability of the filter
to self-oscillate in a reasonably stable fashion can be cre-
atively useful; various nonlinear and nonideal effects may
cause practice to diverge from theory in interesting ways.
In this implementation, the amount of feedback is con-
trolled by a second two-OTA amplifier hooked to the bot-
tom of the ladder in Fig. 4. The first OTA converts the
differential output voltage into an output current through
its transconductance gm1 , and the second OTA converts
that current into a single-ended voltage via its transcon-
ductance gm2 . The transconductance of an OTA operated in
subthreshold is defined as [9]:
Ibias
gm = . (5)
2UT
Writing Kirchhoffs Current Law at the node that they
share, the DC transfer function is
Ibias1  
Vout = Vcm + Vleft Vright . (6)
Ibias2
The effect of increasing the amount of negative feedback
in this FPAA implementation is illustrated in Fig. 5. Note
the peaking resonance behavior, as well as the changing DC
gain.
Fig. 6 shows example time-domain system outputs for
three cases of square wave inputs: k = 1, 10 kHz input (top
graph), k = 4, 10 kHz input (middle graph), and k = 4,
100 Hz (bottom graph). Each waveform on a graph corre-
sponds to a different value of Vcutoff . The DC components
of the waveforms are shifted to provide a convenient way
to show the outputs for several different cutoff frequencies
on the same graph. Varying resonance effects can be seen
in the Gibbs-like oscillations at input transitions.
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Fig. 4. Simulink model used to take the data presented in this

paper. CAB pFETs and OTAs are used for this implementation.
For the k amplifier, the differential V-I OTAs bias current was
swept between 250 nA and 4 A. The I-V OTAs bias current was
left at 1A. The A and 1/A OTAs had biases of 200 nA and
1 A, depending on whether the gain was more or less than one.
The output buffers are biased at 5 or 10 A. Ladder capacitance
values are approximately 2 pF. The FG elements are effectively
short-circuits, used to circumvent the fact that Simulink does not
allow two block outputs to be connected together. Physically, they
are compiled to fully-on floating-gate routing elements.

5
k=4
k=2
0
k=1 Fig. 6. Examples of time-domain outputs. The trace colors in each
k=0.5 graph correspond to different values of Vcutoff , the voltage which
k=0.25
sets the circuits cutoff frequency. Vcutoff was swept between 1.8
5 and 2.2V. The y axis gives the output voltage. The amplitude of all
waveforms is correct, but the voltage offsets have been modified
Gain (dB)

for display purposes. The different graphs correspond to different

10
feedback amounts k and different input frequencies as indicated
in the graph titles.
15

2.9a could support 12 pFET-based ladder VCFs, assuming

20
perfect utilization of all the available CAB pFETs in the
chip; experience suggests that between 8 and 10 may be
25
10
1
10
2
10
3 4
10
5
10 more realistic due to imperfect utilization. However, the
Frequency (Hz) chip also contains numerous nFETs, so one could invert the
topology (making it look more like a traditional NPN-based
Fig. 5. Measured magnitude frequency response for different
amounts of negative feedback k. ladder filter), yielding another 810 filters.
The RASP 2.9a CABs also contain MITEs (Multiple-
Input Translinear Element Networks), which are multiple-
input floating-gate pFETs; these could be potentially used
1.1 How Many VCFs Would Fit? to facilitate additional VCFs. Even more VCFs might be
The question of how many such VCFs could fit on any implemented if the floating-gate routing switches could be
given FPAA platform is complicated. Of course, it would pressed into double duty as legs of the ladder, although
depend on what other kinds of components one might want that would likely be the most challenging approach.
to put on any given FPAA, but it would also depend on how In any case, even relatively straightforward implementa-
much effort could be put into making clever use of FPAA tions could readily support the VCF needs of a polyphonic
resources and developing efficient routing schemes. RASP synthesizer with a single FPAA chip.

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1.2 Differential amplifier implementation issues
The gain of the two two-OTA3 amplifiers used in the feed-
back path and the final output of the filter is controlled by
floating-gate transistors, whose value must be programmed;
this is inconvenient if smooth real-time changes are desired.
The built in OTAs on RASP 2.9a have their gain con-
trols hardwired to these floating gates. It would be more
convent to directly control both the feedback amount and
the differential amplifier driving the output; the latter then
plays the subtractive synthesis role of a VCA. One could
construct OTAs using the stand-alone generic pFETs and
nFETs that are available in each CAB (three of one type of
FET and two of another type could be made equivalent to
one of the dedicated OTAs). Alternatively, one could use
the Gilbert multipliers that are available in each CAB; these
may seem like overkill, since they are four-quadrant multi-
pliers and only two-quadrant multiplication is needed, but
they may be an attractive option if they are not being used
for other purposes. These issues are left as directions for
future work.
2 CONCLUSIONS AND FUTURE WORK
New FPAAs based on floating-gate transistors offer a
flexible platform for the exploration of analog music syn-
thesis. These approaches could empower an analog music
synthesis renaissance due to the advent of large-scale, re-
configurable analog chips. As demonstrated in numerous
applications [10]-[12], FPAAs have the benefit that they
can deliver the functionality of custom integrated analog
CMOS systems, but they also have the flexibility of FP-
GAs. An FPAA is a reconfigurable very large-scale inte-
grated (VLSI) system, so its impact and design are the same
as a custom IC, but it allows a range of potential circuits to
be compiled on a single device. Since our VCF is imple-
mented on an analog VLSI substrate, its design required the
same considerations as those in custom IC design. For ex-
ample, the bias currents of the two-OTA amplifiers needed
to be high enough such that the k gain factor does not
significantly degrade over frequency. Additionally, we re-
duced the inputs amplitude and shifted its bias point so
that it was within the linear regime of the ladder and kept
the ladder FETs in saturation. The classic tradeoff between
power and performance, the consideration of linearity, and
the accounting for transistor operating regimes are all ubiq-
uitous themes in both custom IC designs and FPAA system
designs, and therefore circuit design intuition is essential
when using either platform.
This paper focused on VCFs because they are one of the
most characteristic aspects of analog music synthesis, and it
focused on the transistor ladder filter because it is one of the
3 highly flexible and usable analog synthesis systems. More
The construction two two-OTA amplifiers looks like an error
but is correct. Each amplifier uses two OTAs; the first turns voltage
into a current, and the second essentially acts like a resistor turning
current back into a voltage. The total gain of the two-OTA structure
is determined by the ratio of the gains of the individual OTAs;
having both gains available allows designers to make complex
performance tradeoffs.
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ENGINEERING REPORTS
most well-known VCF structures. Other VCF topologies
could be readily explored as well. For instance, another
common structure with a cascade of four single-pole filters
with a negative feedback loop uses OTA-C filters for the
stages.
While this paper focuses on the VCF subsystem of a
synthesizer, FPAAs are capable of creating entire synthesis
systems. The other two subsystems needed for a simple
synthesizer are the voltage-controlled oscillator (VCO) and
voltage-controlled amplifier (VCA), and both have already
been demonstrated on FPAAs. A VCO was implemented
as part of a sigma-delta modulator [13], and a VCA based
on a Gilbert Multiplier was demonstrated on one of the
first FPAAs [5]. Such subsystems will likely need to be
modified to conform to audio synthesis specifications. For
instance, VCO implementations that would be controllable
over a wide pitch range and remain stable with temperature
changes might pose a significant challenge.
These subsystems could easily be connected together
by creating a Simulink block for each subsystem and then
connecting them all together in a single block diagram.
A set of interface specifications for Simulink blocks in
an analog macromodeling context has already been pro-
posed [14]. The specification makes three recommenda-
tions for Simulink blocks. First, blocks should have voltage
inputs and outputs (current-mode computation should be
done within each block). Second, blocks should make use
of vectorized notation, so a single block can represent a
large number of parallel blocks with different properties.
Finally, analog biasing should be done within each block.
If all three of these recommendations are followed, cre-
ating various synthesis systems with different configura-
tions of VCOs, VCAs, and VCFs will be relatively easy to
accomplish.
Any practically useful implementation of such
systems including the VCF implementation detailed in
this paper would require the development of automatic
calibration procedures. For example, producers should be
able to specify the VCOs cutoff frequency fc rather than the
voltage Vc which sets that frequency. The calibration proce-
dure consists of three steps. First, an analog parameter (Vc )
is swept over its valid range, and the systems behavior (fc )
is measured. Next, a lookup table from parameter to behav-
ior is stored. Finally, the Simulink block sets the parameter
based on the desired behavior. This could be automated by
writing scripts that automatically sweep parameters, mea-
sure behavior, and store characteristics. Simulink blocks are
capable of using the lookup tables to change their parame-
ters, so music producers do not need to be familiar with the
internals of the block they simply need to specify what
behavior they want. Combining this automatic calibration
procedure with the Simulink block specification could yield
technically inclined users could explore and modify the in-
ternal structures of the blocks as desired, to whatever level
of detail interests them.
Implementations need not necessarily employ Simulink,
which is an expensive program; customized software with
a look-and-feel along the lines of DSP-oriented modular
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ENGINEERING REPORTS A TRANSISTOR LADDER VOLTAGE-CONTROLLED FILTER IMPLEMENTED ON A FIELD PROGRAMMABLE ANALOG ARRAY
synthesis programs such as Max/MSP, Pure Data, National
Instruments Reaktor, or the Nord Modular patch editor
might be more appropriate.
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THE AUTHORS
Stephen H. Nease Aaron D. Lanterman
Stephen Nease received the B.S. degree in electrical en-
gineering from Rose-Hulman Institute of Technology,
Terre Haute, IN, in 2009. He received the M.S. and Ph.D.
degrees from the Georgia Institute of Technology, Atlanta,
GA in 2011 and 2014, respectively. He is currently a post-
doctoral scholar at CITEC in the University of Bielefeld.
His interests include neuromorphic circuits and systems,
analog circuit design, and reconfigurable mixed-signal
CMOS systems.
r ogy. Dr. Hasler received her M.S. and B.S.E. in Electrical
Dr. Lanterman grew up in St. Louis, MO and attended
Washington University, where he finished a triple major
consisting of a B.A. in music, B.S. in computer science,
and a B.S. in electrical engineering in 1993. He stayed
on for graduate school, receiving an M.S. (1995) and D.Sc.
(1998) in electrical engineering. His graduate work focused
on target recognition for infrared imagery as part of the
U.S. Army Center for Imaging Science. After graduation,
he joined the Coordinated Science Laboratory at the Univ.
of Illinois at Urbana-Champaign, where he managed a large
project on covert radar systems which exploit illuminators
of opportunity such as commercial television and FM ra-
dio signals. He joined the Georgia Tech faculty in the fall of
2001. He received the School of Electrical and Computer
618
ENGINEERING REPORTS
Jennifer O. Hasler
Engineering Richard M. Bass/Eta Kappa Nu Outstanding
Junior Teacher Award in 2006, and was named a 2009 Hes-
burgh Award Teaching Fellow. He has served as associate
editor for radar for the IEEE Transactions on Aerospace
and Electronic Systems.
r
Jennifer Hasler is a Professor in the School of Electrical
and Computer Engineering at Georgia Institute of Technol-
Engineering from Arizona State University in 1991, and
received her Ph.D. from California Institute of Technology
in Computation and Neural Systems in 1997. Her current
research interests include low-power electronics, mixed-
signal system ICs, floating-gate MOS transistors, adaptive
information processing systems, smart interfaces for sen-
sors, cooperative analog-digital signal processing, device
physics related to submicron devices or floating-gate de-
vices, and analog VLSI models of on-chip learning and
sensory processing in neurobiology. Dr. Hasler received the
NSF CAREER Award in 2001, and the ONR YIP award
in 2002. Dr. Hasler received the Paul Raphorst Best Paper
Award from IEEE Electron Devices Society in 1997, the
CICC Best Student Paper Award in 2006, the ISCAS Best
Sensors Paper award in 2005, a best paper award at SCI
2001.
J. Audio Eng. Soc., Vol. 62, No. 9, 2014 September