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Abstract: It is very important to detect transition-delay faults and stuck-at faults in system on chip (SoC) under
90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing
method. In this paper, an on-chip clock (OCC) controller with a bypass function based on an internal phase-locked
loop is designed to test faults in SoC. Furthermore, a clock chain logic which can eliminate the metastable state is
realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by automatic
test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by using the Synopsys tool and the
correctness of the design is verified. The result shows that the design of an at-speed scan test in this paper is highly
efficient for detecting timing-related defects. Finally, the 89.29% transition-delay fault coverage and the 94.50%
stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design.
Key words: at-speed scan test; on-chip clock; transition-delay faults; phase-locked loop
DOI: 10.1088/1674-4926/34/12/125012 EEACC: 2520
1. Introduction test (DUT). One issue with using an internal PLL clock is that
current ATPG tools assume that clock signals are controlled by
With the recent development of semiconductor processes, primary input pins. Therefore, during test pattern generation it
companies that design and manufacture leading-edge products is necessary to modify the circuit model such that clock sig-
are quickly moving toward very deep submicron (VDSM) inte- nals are driven by primary input pins, while during test pattern
grated circuit (IC) technology1 . Under 90 nm processing has application on ATE launch-capture clocks are derived from a
become the mainstream technology used for system on chip PLL9 .
(SoC). As nanometer technology has led to a drastic increase To detect the path-delay defects in the chip design, at-speed
in operational frequency, circuit performance has become more scan test methodology and the transition-delay fault model are
vulnerable to delay variation, and SoC testing has become more used in this paper. Compared with the traditional method of
challenging2 . Conventional IC test methodology cannot ade- static fault diagnosis based on the stuck-at faults model, using
quately and cost-effectively test the high clock speed and mil- the transition-delay fault model can detect the slow-to-rise and
lions of gates inherent in VDSM technology. At-speed test- the slow-to-fall defects in the path by testing the stuck-at-0 and
ing of ICs is becoming critical for detecting subtle delay de- the stuck at-1 faults10 . Slow-to-rise defects mean that the chip
fects3 5 . internal node state does not correct results from 0 to 1 when the
At-speed scan testing for SoC can test the transition faults chip runs in high frequency. Similarly, the slow-to-fall defects
and support automatic test pattern generation (ATPG) with mean that the chip internal node state does not correct results
Synopsys TetraMAX tool. A key benefit of scan-based at-
speed testing is that only the launch clock and the capture clock
need to operate at the full frequency of the device under test. In
addition, shift data operates at slow speed by using slow shift
clocks to reduce the cost of the test equipment. The automatic
test equipment (ATE) which can supply speed clock is often ex-
pensive and ordinary ATE cannot provide the high frequency
clock. The design of at-speed scan testing in this paper uses the
internal high speed clock generated by the chip6; 7 .
In order to use our approach to test the faults in SoC, addi-
tional on-chip controller circuitry must be designed to control
the on-chip clocks (OCC) in test mode. The basic idea of the
clock control is to use an on-chip clock source, such as a phase
locked loop (PLL) or a delay locked loop (DLL), to provide
at-speed test pulses, while the ATE provides shift pulses and
test control signals at slow speed8 . However, ATE may not
provide an at-speed clock to the input pins of the device under Fig. 1. At-speed transition test timing.
* Project supported by the Key Project Science and Technology Cooperation of Fujian Province, China (No. 2013I0003).
Corresponding author. Email: mqks@fzu.edu.cn, lsqswl@qq.com
Received 26 January 2013, revised manuscript received 8 July 2013 2013 Chinese Institute of Electronics
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J. Semicond. 2013, 34(12) Lin Wei et al.
from 1 to 0 when the chip runs in high frequency. The ATPG nal clock (clk) which is created by the OCC controller circuit is
tool generates a launch pulse using the fast clock, and then, it used for driving the scan cells of the SoC design. The test mode
generates another clock pulse using the same clock to capture signal (test_mode) must be active in order to make sure the cir-
the effect of the launch pulse, and can detect the slow-to-rise cuit is working at testing state. The PLL reset signal (pll_reset)
and the slow-to-fall faults. Finally, whether the states of the is used once during test setup and initialization. The scan en-
nodes in the chip are correct or not is tested11 . The time delay able signal (scan_en) which must be active during every cap-
between launch and the capture cycle is illustrated in Fig. 1. ture procedure enables switching between the slow shift clock
and the fast clock signals. The scan_en signal is used to select
2. An on-chip clock controller design between the scan shift operation and the scan capture opera-
tion, and also drives the flip-flop scan. The PLL bypass signal
2.1. OCC controller for at-speed scan testing (pll_bypass) allows connection of the ATE clock signal directly
to the internal clock signals, thus bypassing the PLL clocks.
When doing test pattern generation for the delay de-
fects, the types of fault models, such as the transition fault The OCC controller circuit serves as an interface between
model, have been used extensively in industry12 . To test the the internal scan chains and the clocks which include both the
transition-delay faults used the fast clock, a PLL logic which fast clock and the slow clock. The OCC controller logic typi-
can output the clock multiplier in the SoC must be used. Then cally contains clock multiplexing logic that allows an internal
the OCC controller is used to control the clock to shift and cap- clock to switch from the slow clock during shift to the fast clock
ture the node states. Figure 2 shows the design architecture of created by the phase-locked loop circuit during capture. Figure
at-speed scan testing. 3 shows the structure of the OCC controller.
The signal function description as follows: the reference The logics of the clock chain, as illustrated in Fig. 4, is
clock (ref_clk) is used as a test default frequency input to the composed of two special scan flip-flops (DFF0 and DFF1)
PLL circuit and it must be always in a free-running state. The which are clocked by the falling edge of the internal clock.
PLL clock (pll_clk) or fast clock (fast_clk) is output from the When the scan_en signal is inactive, DFF0 and DFF1 work at
PLL circuit. It is a multiplied reference clock and also works a shift in state. When the scan_en is low, the DFF0 and DFF1
at a free-running state. It is used for generating the launch keep up the previous state. The clock enable signals generated
and capture pulse when the scan enable signal is low. The by the clock chain logic are used as a strobe signal for the OCC
slow clock (slow_clk) comes from the automatic test equip- controller. The clock output the OCC controller does not pro-
ment (ATE). So it is also called ATE clock (ate_clk). The slow duce burrs or another metastable state because the key of the
clock, typically slower than a fast clock, is used to shift the scan clock control logic is made up of a series of special shift regis-
chain. The ATE clock also drives the reference clock. The inter- ters13 .
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