Low-Cost FPGA Based Antenna Pattern

Measurement System
Mehmet Mert Taygur , Semih Bas , Erkut Yumrukaya , Emre Alp Miran and Serkan Gunel
Department
of Electrical & Electronics Engineering
Dokuz Eylul University, Izmir, TURKEY 35160

AbstractThe paper entitled Low-Cost FPGA Based

Antenna Pattern Measurement System describes a cost-
effective antenna pattern measurement system for edu-
cational purposes. Operating the system does not require
any additional computer support as it is designed to be
a standalone device. The system is built upon Field Pro-
grammable Gate Array (FPGA) platform and contains 4
main blocks; namely, RF source, logarithmic RF detector,
position controller and the central control unit.

I. INTRODUCTION
Antenna pattern measurement is an indispensable
process in antenna engineering, although its not a
trivial task when requirements to meet are strict and
challenging. However, simple far-field pattern mea-
surements for educational purposes could be realized
relatively easy and may not necessarily require expen-
sive, sophisticated equipments.
According to [1], a typical measurement system
contains 5 subsystems
1) source antenna and transmitting system
2) receiving system
3) positioning system
4) recording system
5) data-processing system
Advancements in the computer science and the
semiconductor technology enabled the recording and
data-processing systems to be combined in a single
computer which serve as a central control unit. In-
terfacing a computer to transmitting, receiving and
positioning systems is possible by using dedicated
equipment which include standard digital connections
(e.g GPIB, LAN). Alternatively, a network analyzer
may fulfill the requirement of transmitter, receiver,
computer all alone and can be used for measurement
instantly by only connecting to a positioning system
[2][3]. However, none of these combinations is cost-
effective for simple pattern measurement tasks in ed-
ucation. They are either expensive or delicate to be
used by candidate engineers. A possible solution is
replacing these equipments with discrete transmitter,
receiver, actuator components, which are significantly
cheaper, and interfacing them to the computer by
means of a microcontroller [4] since the accuracy is not
the foremost concern for an educational measurement
system. However, computer dependency may still exist
if microcontroller does not provide a user interface
within the firmware.
The system we describe in this paper is standalone
and based on a soft processor core implementation
on FPGA, hence it is portable and it doesnt require
Fig. 1: System block diagram
any additional computer support. Taking advantage
of reconfigurable architecture of FPGA, it is possible
to adapt the control unit for any kind of interface
or to scale the system later according to changing
needs. Embedded hardware created in the FPGA is
connected to a logarithmic RF detector board, an RF
source and a DC motor-rotary encoder.
II. SYSTEM DESCRIPTION
The system is designed to be operated between
1000-2000 MHz which covers GPS and GSM bands.
Specifications of the system are given as the following;
1) 2D pattern information in less than a minute by
positioning the test antenna in -axis with 1o
resolution.
2) Collecting and digitizing received power data
from -60dBm to 0dBm.
3) Command interface through a USB keyboard and
an HDMI compatible display.
4) Storing measurement data in SD card.
5) 1000-2000 MHz transmitting, 0-6000 MHz re-
ceiving range.
Block diagram of the system is given in Fig. 1.
III. HARDWARE
A. Control Unit
Control Unit is implemented on Digilents
AtlysTM Board which consists of a Spartan-6 LX45
FPGA chip. We designed the control unit as a
microcontroller hardware instead of application
specific circuit. Thus, we have taken advantage of
using standard interfaces and ready-to-use peripherals
provided by the manufacturers. The peripherals which
 Fig. 2: Feedback system for positioning
Fig. 3: CN0150 performance curve at 1.9 GHz,
Courtesy Analog Devices Inc.
create the hardware are chosen according to the
interfaces of other units and specifications of Atlys.
-60dBm up to 0dBm input power. This voltage is
Descriptions of the interfaces are given in the following
converted to 12-bit digital data in ADC and read
hardware sections. We used Xilinx MicroBlazeTM 32-
through the SPI peripheral of the control unit. Typical
bit soft processor core in implementation of embedded
output characteristic curve for 1.9 GHz is given in Fig.
hardware. Xilinx ISE Design Suite has been used as
3.
the design platform.
Interfacing actuator, receiver and transmitter inter- D. Transmitter
faces required extensive usage of I/O ports. Therefore,
For the transmitter side, we designed our own gen-
an expansion board, Digilents VmodMIB - VHDC
erator at 1-2 GHz. Our RF source is a 3 element ring
Module Interface, is added. Additionally, Pmod - SD
resonator array as each of them are tuned by a varactor.
card slot is included to the system in order to store the
Each resonator covers 330 MHz frequency range with
measurement data in a FAT32 formatted SD card.
15V tuning voltage, given in Fig. 4. Voltage input
B. Actuator of the entire generator system is connected to a 8-
The actuator unit consists of a 12V DC motor, a bit DAC which is interfaced with a general purpose
rotary encoder attached to the shaft and a driving- I/O port at the control unit side. 2-bit of the DAC
interfacing circuit which manages signal integrity in interface is used to multiplex the 3 ring resonators
order to protect FPGA chip. The rotary encoder creates to the reference antenna. Thus, effective frequency
two quadrature square wave signals in 1o rotation. resolution is calculated as 5 MHz. Due to the low
There are 2 interfaces which governs the actuator power output of the resonators, signal is amplified by
system; PWM signal and rotary encoder inputs. The 20dB before connecting to the antenna.
control unit is able to send PWM signal in 50 kHz E. User Interface
1
with 50 duty cycle increments. Consequently, encoder
signals are received and acknowledged by the inter- The system provides an interface through external
rupt controller of the processor. Precise positioning is elements; a USB keyboard and an HDMI compatible
obtained by using discrete PID algorithm, shown in 1. display. USB and HDMI ports are provided by Atlys
as on-board connectors. USB signals are converted
Kd de(n) X
to PS/2 protocol before coming into FPGA chip, so
e(n) = Kp e(n) + + 0.01Ki e(n) (1)
0.01 dn n
we used a simple PS/2 peripheral in the embedded
hardware and handled the protocol with an interrupt
Extraction of PID coefficients is made by apply-
based firmware. HDMI display is driven through two
ing Nichols-Ziegler method. Error signal is sampled
consecutive peripherals; a VGA driver which creates
with 10 ms intervals. Coefficients are then optimized
18-bit RGB signal and an HDMI buffer. Since the
to make the system response overshoot free, which
image on the display is created in the VGA peripheral,
guarantees stability even with heavy loads connected
it is not possible to obtain the native resolution that
to the shaft.
A block diagram of the actuator system is given in
Fig. 2.
C. Receiver
Receiver system is a complete RF detector board,
CN0150 from Analog Devices. There are 2 main
components on the board, AD8318 0-6000 MHz RF
detector and AD7887 analog-to-digital converter which
has serial connection interface through SPI protocol.
AD8318 has a linear output voltage characteristic for Fig. 4: Voltage-Frequency characteristic of the oscillator
 Fig. 5: Complete hardware map
HDMI standard may provide. Interface lacks CEC,
DDC options and provides only TMDS signaling at
25 MHz which corresponds to 640x480 frame size.
A block diagram which represents the complete
hardware is given in Fig. 5.
IV. SOFTWARE
Software of the system is written in C language
with Xilinx Software Development Kit (SDK) which
is a modified version of Eclipse IDE. Due to the
demanding requirements of the user interface in terms
of software complexity, we used Xilinx XilkernelTM ,
a small sized kernel for scheduling multiple threads
and handling interrupts. Interface is designed like a
console application as the user types a command from
the keyboard and executes it. Meanwhile, all operations
are shown on the display.
There are 3 threads and 2 interrupts defined in the
system. Priorities hold significance for synchronization
since the kernel might fall in an undefined state if
multiple tasks claim the same resource (e.g. mem-
ory region) simultaneously. Designated priorities from
higher to lower are listed below.
1) Motor control interrupt - Motor control thread:
PID algorithm
2) Keyboard interrupt: Handles PS/2 protocol
3) Pattern measurement thread
4) Main command interface thread
As the given interrupts and threads create the back-
bone for the software, they heavily rely on tool
functions which perform generic tasks like reading-
writing strings or handling communication protocols.
Tool functions are listed as the following.
Draw line-circle rasterization algortihms
String comparison
String output to display
String - variable conversions
ADC read, power calculation
PS/2 scan code - ASCII conversion
Send frequency data through DAC
SD card functions: initialize, read, write, create
file, send command
V. OPERATION & RESULTS
We built a simple measurement setup, shown in Fig.
6, to test the performance of the system.
Our test antenna was a simple half-wavelength
dipole operating at 1 GHz, whose specifications are
well known. The reference antenna was a log periodic
dipole array which covers 700-3000 MHz range.
We replaced our transmitter unit with signal gener-
ator equipments HP 8350B and HP83592A, since the
nonlinear voltage-frequency characteristic of the oscil-
lator prevented precise tuning in noisy environment.
Although we were unable to test the transmitter unit
within the whole system, measurement would still be
performed except that the operating frequency should
have been adjusted manually.
A pattern measurement operation is completed in
30 seconds approximately as the test antenna makes
a 360o rotation while 360 samples are collected. Data
sampling and processing are fast enough to be repeated
1500 times in 1 complete tour. As soon as the data are
collected, pattern is displayed with directivity, -3dB
beamwidth information. Pattern data is displayed in
relative form where the maximum point is labeled as
0dBi. Directivity is calculated according to 2.
(0 Pmin ).360
P360 (2)
i=1 P [i]
User is able to analyze the pattern in 2 different way.
First, relative power for each angle point is observed.
Secondly, the regions where the antenna is able to
produce a relative power more than the specified value,
can be investigated. Pattern data can be exported into
Fig. 6: Measurement setup block diagram

Fig. 7: Measurement results
Fig. 8: Measured pattern
a FAT32 formatted SD card in .csv format if desired.
The libraries for the FAT structure is taken from Xilinx
sources but they are modified to be compatible with the
SPI protocol for communicating the SD card.
The numerical results that we obtained from mea-
surement are shown in Fig. 7.
An obvious error seen in Fig. 7 is the inconsistent
directivity value. Since the measurement is not taken
in an anechoic chamber, it can be predicted that reflec-
tions might have caused the problem. Also, considering
the Maximum Power and Power Range values reveals
that the noise floor is nearly at -40dBm which is higher
than the native lowest power limit of the detector,
proving the excessive reflection.
Antenna pattern, on the other hand, shows the ex-
pected characteristic, as seen in Fig. 8. Although two
major beam have 2dB difference approximately at their
maximum points, scale of the entire pattern allows it
to be ignored.
A picture of the system is given in Fig. 9.
VI. CONCLUSION
We have built a standalone, scalable antenna pattern
measurement system based on an FPGA platform and
receiver, transceiver, positioning subsystems. Total cost
of the entire system is less than 1000$, including
the components that we already had in our inven-
tory. Compared to similar educational systems, we
managed to keep total cost significantly lower since
we eliminated the need of sophisticated equipment
View publication stats
Fig. 9: HDMI display, FPGA board, keyboard,
receiver-actuator and power supply
such as Vector Network Analyzer (VNA) or Spectrum
Analyzer, which are the core elements in conventional
antenna measurement setup. Correspondingly, func-
tional specifications meet only basic requirements to
measure 2D pattern of elementary antennas like Yagi-
Uda, half-wavelength dipole. Sample measurements
revealed that 15dB dynamic range can be achieved
easily even without making the measurement in an
anechoic chamber. Theoretically, the system can offer
50dB dynamic range which is quite enough for educa-
tional purposes. Interface allows the user to perform
simple data tracing on the pattern and exports the
measurement data to SD card if desired. Components
of the system can be easily replaced or upgraded by
taking advantage of FPGA features. Thus, the system
provides a platform whose functionality can be im-
proved immensely, unlike conventional measurement
systems. Limited bandwidth at the transmitter side (1-
2 GHz) can be expanded by adding new data paths
to the DAC interface and including new generators.
Recent hardware implementation has consumed %30
of the Spartan-6 LX45 chip, which means there is
plenty room to improve in terms of hardware.
To summarize, our antenna pattern measurement
system introduces a cost-effective solution for educa-
tional purposes.
R EFERENCES
[1] A. S. Committee, IEEE Standard Test Procedures for Anten-
nas, ANSI/IEEE Std 149-1979, 1979.
[2] S. R. Nichols, R. Dygert, and D. Wayne, Advances in an-
tenna measurement instrumentation and systems, in 2012 6th
European Conference on Antennas and Propagation (EUCAP).
IEEE, Mar. 2012, pp. 31903194.
[3] H. Bartik, T. Korinek, Z. Hradecky, and M. Mazanek, New an-
tenna measurement system, in 15th Conference on Microwave
Techniques COMITE 2010. IEEE, 2010, pp. 4950.
[4] B. C. Brown, F. G. Goora, and C. D. Rouse, The Design of an
Economical Antenna-Gain and Radiation-Pattern Measurement
System, IEEE Antennas and Propagation Magazine, vol. 53,
no. 4, pp. 188200, Aug. 2011.