LABORATORY MANUAL ON

EXPERIMENTS USING MODELSIM &

XILINX


Study of MODELSIM
Aim: To Study the ModelSim tool.

ModelSim is a simulation and debugging tool for Verilog, VHDL, and mixed-language designs.

I. ModelSim Conceptual Overview

a. Basic Simulation Flow

The following diagram shows the basic steps for simulating a design in ModelSim.

Create a working library

Compile design units

Run simulation

Debug Results

Creating the working library:

In ModelSim, all designs, be they VHDL, Verilog, or some combination thereof, are compiled
into a library. You typically start a new simulation in ModelSim by creating a working library
called "work". "Work" is the library name used by the compiler as the default destination for
compiled design units.

Compiling your design:

After creating the working library, you compile your design units into it. The ModelSim library
format is compatible across all supported platforms. You can simulate your design on any
platform without having to recompile your design.

Running the simulation:

With the design compiled, you invoke the simulator on a top-level module (Verilog) or a
configuration or entity/architecture pair (VHDL). Assuming the design loads successfully, the
simulation time is set to zero, and you enter a run command to begin simulation.

Debugging your results:

If you dont get the results you expect, you can use ModelSims robust debugging environment
to track down the cause of the problem.

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b. Project flow

A project is a collection mechanism for an HDL design under specification or test. Even though
you dont have to use projects in ModelSim, they may ease interaction with the tool and are
useful for organizing files and specifying simulation settings.

The following diagram shows the basic steps for simulating a design within a ModelSim
project.

Create a project

Add files to the project

Compile design files

Run Simulation

Debug Results

As you can see, the flow is similar to the basic simulation flow. However, there are two
important differences:
You do not have to create a working library in the project flow; it is done for you
automatically.
Projects are persistent. In other words, they will open every time you invoke ModelSim
unless you specifically close them.

c. Multiple library flow

ModelSim uses libraries in two ways: 1) as a local working library that contains the compiled
version of your design; 2) as a resource library. The contents of your working library will
change as you update your design and recompile. A resource library is typically static and
serves as a parts source for your design. You can create your own resource libraries, or they
may be supplied by another design team or a third party (e.g., a silicon vendor).
You specify which resource libraries will be used when the design is compiled, and there are
rules to specify in which order they are searched. A common example of using both a working
library and a resource library is one where your gate-level design and test bench are compiled

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into the working library, and the design references gate-level models in a separate resource
library.

The diagram shows the basic steps for simulating with multiple libraries.

Create a working library

Compile design files

Link to resource libraries

Run Simulation

Debug Results

You can also link to resource libraries from within a project. If you are using a project, you
would replace the first step above with these two steps: create the project and add the test-bench
to the project.

d. Debugging tools

ModelSim offers numerous tools for debugging and analyzing your design. Several of these
tools are covered in subsequent lessons, including:
Setting breakpoints and stepping through the source code
Viewing waveforms and measuring time
Viewing and initializing memories

II. BASIC SIMULATION

Creating the working design library:

Before you can simulate a design, you must first create a library and compile the source code
into that library.
1. Create a new directory and copy the tutorial files into it.
Start by creating a new directory for this exercise (in case other users will be working with
these lessons).

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Verilog: Copy counter.v and tcounter.v files from /<install_dir>/examples to the new
directory.
2. Start ModelSim if necessary.
a. Use the ModelSim icon in Windows.
Upon opening ModelSim for the first time, you will see the Welcome to ModelSim
dialog. Click Close.
b. Select File > Change Directory and change to the directory you created in step 1.
3. Create the working library.
a. Select File > New > Library.
This opens a dialog where you specify physical and logical names for the library.
(Fig. 1). You can create a new library or map to an existing library. Well be doing
the former.
b. Type work in the Library Name field if it isnt entered automatically.
c. Click OK.
ModelSim creates a directory called work and writes a specially-formatted file
named _info into that directory. The _info file must remain in the directory to
distinguish it as a ModelSim library. Do not edit the folder contents from your
operating system; all changes should be made from within ModelSim.
ModelSim also adds the library to the list in the Workspace (Fig. 2) and
records the library mapping for future reference in the ModelSim initialization
file (modelsim.ini).

When you pressed OK in step c above, three lines were printed to the Main window Transcript
pane:
vlib work
vmap work work
# Modifying modelsim.ini

The first two lines are the command-line equivalent of the menu commands you invoked. Most
menu driven functions will echo their command-line equivalents in this fashion. The third line
notifies you that the mapping has been recorded in the ModelSim initialization file.

Fig 1: Create a new library dialog

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Fig 2: The newly created work library

Compiling the design:

With the working library created, you are ready to compile your source files.
You can compile by using the menus and dialogs of the graphic interface, as in the Verilog
example below.

1. Verilog: Compile counter.v and tcounter.v.

a. Select Compile > Compile.
This opens the Compile Source Files dialog (Fig. 3).
If the Compile menu option is not available, you probably have a project open. If so,
close the project by selecting File > Close when the Workspace pane is selected.
b. Select counter.v, hold the <Ctrl> key down, and then select tcounter.v.
c. With the two files selected, click Compile.
The files are compiled into the work library.
d. Click Done.

2. View the compiled design units.

a. On the Library tab, click the + icon next to the work library and you will see two
design units (Fig. 4). You can also see their types (Modules, Entities, etc.) and the
path to the underlying source files if you scroll to the right.

Fig. 3: The Compile HDL Source Files dialog

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Fig. 4: Verilog modules compiled into the work library

Loading the design into the simulator:

1. Load the test_counter module into the simulator.

a. Double-click test_counter in the Main window Workspace to load the design.
You can also load the design by selecting Simulate > Start Simulation in the menu
bar. This opens the Start Simulation dialog. With the Design tab selected, click the
+ sign next to the work library to see the counter and test_counter modules. Select
the test_counter module and click OK (Fig. 5).

When the design is loaded, you will see a new tab named sim that displays the
hierarchical structure of the design (Fig. 6). You can navigate within the hierarchy
by clicking on any line with a + (expand) or - (contract) icon. You will also see
a tab named Files that displays all files included in the design.

Fig. 5: Loading the design with the Start Simulation dialog

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Fig. 6: Workspace tab showing a Verilog design

Running the simulation:

Now you will run the simulation.

1. Set the graphic user interface to view all debugging windows.
a) Select View > Debug Windows > All Windows.
This opens all ModelSim windows, giving you different views of your design data and
a variety of debugging tools. Most windows will open as panes within the Main
window. The Dataflow, List, and Wave windows will open as separate windows. You
may need to move or resize the windows to your liking. Panes within the Main window
can be undocked to stand alone.
2. Add signals to the Wave window.
a) In the Workspace pane, select the sim tab.
b) Right-click test_counter to open a popup context menu.
c) Select Add > Add to Wave (Fig. 7).
Three signals are added to the Wave window.
3. Run the simulation.
a) Click the Run icon in the Main or Wave window toolbar.
The simulation runs for 100 ns (the default simulation length) and waves are
drawn in the Wave window.
b) Type run 500 at the VSIM> prompt in the Main window.
The simulation advances another 500 ns for a total of 600 ns (Fig. 8).
c) Click the Run -All icon on the Main or Wave window toolbar.
The simulation continues running until you execute a break command or it
hits a statement in your code (e.g., a Verilog $stop statement) that halts the
simulation.
d) Click the Break icon.

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The simulation stops running.

Fig. 7: Adding signals to the Wave window

Fig. 8: Waves being drawn in the Wave window

Setting breakpoints and stepping in the Source window:

Next you will take a brief look at one interactive debugging feature of the ModelSim
environment. You will set a breakpoint in the Source window, run the simulation, and then step
through the design under test. Breakpoints can be set only on lines with red line numbers.
1. Open counter.v in the Source window.
a) Select the Files tab in the Main window Workspace.
b) Double-click counter.v to add it to the Source window.
2. Set a breakpoint on line 31 of counter.v.
a) Scroll to line 31 and click on the line number.
A red ball appears next to the line (Fig. 9) indicating that a breakpoint has been set.
3. Disable, enable, and delete the breakpoint.
a) Click the red ball to disable the breakpoint. It will become a black circle.

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b) Click the black circle to re-enable the breakpoint. It will become a red ball.
c) Click the red ball with your right mouse button and select Remove Breakpoint 31.
d) Click on line number 31 again to re-create the breakpoint.
4. Restart the simulation.
a) Click the Restart icon to reload the design elements and reset the simulation time to zero.
The Restart dialog that appears gives you options on what to retain during the restart
(Fig. 10).
b) Click Restart in the Restart dialog.
c) Click the Run -All icon.
The simulation runs until the breakpoint is hit. When the simulation hits the
breakpoint, it stops running, highlights the line with a blue arrow in the Source view
(Fig. 11), and issues a Break message in the Transcript pane.
When a breakpoint is reached, typically you want to know one or more signal values.
You have several options for checking values:
look at the values shown in the Objects window (Fig. 12).
set your mouse pointer over the count variable in the Source window, and a
"balloon" will pop up with the value (Fig. 11)
highlight the count variable in the Source window, right-click it, and select
Examine from the pop-up menu
use the examine command to output the value to the Main window Transcript
(i.e., examine count)
5. Try out the step commands.
a) Click the Step icon on the Main window toolbar.
This single-steps the debugger.
Experiment on your own. Set and clear breakpoints and use the Step, Step Over, and
Continue Run commands until you feel comfortable with their operation.

Fig. 9: A breakpoint in the Source window

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Fig. 10: The Restart dialog

Fig. 11: Resting the mouse pointer on a variable in the Source view

Figure 12: Values shown in the Objects window

Before continuing we need to end the current simulation.

1. Select Simulate > End Simulation.
2. Click Yes when prompted to confirm that you wish to quit simulating.

III. ModelSim Projects

Introduction
In this lesson you will practice creating a project. At a minimum, projects have a work library
and a session state that is stored in a .mpf file. A project may also consist of:
HDL source files or references to source files
other files such as READMEs or other project documentation
local libraries
references to global libraries
This lesson uses the Verilog files tcounter.v and counter.v in the examples.

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Creating a new project
1. If you just finished the previous lesson, ModelSim should already be running. If not, start
ModelSim.
a) Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows.
2. Create a new project.
a) Select Create a Project from the Welcome dialog or File > New > Project (Main
window) from the menu bar.
This opens a dialog where you enter a Project Name, Project Location (i.e., directory),
and Default Library Name (Fig. 13). The default library is where compiled design units
will reside.
b) Type test in the Project Name field.
c) Click Browse to select a directory where the project file will be stored.
d) Leave the Default Library Name set to work.
e) Click OK.
If you see the Select Initial Ini dialog, asking which modelsim.ini file you would like
the project to be created from, select the Use Default Ini button.

Fig. 13: The Create Project dialog

Adding objects to the project

Once you click OK to accept the new project settings, you will see a blank Project tab in the
workspace area of the Main window and the Add items to the Project dialog will appear (Fig.
14). From this dialog you can create a new design file, add an existing file, add a folder for
organization purposes, or create a simulation configuration (discussed below).
1. Add two existing files.
a) Click Add Existing File.
This opens the Add file to Project dialog (Fig. 15). This dialog lets you browse to find
files, specify the file type, specify which folder to add the file to, and identify whether
to leave the file in its current location or to copy it to the project directory.
b) Click Browse.
c) Open the examples directory in your ModelSim installation tree.
d) Verilog: Select counter.v, hold the <Ctrl> key down, and then select tcounter.v.
e) Click Open and then OK.
f) Click Close to dismiss the Add items to the Project dialog.
You should now see two files listed in the Project tab of the Workspace pane (Fig. 16).

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Question mark icons (?) in the Status column mean the file hasnt been compiled or the
source file has changed since the last successful compile. The other columns identify
file type (e.g., Verilog or VHDL), compilation order, and modified date.

Fig. 14: Adding new items to a project

Fig. 15: The Add file to Project dialog

Fig. 16: Newly added project files display a ? for status

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Compiling and loading a design

1. Compile the files.
a. Right-click anywhere in the Project tab and select Compile > Compile All from the pop-
up menu.
ModelSim compiles both files and changes the symbol in the Status column to a check
mark. A check mark means the compile succeeded. If the compile had failed, the symbol
would be a red X, and you would see an error message in the Transcript pane.
2. View the design units.
a. Click the Library tab in the workspace.
b. Click the "+" icon next to the work library.
You should see two compiled design units, their types (modules in this case), and the
path to the underlying source files (Fig. 17).
3. Load the test_counter design unit.
a. Double-click the test_counter design unit.
You should see a new tab named sim that displays the structure of the test_counter
design unit (Fig. 18). A fourth tab named Files contains information about the underlying
source files.
At this point you would generally run the simulation and analyze or debug your design
like you did in the previous lesson. For now, youll continue working with the project.
However, first you need to end the simulation that started when you loaded test_counter.
4. End the simulation.
a. Select Simulate > End Simulation.
b. Click Yes.

Fig. 17: The Library tab with an expanded library

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Fig. 18: The structure tab for the counter design unit

Simulation Configurations
A Simulation Configuration associates a design unit(s) and its simulation options.
For example, say every time you load tcounter.v you want to set the simulator resolution to
picoseconds (ps) and enable event order hazard checking. Ordinarily you would have to specify
those options each time you load the design. With a Simulation Configuration, you specify
options for a design and then save a "configuration" that associates the design and its options.
The configuration is then listed in the Project tab and you can double-click it to load counter.v
along with its options.

1. Create a new Simulation Configuration.

a) Select File > Add to Project > Simulation Configuration.
This opens the Simulate dialog (Fig. 19). The tabs in this dialog present a myriad of
simulation options. You may want to explore the tabs to see whats available. You can
consult the ModelSim Users Manual to get a description of each option.
b) Type counter in the Simulation Configuration Name field.
c) Select HDL from the Place in Folder drop-down.
d) Click the + icon next to the work library and select test_counter.
e) Click the Resolution drop-down and select ps.
f) For Verilog, click the Verilog tab and check Enable Hazard Checking.
g) Click OK.
The Project tab now shows a Simulation Configuration named counter (Fig. 20).
2. Load the Simulation Configuration.
a) Double-click the counter Simulation Configuration in the Project tab.
In the Transcript pane of the Main window, the vsim (the ModelSim simulator)
invocation shows the -hazards and -t ps switches (Fig. 21).
These are the command-line equivalents of the options you specified in the Simulate
dialog.

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Fig. 19: The Simulation Configuration dialog

Fig. 20: A Simulation Configuration in the Project tab

Fig. 21: Transcript shows options used for Simulation Configuration

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Before continuing you need to end the current simulation and close the current project.
1. Select Simulate > End Simulation. Click Yes.
2. Select the Project tab in the Main window Workspace.
3. Right-click the test project to open a context popup menu and select Close Project.
If you do not close the project, it will open automatically the next time you start
ModelSim.

RESULT:
Thus the design and simulation procedure for ModelSim tool is studied.

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SIMULATION OF COMBINATIONAL CIRCUITS

Aim:
To simulate the following basic modules using gate level modelling.

I. Half adder
II. Full adder
III. Half subtractor
IV. Full subtractor

Verilog code:

I. Half adder:

Source code:

module halfadder(cout,sum,a,b);
input a,b;
output cout,sum;
xor(sum,a,b);
and(cout,a,b);
endmodule

Stimulus:

module halfaddstim;
reg a,b;
wire cout,sum;
halfadder h1(cout, sum,a,b);
initial
begin
$monitor($time,"a=%b,b=%b,sum=%b,cout=%b",a,b,sum,cout);
end
initial
begin
a=1'b0;b=1'b0;
#5 a=1'b0;b=1'b1;
#5 a=1'b1;b=1'b0;
#5 a=1'b1;b=1'b1;
end
endmodule

Observation:

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# 0 a=0, b=0, sum=0, cout=0

# 5 a=0, b=1, sum=1, cout=0
# 10a=1, b=0, sum=1, cout=0
# 15a=1, b=1, sum=0, cout=1

Waveforms:

II. Full adder:

Source code:

module fulladder(sum,cout,a,b,c);
output sum,cout;
input a,b,c;
wire s1,c1,c2,c3;
xor(s1,a,b);
xor(sum,s1,c);
and(c1,a,b);
and(c2,b,c);
and(c3,a,c);
or(cout,c1,c2,c3);
endmodule

Stimulus:

module fulladdstim;
reg a,b,c;
wire sum,cout;
fulladder fa(sum,cout,a,b,c);
initial
begin
$monitor($time, "a=%b, b=%b, c=%b, sum=%b,
cout=%b",a,b,c,sum,cout);
end
initial
begin
a=1'b0;b=1'b0;c=1'b0;
#5 a=1'b0;b=1'b0;c=1'b1;
#5 a=1'b0;b=1'b1;c=1'b0;
#5 a=1'b0;b=1'b1;c=1'b1;
#5 a=1'b1;b=1'b0;c=1'b0;
#5 a=1'b1;b=1'b0;c=1'b1;
#5 a=1'b1;b=1'b1;c=1'b0;
#5 a=1'b1;b=1'b1;c=1'b1;

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end
endmodule

Observation:

# 0 a=0, b=0, c=0, sum=0, cout=0

# 5 a=0, b=0, c=1, sum=1, cout=0
# 10a=0, b=1, c=0, sum=1, cout=0
# 15a=0, b=1, c=1, sum=0, cout=1
# 20a=1, b=0, c=0, sum=1, cout=0
# 25a=1, b=0, c=1, sum=0, cout=1
# 30a=1, b=1, c=0, sum=0, cout=1
# 35a=1, b=1, c=1, sum=1, cout=1

Waveforms:

III. Half Subtractor:

Source code:

module halfsubtractor(d,b,x,y);
input x,y;
output d,b;
wire i1;
xor(d,x,y);
not(i1,x);
and(b,i1,y);
endmodule

Stimulus:

module halfsubstim;
reg x,y;
wire d,b;
halfsubtractor h1(d, b,x,y);
initial
begin
$monitor($time,"a=%b,b=%b,sum=%b,cout=%b",x,y,d,b);
end
initial
begin
x=1'b0;y=1'b0;
#5 x=1'b0;y=1'b1;

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#5 x=1'b1;y=1'b0;
#5 x=1'b1;y=1'b1;
end
endmodule

Observation:

# 0 a=0, b=0, sum=0, cout=0

# 5 a=0, b=1, sum=1, cout=1
# 10a=1, b=0, sum=1, cout=0
# 15a=1, b=1, sum=0, cout=0
Waveforms:

IV. Full Subtractor:

Source code:

module fullsub(d,b,x,y,z);
output d,b;
input x,y,z;
wire x1,a1,i1,o1,a2;
xor(x1,x,y);
xor(d,x1,z);
and(a1,y,z);
not(i1,x);
or(o1,y,z);
and(a2,i1,o1);
or(b,a2,a1);
endmodule

Stimulus:

module fullsubstim;
reg x,y,z;
wire d,b;
fullsub fa(d,b,x,y,z);
initial
begin
$monitor($time, "x=%b, y=%b, z=%b, d=%b, b=%b",x,y,z,d,b);
end
initial
begin
x=1'b0;y=1'b0;z=1'b0;

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#5 x=1'b0;y=1'b0;z=1'b1;
#5 x=1'b0;y=1'b1;z=1'b0;
#5 x=1'b0;y=1'b1;z=1'b1;
#5 x=1'b1;y=1'b0;z=1'b0;
#5 x=1'b1;y=1'b0;z=1'b1;
#5 x=1'b1;y=1'b1;z=1'b0;
#5 x=1'b1;y=1'b1;z=1'b1;
end
endmodule

Observation:

# 0x=0, y=0, z=0, d=0, b=0

# 5x=0, y=0, z=1, d=1, b=1
# 10x=0, y=1, z=0, d=1, b=1
# 15x=0, y=1, z=1, d=0, b=1
# 20x=1, y=0, z=0, d=1, b=0
# 25x=1, y=0, z=1, d=0, b=0
# 30x=1, y=1, z=0, d=0, b=0
# 35x=1, y=1, z=1, d=1, b=1

Waveforms:

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SIMULATION OF SEQUENTIAL CIRCUITS

Aim:
To simulate the following basic modules using behavioural modelling.

I. SR FLIP-FLOP
II. JK FLIP-FLOP
III. D FLIP-FLOP
IV. T FLIP-FLOP

Verilog code:

I. SR FLIP-FLOP:

Source code:

module srf(q,q1,s,r,clear,reset, clk);

input s,r,clear,reset, clk;
output q,q1;
reg q=1'b0,q1=1'b1;

always@(s or r or clk or reset or clear)

begin
if(clear==1'b1)
{q,q1}=2'b01;
else if(reset==1'b1)
{q,q1}=2'b10;
else
begin
case({s,r})
2'b10:{q,q1}=2'b10;
2'b01:{q,q1}=2'b01;
2'b00:{q,q1}={q,q1};
2'b11:$display("invalid");
endcase
end
end
endmodule

Stimulus:

module srf_stim;
reg s,r,clear,reset,clk;
wire q,q1;
always
#5 clk=~clk;
srf s1(q,q1,s,r,clear,reset, clk);
initial

$monitor($time,"clk=%b,clear=%b,reset=%b,s=%b,r=%b,q=%b,q1=%b",clk,clear,rese
t,s,r,q,q1);
initial
begin

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clear=1'b1; clk=1'b1;
#15 clear=1'b0; reset=1'b1;
#15 clear=1'b0; reset=1'b0; s=1'b1; r=1'b0;
#15 s=1'b0; r=1'b1;
#15 s=1'b0; r=1'b0;
#15 s=1'b1; r=1'b1;
#15 s=1'b1; r=1'b0;
#15 s=1'b0; r=1'b0;
end
endmodule

Observation:

# 0clk=1, clear=1, reset=x, s=x, r=x, q=0, q1=1

# 15clk=1, clear=0, reset=1, s=x, r=x, q=1, q1=0
# 30clk=1, clear=0, reset=0, s=1, r=0, q=1, q1=0
# 45clk=1, clear=0, reset=0, s=0, r=1, q=0, q1=1
# 60clk=1, clear=0, reset=0, s=0, r=0, q=0, q1=1
# invalid
# 75clk=1, clear=0, reset=0, s=1, r=1, q=0, q1=1
# 90clk=1, clear=0, reset=0, s=1, r=0, q=1, q1=0
# 105clk=1, clear=0, reset=0, s=0, r=0, q=1, q1=0.

Waveforms

II. JK FLIP-FLOP:

Source code:

module jkf(q,q1,j,k,clear,reset,clk);
input j,k,clear,reset,clk;
output q,q1;
reg q=1'b0,q1=1'b1;
always@(j or k or clk or reset or clear)
begin
if(clear==1'b1)
{q,q1}=2'b01;
else if(reset==1'b1)
{q,q1}=2'b10;
else
begin
case({j,k})
2'b10:{q,q1}=2'b10;
2'b01:{q,q1}=2'b01;

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2'b00:{q,q1}={q,q1};
2'b11:{q,q1}=~{q,q1};
endcase
end
end
endmodule

Stimulus:

module jkf_stim;
reg j,k,clear,reset,clk=1'b1;
wire q,q1;
always
#5 clk=~clk;
jkf s1(q,q1,j,k,clear,reset, clk);
initial
$monitor($time,"clk=%b, clear=%b, reset=%b, j=%b, k=%b, q=%b, q1=%b", clk,
clear,reset,j,k,q,q1);
initial
begin
clear=1'b1;
#15 clear=1'b0; reset=1'b1;
#15 clear=1'b0; reset=1'b0; j=1'b1; k=1'b0;
#15 j=1'b0; k=1'b1;
#15 j=1'b0; k=1'b0;
#15 j=1'b1; k=1'b1;
#15 j=1'b1; k=1'b0;
#15 j=1'b0; k=1'b0;
end
endmodule

Observation:

# 0clk=1, clear=1, reset=x, j=x, k=x, q=0, q1=1

# 15clk=1, clear=0, reset=1, j=x, k=x, q=1, q1=0
# 30clk=1, clear=0, reset=0, j=1, k=0, q=1, q1=0
# 45clk=1, clear=0, reset=0, j=0, k=1, q=0, q1=1
# 60clk=1, clear=0, reset=0, j=0, k=0, q=0, q1=1
# 75clk=1, clear=0, reset=0, j=1, k=1, q=1, q1=0
# 90clk=1, clear=0, reset=0, j=1, k=0, q=1, q1=0
# 105clk=1, clear=0, reset=0, j=0, k=0, q=1, q1=0

Waveforms

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III. D FLIP-FLOP:

Source code:

module df(q,q1,d,clear,reset,clk);
input d,clear,reset,clk;
output q,q1;
reg q=1'b0,q1=1'b1;

always@(d or clk or reset or clear)

begin
if(clear==1'b1)
{q,q1}=2'b01;
else if(reset==1'b1)
{q,q1}=2'b10;
else
begin
if(d==1)
{q,q1}=2'b10;
else
{q,q1}=2'b01;
end
end
endmodule

Stimulus:

module df_stim;
reg d,clear,reset,clk=1'b1;
wire q,q1;
always
#5 clk=~clk;
df d1(q,q1,d,clear,reset,clk);
initial
$monitor($time,"clk=%b, clear=%b, reset=%b, d=%b, q=%b, q1=%b",
clk, clear, reset, d, q, q1);
initial
begin
clear=1'b1;
#15 clear=1'b0; reset=1'b1;
#15 clear=1'b0; reset=1'b0;

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#15 d=1'b0;
#15 d=1'b1;
#15 d=1'b0;
#15 d=1'b1;
end
endmodule

Observation:

# 0clk=1, clear=1, reset=x, d=x, q=0, q1=1

# 15clk=1, clear=0, reset=1, d=x, q=1, q1=0
# 30clk=1, clear=0, reset=0, d=x, q=0, q1=1
# 45clk=1, clear=0, reset=0, d=0, q=0, q1=1
# 60clk=1, clear=0, reset=0, d=1, q=1, q1=0
# 75clk=1, clear=0, reset=0, d=0, q=0, q1=1
# 90clk=1, clear=0, reset=0, d=1, q=1, q1=0
Waveforms

IV. T FLIP-FLOP:

Source code:

module tf(q,q1,t,clear,reset,clk);
input t,clear,reset,clk;
output q,q1;
reg q=1'b0,q1=1'b1;
always@(t or clk or reset or clear)
begin
if(clear==1'b1)
{q,q1}=2'b01;
else if(reset==1'b1)
{q,q1}=2'b10;
else
begin
if(t==1)
{q,q1}=~{q,q1};
else
{q,q1}={q,q1};
end
end
endmodule

Stimulus:

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module tf_stim;
reg clk, t,clear,reset;
wire q,q1;
always
#5 clk=~clk;
tf t1(q,q1,t,clear,reset,clk);

initial
begin
$monitor($time,"clear=%b, reset=%b, t=%b, q=%b,
q1=%b",clk,clear,reset,t,q,q1);
clear=1'b1; clk=1'b1;
#15 clear=1'b0; reset=1'b1;
#15 clear=1'b0; reset=1'b0;
#15 t=1'b0;
#15 t=1'b1;
#15 t=1'b0;
#15 t=1'b1;
end
endmodule

Observation:

# 0clk=1, clear=1, reset=x, t=x, q=0, q1=1

# 15clk=1, clear=0, reset=1, t=x, q=1, q1=0
# 30clk=1, clear=0, reset=0, t=x, q=1, q1=0
# 45clk=1, clear=0, reset=0, t=0, q=1, q1=0
# 60clk=1, clear=0, reset=0, t=1, q=0, q1=1
# 75clk=1, clear=0, reset=0, t=0, q=0, q1=1
# 90clk=1, clear=0, reset=0, t=1, q=1, q1=0

Waveforms

Result:
Thus the basic modules were simulated using behavioural model and their
outputs are verified.

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Aim:
To simulate the following modules using behavioural modelling.

I. 4-bit synchronous up-down counter

Verilog code:

I. 4-bit synchronous up-down counter

Source code:

module counter (Q, CLK, CLR, up_down);

input CLK, CLR, up_down;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge CLK or posedge CLR)
begin
if (CLR)
tmp = 4'b0000;
else
if (up_down)
tmp = tmp + 1'b1;
else
tmp = tmp - 1'b1;
end
assign Q = tmp;
endmodule

Stimulus:

module counter_stim;
reg CLR, up_down;
wire[3:0] Q;
reg CLK=1'b0;
always
#1 CLK=~CLK;
counter c1(Q, CLK, CLR, up_down);
initial
$monitor($time, " clr=%b, up-down=%b, q=%b", CLR, up_down, Q);
initial
begin
CLR=1'b1;
#2 CLR =1'b0; up_down=1'b1;
#30 CLR =1'b0; up_down=1'b0;
#30 CLR=1'b1;
end
endmodule

Observation:

# 0 clr=1, up-down=x, q=0000

# 2 clr=0, up-down=1, q=0000
# 3 clr=0, up-down=1, q=0001

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# 5 clr=0, up-down=1, q=0010
# 7 clr=0, up-down=1, q=0011
# 9 clr=0, up-down=1, q=0100
# 11 clr=0, up-down=1, q=0101
# 13 clr=0, up-down=1, q=0110
# 15 clr=0, up-down=1, q=0111
# 17 clr=0, up-down=1, q=1000
# 19 clr=0, up-down=1, q=1001
# 21 clr=0, up-down=1, q=1010
# 23 clr=0, up-down=1, q=1011
# 25 clr=0, up-down=1, q=1100
# 27 clr=0, up-down=1, q=1101
# 29 clr=0, up-down=1, q=1110
# 31 clr=0, up-down=1, q=1111
# 32 clr=0, up-down=0, q=1111
# 33 clr=0, up-down=0, q=1110
# 35 clr=0, up-down=0, q=1101
# 37 clr=0, up-down=0, q=1100
# 39 clr=0, up-down=0, q=1011
# 41 clr=0, up-down=0, q=1010
# 43 clr=0, up-down=0, q=1001
# 45 clr=0, up-down=0, q=1000
# 47 clr=0, up-down=0, q=0111
# 49 clr=0, up-down=0, q=0110
# 51 clr=0, up-down=0, q=0101
# 53 clr=0, up-down=0, q=0100
# 55 clr=0, up-down=0, q=0011
# 57 clr=0, up-down=0, q=0010
# 59 clr=0, up-down=0, q=0001
# 61 clr=0, up-down=0, q=0000
# 62 clr=1, up-down=0, q=0000

Waveforms:

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Study of Xilinx ISE

I. Getting Started

Software Requirements:
To use this tutorial, you must install the following software:
ISE 9.1i

Hardware Requirements:
To use this tutorial, you must have the following hardware:
Spartan-3 Startup Kit, containing the Spartan-3 Startup Kit Demo Board

Starting the ISE Software

To start ISE, double-click the desktop icon, or start ISE from the Start menu by
selecting:

Start All Programs Xilinx ISE 9.1i Project Navigator

Accessing Help
To open Help, do either of the following:
Press F1 to view Help for the specific tool or function that you have selected or
highlighted.
Launch the ISE Help Contents from the Help menu. It contains information
about creating and maintaining your complete design flow in ISE.

Fig. 1: ISE Help Topics

II. Create a New Project

Create a new ISE project which will target the FPGA device on the Spartan-3 Startup
Kit demo board. To create a new project:
1. Select File > New Project. The New Project Wizard appears.
2. Type tutorial in the Project Name field.

3. Enter or browse to a location (directory path) for the new project. A tutorial
subdirectory is created automatically.

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4. Verify that HDL is selected from the Top-Level Source Type list.
5. Click Next to move to the device properties page.
6. Fill in the properties in the table as
shown below: Product
Category: All
Family: Spartan3E
Device: XC3S250E
Package: PQ208 Speed Grade: -4
Top-Level Source Type: HDL

Synthesis Tool: XST (VHDL / Verilog)

Simulator: ISE Simulator (VHDL / Verilog)
Preferred Language: Verilog (or VHDL)
Verify that Enable Enhanced Design Summary is selected.

Leave the default values in the remaining fields.

When the table is complete, your project properties will look like the following:

Figure 2: Project Device Properties

7. Click Next to proceed to the Create New Source window in the New Project
Wizard. At the end of the next section, your new project will be complete.

III. Create an HDL Source

In this section, you will create the top-level HDL file for your design. The language
used for the tutorial will be Verilog. Hence, continue the Creating a Verilog Source
section.

Creating a Verilog Source:

Create the top-level Verilog source file for the project as follows:
1) Click New Source in the New Project dialog box.

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2) Select Verilog Module as the source type in the New Source dialog box.
3) Type in the file name counter.
4) Verify that the Add to Project checkbox is selected.
5) Click Next.
6) Declare the ports for the counter design by filling in the port information as
shown below:

Figure 3: Define Module

7) Click Next, then Finish in the New Source Information dialog box to
complete the new source file template.
8) Click Next, then Next, then Finish.

The source file containing the counter module displays in the Workspace, and the
counter displays in the Sources tab, as shown below:

Figure 4: New Project in ISE

Using Language Templates (Verilog):
The next step in creating the new source is to add the behavioral description for
counter.

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Use a simple counter code example from the ISE Language Templates and
customize it for the counter design.
1) Place the cursor on the line below the output [3:0] COUNT_OUT; statement.
2) Open the Language Templates by selecting Edit Language
Templates Note: You can tile the Language Templates and the counter
file by selecting Window Tile Vertically to make them both visible.
3) Using the + symbol, browse to the following code example:
Verilog Synthesis Constructs Coding Examples Counters
Binary Up/Down Counters Simple Counter
4) With Simple Counter selected, select Edit Use in File, or select the Use
Template in File toolbar button. This step copies the template into the
counter source file.
5) Close the Language Templates.

Final Editing of the Verilog Source:

1) To declare and initialize the register that stores the counter value,
modify the declaration statement in the first line of the template as
follows:
replace: reg [<upper>:0]
<reg_name>; with: reg [3:0]
count_int = 0;
2) Customize the template for the counter design by replacing the port and signal
name placeholders with the actual ones as follows:
replace all occurrences of <clock> with CLOCK
replace all occurrences of <up_down> with
DIRECTION replace all occurrences of
<reg_name> with count_int
3) Add the following line just above the endmodule statement to assign the
register value to the output port:
assign COUNT_OUT = count_int;
4) Save the file by selecting File Save.

When you are finished, the code for the counter will look
like the following: module counter(CLOCK,
DIRECTION, COUNT_OUT);
input CLOCK; input DIRECTION;
output [3:0] COUNT_OUT; reg [3:0] count_int = 0;
always@(posedge CLOCK) if (DIRECTION)
count_int <= count_int + 1;
else
count_int <=
count_int - 1; assign COUNT_OUT =
count_int;
endmodule
You have now created the Verilog source for the tutorial project.

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Checking the Syntax of the New Counter Module:
When the source files are complete, check the syntax of the design to find errors
and typos.
1) Verify that Synthesis/Implementation is selected from the drop-down list in the
Sources window.
2) Select the counter design source in the Sources window to display the
related processes in the Processes window.
3) Click the + next to the Synthesize-XST process to expand the process group.
4) Double-click the Check Syntax process.

Note: You must correct any errors found in your source files. You can check for errors
in the Console tab of the Transcript window. If you continue without valid syntax, you
will not be able to simulate or synthesize your design.
5) Close the HDL file.

IV. Create Timing Constraints

Specify the timing between the FPGA and its surrounding logic as well as the
frequency the design must operate at internal to the FPGA. The timing is specified
by entering constraints that guide the placement and routing of the design. It is
recommended that you enter global constraints. The clock period constraint
specifies the clock frequency at which your design must operate inside the FPGA.
The offset constraints specify when to expect valid data at the FPGA inputs and
when valid data will be available at the FPGA outputs.

Entering Timing Constraints:

To constrain the design do the following:
1) Select Synthesis/Implementation from the drop-down list in the Sources
window.
2) Select the counter HDL source file.
3) Click the + sign next to the User Constraints processes group, and
double-click the Create Timing Constraints process.
ISE runs the Synthesis and Translate steps and automatically creates
a User Constraints File (UCF). You will be prompted with the
following message:

Figure 5: Prompt to Add UCF File to Project

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4) Click Yes to add the UCF file to your project.

The counter.ucf file is added to your project and is visible in the
Sources window. The Xilinx Constraints Editor opens
automatically.
Note: You can also create a UCF file for your project by selecting
Project Create New Source.
In the next step, enter values in the fields associated with CLOCK in the
Constraints Editor Global tab.
5) Select CLOCK in the Clock Net Name field, then select the Period
toolbar button or double-click the empty Period field to display the
Clock Period dialog box.
6) Enter 40 ns in the Time field.

Figure 6: Clock Period

7) Click OK.
8) Select the Pad to Setup toolbar button or double-click the empty Pad to Setup field
to display the Pad to Setup dialog box.
9) Enter 10 ns in the OFFSET field to set the input offset constraint.

Figure 7: Pad to Setup

10) Click OK.

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11) Select the Clock to Pad toolbar button or double-click the empty Clock to Pad field
to display the Clock to Pad dialog box.
12) Enter 10 ns in the OFFSET field to set the output delay constraint.

Figure 8: Clock to Pad

13) Click OK.

The constraints are displayed in the Constraints (read-write) tab, as shown below:

Figure 9: Timing Constraints

14) Save the timing constraints. If you are prompted to rerun the TRANSLATE or
XST step, click OK to continue.
15) Close the Constraints Editor.

V. Implement Design and Verify Constraints

Implement the design and verify that it meets the timing constraints specified in the
previous section.
Implementing the Design
1) Select the counter source file in the Sources window.
2) Open the Design Summary by double-clicking the View Design Summary
process in the Processes tab.
3) Double-click the Implement Design process in the Processes tab.
4) Notice that after Implementation is complete, the Implementation processes have a green

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check mark next to them indicating that they completed successfully without Errors or
Warnings.

Figure 10: Post Implementation Design Summary

5) Locate the Performance Summary table near the bottom of the Design
Summary.
6) Click the All Constraints Met link in the Timing Constraints field to view the
Timing Constraints report. Verify that the design meets the specified timing
requirements.

Figure 11: All Constraints Met Report

7) Close the Design Summary.

Assigning Pin Location Constraints:

Specify the pin locations for the ports of the design so that they are
connected correctly on the Spartan-3 Startup Kit demo board.

To constrain the design ports to package pins, do the following:

1) Verify that counter is selected in the Sources window.
2) Double-click the Assign Package Pins process found in the User Constraints
process group. The Xilinx Pinout and Area Constraints Editor (PACE) opens.
3) Select the Package View tab.
4) In the Design Object List window, enter a pin location for each pin in the Loc

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column using the following information:
CLOCK input port connects to FPGA pin T9 (GCK0 signal on board)
COUNT_OUT<0> output port connects to FPGA pin K12 (LD0 signal on
board)
COUNT_OUT<1> output port connects to FPGA pin P14 (LD1 signal on
board)
COUNT_OUT<2> output port connects to FPGA pin L12 (LD2 signal on
board)
COUNT_OUT<3> output port connects to FPGA pin N14 (LD3 signal on
board)
DIRECTION input port connects to FPGA pin K13 (SW7 signal on board)

Notice that the assigned pin locations are shown in blue:

Figure 12: Package Pin Locations

5) Select File Save. You are prompted to select the bus delimiter type based
on the synthesis tool you are using. Select XST Default <> and click OK.
6) Close PACE.

Notice that the Implement Design processes have an orange question mark next to
them, indicating they are out-of-date with one or more of the design files. This is
because the UCF file has been modified.

VI. Re-implement Design and Verify Pin Locations

Reimplement the design and verify that the ports of the counter design are routed to
the package pins specified in the previous section.
First, review the Pinout Report from the previous implementation by doing the
following:
1) Open the Design Summary by double-clicking the View Design
Summary process in the Processes window.
2) Select the Pinout Report and select the Signal Name column header to sort
the signal names. Notice the Pin Numbers assigned to the design ports in
the absence of location constraints.

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Figure 13: Package Pin Locations Prior to Pin Location Constraints

3) Reimplement the design by double-clicking the Implement Design process.

4) Select the Pinout Report again and select the Signal Name column header
to sort the signal names.
5) Verify that signals are now being routed to the correct package pins.

Figure 14: Package Pin Locations after Pin Location Constraints

6) Close the Design Summary.

VII. Download Design to the Spartan-3 Demo Board

This is the last step in the design verification process. This section provides simple
instructions for
downloading the counter design to the Spartan-3 Starter Kit demo board.

1) Connect the 5V DC power cable to the power input on the demo board (J4).
2) Connect the download cable between the PC and demo board (J7).
3) Select Synthesis/Implementation from the drop-down list in the Sources
window.

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4) Select counter in the Sources window.
5) In the Processes window, click the + sign to expand the Generate Programming File
processes.
6) Double-click the Configure Device (iMPACT) process.
7) The Xilinx WebTalk Dialog box may open during this process. Click Decline.
8) Select Disable the collection of device usage statistics for this project

only and click OK. iMPACT opens and the Configure Devices dialog

box is displayed.

Figure 15: iMPACT Welcome Dialog Box

9) In the Welcome dialog box, select Configure devices using Boundary-Scan

(JTAG).
10) Verify that Automatically connect to a cable and identify Boundary-Scan chain
is selected.
11) Click Finish.
12) If you get a message saying that there are two devices found, click OK to
continue.
The devices connected to the JTAG chain on the board will be detected and
displayed in the iMPACT window.
13) The Assign New Configuration File dialog box appears. To assign a
configuration file to the xc3s200 device in the JTAG chain, select the
counter.bit file and click Open.

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Figure 16: Assign New Configuration File

14) If you get a Warning message, click OK.

15) Select Bypass to skip any remaining devices.
16) Right-click on the xc3s200 device image, and select Program... The
Programming Properties dialog box opens.
17) Click OK to program the device.
When programming is complete, the Program Succeeded message is displayed.
On the board, LEDs 0, 1, 2, and 3 are lit, indicating that the counter is running.
18) Close iMPACT without saving.

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Study of Xilinx FPGA Trainer Kit

Kit Specifications

1. FPGA Specifications:

1.1 Hardware:
Family: Spartan3E
Device: XC3S250E
Package: PQ208
Speed Grade: -4

1.2 Software:
Synthesis Tool: XST (VHDL/Verilog)
Simulator: ISE Simulator (VHDL/Verilog)

2. Other hardware:

2.1 Clock Generation:

The trainer kit has two clock sources:
Fixed clock of 4MHz connected to PIN No: 181
Manual clock by push-to-on switch connected to PIN No: 178. When the key is
pressed once, one positive going pulse will be applied to the clock pin of FPGA.

2.2 Input Signal Generation:

The input signal level is generated using DIP switches. The DIP-switch has 8 separate
switches. The switch diagram is shown below:

Switch S2
Signal S2-1 S2-2 S2-3 S2-4 S2-5 S2-6 S2-7 S2-8
Pin 159 169 174 175 183 184 194 204

Switch
S3
Signal S3-1 S3-2 S3-3 S3-4 S3-5 S3-6 S3-7 S3-8
Pin 159 169 174 175 183 184 194 204

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When the switch is ON position the output will be 0 level, which is fed to FPGA as
input. When the switch is OFF position the output of this will be 1 level. The RC is
used to limit the current, while connecting to ground point.

2.3 Outputs:
The FPGA device outputs are connected to bar-graph LEDs which shows the output
level. The output is 1 level the LED will be glowing and when the output is at 0 level
the LED will be in off.

2.4 Bi-directional Lines:

The PIN Nos. 106, 107, 108, 109, 112, 113, 115 & 116 of FPGA can be used as bi-
directional, in which the output can be viewed at DS7 and the input can be set by switch
S1. The circuit diagram of single line is given below:

Switch S1
Signal S1-1 S1-2 S1-3 S1-4 S1-5 S1-6 S1-7 S1-8
Pin 106 107 108 109 112 113 115 116

2.5 Edge Triggered Signals:

PIN Nos. 126, 127 and 128 are connected to push-to-on switches, which generate a
positive going pulse.

2.6 Keyboard:
The trainer kit has a 4*4 key matrix connected to the FPGA I/O lines. The connection
details are given below:

Scan Lines Return Lines

SC0 123 RT0 137
SC1 122 RT1 138
SC2 120 RT2 139
SC3 119 RT3 140

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2.7 Seven Segment Display:

The trainer kit has 4 digit seven segment displays, which are multiplexed. The connection
detail is given below.

2.8 LCD:
The trainer kit has one 16*2 LCD display. The connection details are given below:

LCD Control Signals

Signa
l RS R/W EN
Pin 55 61 62

LCD Data lines

Signa
l D0 D1 D2 D3 D4 D5 D6 D7
Pin 63 64 65 68 69 76 89 90
- LCD Register Select
RS Signal
R/W - LCD Read / Write Signal
- LCD Enable
EN Signal
D7-D0 - LCD Data
Lines

2.9 26-pin FRC Lines:

FRC Pin 1 2 3 4 5 6 7 8 9 10 11 12 13
FPGA
Pin 2 3 4 5 8 9 11 12 15 16 18 19 33
FRC Pin 14 15 16 17 18 19 20 21 22 23 24 25 26
FPGA
Pin 34 35 36 39 40 41 42 45 47 129 132 +5V GND

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FPGA Kit Interfacing Diagram

Fig. 1 FPGA Spartan3E-250K

Fig. 2 Seven-segment display interface

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Fig. 3 Matrix Keypad interface

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Ripple Carry Adder- Implementation using Spartan FPGA

Aim:
To design a 4-bit Ripple carry adder and demonstrate its working on a Xilinx FPGA
Trainer Kit.

Tools Required:

Hardware:
Family: SPARTAN 3E
Device: XC3S250E
Package: PQ208
Speed: 4
Software:
Xilinx 9.1i

PROCEDURE:

1. Simulation :

Load ModelSim simulator.

Open a new project and VerilogHDL programs for the given circuits in all the
four
models of the project.
Simulate and verify the functionality of the circuit.

Program:

module ripple(sum,cout,a,b,cin);
output [3:0] sum;
output cout;
input [3:0] a,b;
input cin;
wire c1,c2,c3;
fulladd f1(sum[0],c1,a[0],b[0],cin);
fulladd f2(sum[1],c2,a[1],b[1],c1);
fulladd f3(sum[2],c3,a[2],b[2],c2);
fulladd f4(sum[3],cout,a[3],b[3],c3);
endmodule

module fulladd(sum,cout,a,b,c);
output sum,cout;
input a,b,c;
assign sum=a^b^c;
assign cout=(a&b)|(b&c)|(c&a);
endmodule

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Simulation Result:

2. SCHEMATIC EDITOR:
Load Xilinx project navigator.
Create new project.
Create new source (schematic).
Draw the given circuit diagram using schematic editor.
View the RTL level schematic.
Synthesis project and verify the results in modelsim.

Circuit for full adder:

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Circuit for 4-bit ripple carry adder:

Synthesis Report:

Result:
Thus the ripple carry adder circuits are designed using verilog and their outputs were
demonstrated in Xilinx FPGA trainer.

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Booth Multiplier- Implementation using Spartan FPGA

Aim:
To design a booth multiplier and demonstrate its working on a Xilinx FPGA Trainer
Kit.

Tools Required:

Hardware:
Family: SPARTAN 3E
Device: XC3S250E
Package: PQ208
Speed: 4
Software:
Xilinx 9.1i

PROCEDURE:

3. Simulation :

Load Modelsim simulator.

Open a new project and verilog programs for the given circuits in all the four
models of the project.
Simulate and verify the functionality of the circuit.

Program:
module multiplier(prod, busy, mc, mp, clk);
output [15:0] prod;
output busy;
input [7:0] mc, mp;
input clk;
reg [7:0] A, Q, M;
reg Q_1;
reg [3:0] count=3'b000;
wire [7:0] sum, difference;
always @(negedge clk)
begin
if (count==0) begin
A <= 8'b0;
M <= mc;
Q <= mp;
Q_1 <= 1'b0;
count <= 8;
end
else begin
case ({Q[0], Q_1})
2'b0_1 : {A, Q, Q_1} <= {sum[7], sum, Q};
2'b1_0 : {A, Q, Q_1} <= {difference[7], difference, Q};
default: {A, Q, Q_1} <= {A[7], A, Q};
endcase
count <= count - 1'b1;
end
end
alu adder (sum, A, M, 1'b0);

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alu subtracter (difference, A, ~M, 1'b1);
assign prod = {A, Q};
assign busy = (count != 0);
endmodule

//The following is an alu.

//It is an adder, but capable of subtraction:
//Recall that subtraction means adding the two's complement--
//a - b = a + (-b) = a + (inverted b + 1)
//The 1 will be coming in as cin (carry-in)

module alu(out, a, b, cin);

output [7:0] out;
input [7:0] a;
input [7:0] b;
input cin;
assign out = a + b + cin;
endmodule

4. SCHEMATIC EDITOR:

Load Xilinx project navigator.

Create new project.
Create new source (schematic).
Draw the given circuit diagram using schematic editor.
View the RTL level schematic.
Synthesis project and verify the results in modelsim.

BLOCK DIAGRAM:

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RTL SCHEMATIC:

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SYNTHESIS REPORT:

Result:
Thus the BOOTH MULTIPLIER circuit is designed using verilog and the output was
demonstrated in Xilinx FPGA trainer.

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Moore FSM
1011 overlapping sequence detector. Output becomes 1 when sequence is detected in state S4 else it
remains 0 for other states.

Verilog Code for FSM:

// 4-State Moore state machine
// A Moore machine's outputs are dependent only on the current state.
// The output is written only when the state changes. (State
// transitions are synchronous.)
module seq_dect
(
input clk, data_in, reset,
output reg data_out
);
// Declare state register
reg [2:0]state;
// Declare states
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;

// Determine the next state

always @ (posedge clk or posedge reset) begin
if (reset)
state <= S0;
else
case (state)
S0:
if (data_in)
state <= S1;
else
state <= S0;
S1:
if (data_in)
state <= S1;
else
state <= S2;
S2:
if (data_in)
state <= S3;
else

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state <= S2;
S3:
if (data_in)
state <= S4;
else
state <= S2;
S4:
if (data_in)
state <= S1;
else
state <= S2;
endcase // case (state)
end // always @ (posedge clk or posedge reset)
// Output depends only on the state
always @ (state) begin
case (state)
S0:
data_out = 1'b0;
S1:
data_out = 1'b1;
S2:
data_out = 1'b0;
S3:
data_out = 1'b1;
S4:
data_out = 1'b1;
default:
data_out = 1'b0;
endcase // case (state)
end // always @ (state)

endmodule // moore_mac

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