Digital Logic Design, EE Department, Wah Engineering College

EXPERIMENT NO. : 13

(a) Implementation and Verification of R-S flip flop and D flip flop
(b) Design of 3-bit Synchronous Counter using JK Flip Flop

Part (a)

Objective:
The aim of this experiment is to study the fundamentals of basic memory units and to
become familiar with various types of flip-flops.

Apparatus:
Logic trainer
IC: NAND,NOT
Power supply

Theory:
RS flip-flop is also called Synchronous flip-flop. That means that this flip-flop is
concerned with time. Digital circuits can have a concept of time using a clock signal. The
clock signal simply goes from low-to-high and high-to-low in a short period of time.

RS flip-flop and its truth table

In case of D flip-flop, The Q output always takes on the state of the D input at the
moment of a rising clock edge. (or falling edge if the clock input is active low). It is
called the D flip-flop for this reason, since the output takes the value of the D input or
Data input, and Delays it by one clock count. The D flip-flop can be interpreted as a
primitive memory cell, zero-order hold, or delay line.
 Digital Logic Design, EE Department, Wah Engineering College

D flip-flop and its truth table

Procedure:
Construct the circuits shown logic diagrams.
Connect inputs to switches of logic trainer and output to LED.
Apply various combinations of inputs and observe the conditions of LEDs.
Mark results in truth table.

Observations & Calculations:

Truth table for RS flip flop

Clock Inputs Outputs

Comments
S R Q Q

Truth table for D flip flop

Clock Inputs Outputs

Comments
D Q Q
 Digital Logic Design, EE Department, Wah Engineering College

Part (b)

Objective:
The aim of this experiment is to study the fundamentals of basic memory units and to
become familiar with various types of counters
Apparatus:
Logic trainer
IC: NAND,NOT, JK Flip Flop 7476
Power supply

Theory:

A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. A specified sequence of states appears as
counter output. This is the main difference between a register and a counter. There are two types
of counter, synchronous and asynchronous. In synchronous common clock is given to all flip flop
and in asynchronous first flip flop is clocked by external pulse and then each successive flip flop
is clocked by Q or Q output of previous stage. A soon the clock of second stage is triggered by
output of first stage. Because of inherent propagation delay time all flip flops are not activated at
same time which results in asynchronous operation.
 Digital Logic Design, EE Department, Wah Engineering College

Comments:

Conclusion:
 Digital Logic Design, EE Department, Wah Engineering College

Questions:

1. Write three differences between synchronous counter and asynchronous

counter?

2. How will you design 3-bit synchronous counter using JK flip flop?