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HomeELECTRONICSVLSI/VHDL/VerilogDSPApplicationsAnEfficientConstantMultiplierArchitectureBasedonVerticalHorizontalBinaryCommonSubexpressionEliminationAlgorithmforReconfigurableFIRFilterSynthesis.
2015

AN EFFICIENT CONSTANT MULTIPLIER ARCHITECTUREBASED ON VERTICAL-HORIZONTAL

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BINARY COMMONSUB-EXPRESSION ELIMINATION ALGORITHM FORRECONFIGURABLE FIR
FILTER SYNTHESIS. 2015 Name

DSPApplications February3,2017
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ProjectTitle:

An Efficient Constant Multiplier ArchitectureBased on VerticalHorizontal Binary Email

CommonSubexpression Elimination Algorithm forReconfigurable FIR Filter
Synthesis.2015
Subject
Abstract:
Re: An Efficient Constant Multiplier ArchitectureBased on VerticalHorizontal Binary C

This paper proposes an efficient constant multiplier architecture based on Message

verticalhorizontal binary common subexpression elimination (VHBCSE)
algorithmfordesigningareconfigurablefiniteimpulseresponse(FIR)filterwhose
coefficients can dynamically change in real time. To design an efficient
reconfigurable FIR filter, according to the proposed VHBCSE algorithm, 2bit
binarycommonsubexpressionelimination(BCSE)algorithmhasbeenappliedverticallyacrossadjacentcoefficientsonthe2Dspace
ofthecoefficientmatrixinitially,followedbyapplyingvariablebitBCSEalgorithmhorizontallywithineachcoefficient.Thistechniqueis
capable of reducing the average probability of use or the switching activity of the multiplier block adders by 6.2% and 19.6% as
compared to that of two existing 2bit and 3bit BCSE algorithms respectively. ASIC implementation results of FIR filters using this
multipliershowthattheproposedVHBCSEalgorithmisalsosuccessfulinreducingtheaveragepowerconsumptionby32%and52%
alongwithanimprovementintheareapowerproduct(APP)by25%and66%comparedtothoseofthe2bitand3bitBCSEalgorithms
respectively.AsregardstheimplementationofFIRfilter,improvementsof13%and28%inareadelayproduct(ADP)and76.1%and I'm not a robot
77.8% in power delay product (PDP) for the proposed VHBCSE algorithm have been achieved over those of the earlier multiple reCAPTCHA
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constantmultiplication(MCM)algorithms,viz.faithfullyroundedtruncatedmultipleconstantmultiplication/accumulation(MCMAT)and
multiroot binary partition graph (MBPG) respectively. Efficiency shown by the results of comparing the FPGA and ASIC SEND INQUIRY
implementationsofthereconfigurableFIRfilterdesignedusingVHBCSEalgorithmbasedconstantmultiplierestablishesthesuitability
oftheproposedalgorithmforefficientfixedpointreconfigurableFIRfiltersynthesis.

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