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ACKNOWLEDGEMENT

It is great pleasure for me to express my grateful thanks to Dr.K.RAVINDRA,

our honourable Principal, MallaReddy Institute of Technology and Science, who had

inspired a lot through his speeches. He is the only personality who had given the meaning

to the technological studies and told us to survive in this competitive world.

I express our deep sense of gratitude and heart full thanks to Mrs.N.NEELIMA,

Head of the Department of Electronics and Communication Engineering, MRITS for her

cheerful motivation and encouragement at each stage of this endeavour.

I would also like to thank all the staff of the Department of ECE who jave been

helpful directly or indirectly in making the project a success.

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ABSTRACT
Owing to the rapid growth in portable electronic devices with
constraint of power, it becomes a critical challenge as well as a
competitive task to design high performance, small chip area and low
power consumption circuits to enhance product competitiveness for
integrated circuit designers nowadays. The full adder is regarded as
the most signifcant and crucial building block in an arithmetic unit of
portable devices in todays highly competitive markets. Therefore it
becomes a hot issue to design a low-power, high-speed FA (LPHS-FA)
occupying a small chip area.

A low-power, high-speed full adder, abbreviated as LPHS-FA, is designed as an


elegant way to reduce circuit complexity and improve the performance thereof. The
LPHS-FA which consists of three modules named as XOR-XNOR module, Carry Module
and Sum Module were designed using Pass Transistor Logic and Transmission Gate
Logics respectively to reduce the number of transistors in a chip. Employing as few as 15
MOSFETs in total, the LPHS-FA is designed using MENTOR GRAPHICS Chip design
tools using 0.18-m CMOS process technology. In short, an LPHS-FA is presented in a
concise form as a high-performance FA in practical applications.

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LIST OF FIGURES
S.No. Title Page.No.
Figure 2.1.1 Schematic Symbol of 1-Bit Full Adder 4
Figure 2.1.2 Circuit Diagram of 1-bit Full Adder 5
Figure 2.1.3 Power Break Down in High Performance Microprocessor 6
Figure 2.2.1 4-bit Ripple Carry Adder 6
Figure 2.2.2 4-bit Carry-Look ahead Adder 7
Figure 2.2.3 Carry Select Adder 8
Figure 2.2.4 Carry Skip Adder 9
Figure 2.2.5 Proposed DPTAAL Full Adder Logic Diagram 10
Figure 3.2.1 CMOS Inverter Mode for Static Power Consumption 13
Figure 3.2.2 Model Describing Parasitic Diodes Present in CMOS
Inverter 13
Figure 3.3.1 Symbol and truth table of Pass Transistor 18
Figure 3.4.1 Basic designs using Complimentary Pass Transistor Logic 19
Figure 3.4.2 Complimentary Pass Transistor Logic 20
Figure 4.1.1 Schematic of NOT gate 21
Figure 4.1.2 Test bench of NOT gate 22
Figure 4.1.3 Wave form of NOT gate 22
Figure 4.2.1 Schematic of NAND gate 23
Figure 4.2.2 Test bench of NAND gate 23
Figure 4.2.2 Wave form of NAND gate 24
Figure 4.3.1 schematic of AND gate 24
Figure 4.3.2 Test bench of AND gate 25
Figure 4.3.3 Wave form of AND gate 25
Figure 4.4.1 schematic of OR gate 26
Figure 4.4.2 Test bench of OR gate 26
Figure 4.4.3 Wave form of OR gate 26

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Figure 4.5.1 schematic of XOR-XNOR module 27
Figure 4.5.2 Test bench of XOR-XNOR module 27
Figure 4.5.3 Wave form of XOR-XNOR module 28
Figure 4.6.1 schematic of CARRY module 29
Figure 4.6.2 Test bench of CARRY module 29
Figure 4.6.3 Wave form of CARRY module 30
Figure 4.7.1 schematic of SUM module 31
Figure 4.7.2 Test bench of SUM module 31
Figure 4.7.3 Wave form of SUM module 32
Figure 4.8.1 Pass transistor logic 33
Figure 4.8.2 Full adder using pass transistor logic 34
Figure 4.8.3 Full adder using pass transistor logic test bench 34
Figure 4.9.1 Full adder using complementary pass transistor logic 35
Figure 4.9.2 Full adder using complementary pass transistor logic 36
Test bench
Figure 4.10.1 Control and regeneration block schematic 37
Figure 4.10.2 Control and regeneration block schematic test bench 37
Figure 5.2 Full custom design flow 39
Figure 5.3 Proposed LPHS Full Adder Schematic 40
Figure 5.4 Symbol of Full Adder 41
Figure 5.5 Proposed LPHS Full Adder Test Bench 41
Figure 6.1 Final block simulation report 45
Figure 6.2.1 Simulation Result of LPHS Full adder 46
Figure 6.2.2 Simulation Result of LPHS Full Adder for carry 46
Figure 6.2.3 Simulation Result of LPHS Full Adder for sum 47
Figure 6.2.4 Simulation Result of LPHS Full Adder for XOR-XNOR 47
Figure 6.2.5 Simulation Result of LPHS Full Adder for AND 48
Figure 6.2.6 Simulation Result of LPHS Full Adder for NAND 48
Figure 6.2.7 Simulation Result of LPHS Full Adder for INVERTER 49
Figure 6.2.8 Simulation Result of LPHS Full Adder for OR 49

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LIST OF TABLES
S.No. Title Page No.
Table 1.1.1 Truth table of full adder 2

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ABBREVATIONS

PMOS : Positive Metal Oxide Semiconductor


NMOS : Negative Metal Oxide Semiconductor
CMOS : Complementary Metal Oxide Semiconductor
PT : Pass Transistor
CPL : Complementary Pass Transistor
DRC : Design Rule Check
LVS : Layout Versus Schematic
IC : Integrated circuit
VLSI : Very Large Scale Integration
PDP : Power Delay Product
LPHS : Low Power High Speed
H-SPICE : Hewlett Simulation Program with Integrated Circuit Emphasis
TSMC : Taiwan Semiconductor Manufacturing Company Limited

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