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HomeELECTRONICSVLSI/VHDL/VerilogCoreProjectsA520k(18900,17010)ArrayDispersionLDPCDecoderArchitecturesforNANDFlashMemory2016

A 520K (18 900, 17 010) ARRAY DISPERSION LDPC DECODER ARCHITECTURES FOR NAND-

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FLASH MEMORY 2016
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CoreProjects February13,2017

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A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for
NANDFlashMemory2016
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Abstract:
Subject
Though Latin square may be a wellknown algorithm to construct lowdensity
paritycheck (LDPC) codes for satisfying long code length, high coderate, Re: A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for NAND
sensiblecorrectingcapability,andlowerrorfloor,ithasadrawbackofhugesub
Message
matrixthatthehardwareimplementationcanbesufferedfromgiantbarrelshifter
andworseroutingcongestioninfittingNANDflashapplications.Inthispaper,a
topdown style methodology, which not solely goes through code construction
andoptimization,butadditionallyhardwareimplementationtomeetallthecriticalnecessities,ispresented.A2steparraydispersion
algorithm is proposed to construct long LDPC codes with a tiny sub matrix size. Then, the constructed LDPC code is optimized by
maskingmatrixtoobtainhigherbiterrorrate(BER)performanceandlowererrorfloor.Inaddition,ourLDPCcodeshaveadiagonallike
structureintheparitycheckmatrixresultinginaproposedhybridstoragearchitecture,thathastheadvantagesofbetterareaefficiency
andmassiveenoughdatabandwidthforprimedecodingthroughput.TobeadoptedforNANDflashapplications,an(eighteen900,17
010)LDPCcodewithacoderateof0.9andsubmatrixsizeofsixtythreeismadeandthesectorprogrammablegatearraysimulations
showthattheerrorfloorissuccessfullysuppressedrightdowntoBERof1012.Theproposeddesignofthispaperanalysisthelogic
size,spaceandpowerconsumptionusingXilinxfourteen.2.
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