SQWIRE

Welcome to the world of

JUNCTIONLESS NANOWIRE FETs!

Isabelle FERAIN
Tyndall National Institute
University College Cork

www.tyndall.ie 1
 Dimensions scaling

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 Voltage scaling

Dynamic power dissipation in present CMOS

circuits at frequency, f, supply voltage, VDD and
load capacitance Cload can be described by: Pdynamic Cload Vdd2 fcycle

3
10

Any reduction of power consumption thus requires 10

2
Vds=0.9V

to reduce supply voltage 1 Vds=0.05V

Drain current (A/m)

10
0
10
-1
10
Vdd scaling is 10
-2

set by the threshold voltage of transistors 10

-3

Gate length = 70nm

dependent on the inverse sub-threshold slope
-4
10 W=25nm

(kT/q)
-5
10
0 0.5 1 1.5
Gate voltage (V)
limited by short-channel effects
Courtesy:
Prof. Gerard Ghibaudo (IMEP)
Enhanced coupling between gate and channel

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 Enhanced Electrostatic Control

Gate-all-Around
3 Gates
2 Gates

Gate Source

1 Gate
Drain
ID

Buried oxide
Gate
Polysilicon Gate
Source Drain
Silicon
BOX Fin
Gate

Gate

Gate
20 nm Buried Oxide
Source Drain

Buried oxide Tri-Gate with 800C 600Torr 5min H2Anneal

Fins are 45x78nm, Nice corner rounding by H2 anneal
Back gate (substrate)

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 Does it look too good to be true?

Improved Lg scalability
Almost ideal sub-threshold slope (60mV/dec) at RT
Low drain-to-source current (IOFF)

Drive current ION

crystal orientation dependence
High nano-wire pitch density
Source/Drain resistance Rsd
SEG / Layout optimization needed

Critical Dimensions
Critical Dimensions
Gate length
Nano-wire width
Gate oxide thickness
Junction abruptness
Junction Depth

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Junctionless nanowire transistors

DEVICE STRUCTURE

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 Device Structure (1/2)

3
10
2
Vds=0.9V
10
1 Vds=0.05V

Drain current (A/m)

10
0
10
DIBL
Hooray!!
-1
10
-2

No need for source &

10
-3
10
drain engineering 10
-4 Gate length = 20nm
W=25nm
anymore! 10
-5

0 0.5 1 1.5
Gate voltage (V)

J.-P. Colinge et al., Nanowire transistors without junctions, Nature Nanotechnology, Vol. 5, No. 3, pp. 225-229, 2010.

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 Device structure (2/2)

Gate
Source

Drain

Gate
Silicon
Oxide
Nanowire

BOX

The cross-section of the

channel must be small enough
so that the gate can deplete
the heavily doped channel
entirely (OFF state)
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Junctionless nanowire transistors

CONDUCTION MECHANISM

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 Conduction mechanism (1/4)

Electrostatic pinch-off:
The cross section is small enough for the channel region to be depleted
(VD=50mV, Nd>5e18/cm3)

Below VTH Slightly above VTH

Depletion is gone
Higher VG

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 Conduction mechanism (2/4)

VD=50mV VG > VTH

VD=200mV

-4
10
5x5_Lgate=10nm, tox=2nm
10
-6 VDS=1.0V VD=400mV
Drain Current (A)

-8
VDS=50mV
10

-10

VD=600mV
10

-12
10

-14
DIBL S/S
10
Junction-less : 48 mV 66.2 mV/dec
Inversion-mode : 153 mV 83.8 mV/dec
-16
10
-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
Gate Voltage (V)

Channel pinch-off
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 Conduction mechanism (3/4)

Below Threshold

a BOX b BOX c BOX

Above Threshold

d BOX e BOX f BOX

Inversion Accumulation
Junctionless
Mode Mode

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 Conduction mechanism (4/4)

Channel in Multigate FETs @ VG= VG =1V

N+PN+ N+N+N+
Inversion Junctionless
Mode Ninv>1x1020 cm
-3 ND=1x1019cm-3

n=4x1019 cm
-3

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Junctionless nanowire transistors

MOBILITY

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 Electron Mobility (1/2)

N+PN+ VG= VG =1V N+N+N+ Junctionless

Inversion Mode ND=1x1019cm-3

me=10-30 cm2/Vs me=50 cm2/Vs

me=250 cm2/Vs me=70 cm2/Vs

Electric field ~ 0MV/cm
(flatband)

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 Electron Mobility (2/2)

1e15 1e16 1e17 1e18 1e19 1e20

JL

Lg and EOT scaling increased Eeff in the channel decreases

Without strain technology the channel mobility in IM/AM FETs would be = or lower
than in heavily doped Si
Thompson S.E. et al., A 90-nm logic technology featuring strained-silicon, IEEE Transactions on Electron Devices, vol.51, 11
(2004) 1790-1797.
Jacoboni, C. et al., A review of some charge transport properties of silicon, Solid State Electron. 20, issue 2(1977) 77-89.
J.P.-Colinge et al., Reduced electric field in junctionless transistors, Applied Physics Letters 96 (2010) 073510.

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Junctionless nanowire transistors

PROCESS INDUCED-VARIABILITY

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 Process induced-Variability (1/3)

A
C

B
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 Process induced-Variability (2/3)

* Comparing SOI and bulk FinFETs: Performance, height

manufacturing variability, and cost, in ElectroIQ

width
THRESHOLD VOLTAGE (V) for ND=1e19, Tox=2nm
15 -0.7
0.4 0.3 -0.5 -0.6
14 0.2 -0.1 -0.4
0.5
-0.3
13 0
-0.2

A. Kranti. Junctionless nanowire transistor (JNT): 12 0.1 -0.5

Silicon thickness(nm)
0.6 -0.4

Properties and design guidelines. 11

0.4 0.3
0.2
-0.1
-0.2
-0.3

In: Proceedings of ESSDERC 2010, pp.357-360.

10 0
0.5
0.1 -0.1
9
0
8 0.3
0.2 0.1
0.6
0.4
7 0.2
0.5 0.3
6 0.7 0.4

0.6 0.5
5
10 15 20 25 30 35 40
Silicon Width (nm)

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 Process induced-Variability (3/3)

Doping Statistical number of Gate

concentration [cm-3] doping atoms in the channel Source

1e15 0.002 Drain TSi=10nm

1e18 2 Lg=20nm
Gate
Silicon
1e19 20 Oxide WSi=10nm
Nanowire

Junctionless
Lg=10 nm; Tsi=Wsi=3nm
Tox=1nm
Nchannel= 1e20cm-3 (JNT) or
0 (IM)
NSD=1e20cm-3
Inversion mode

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 Conclusion

Naturally CMOS-toolset compatible

Switching properties:
SS=80mV/dec and DIBL=40 mV/V for JNT with Lg=25nm, W=25nm, TSOI=10nm,
Vd=0.9V (experimentally demonstrated by CEA-LETI within FP7-funded project
SQWIRE)

Scalability:
SS for p-channel JNT (Lg=3nm) is 80 mV/dec

Manufacturability:
JNT suppress the difficulty of fabricating ultra-shallow junctions
SOI thickness control is critical

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 Acknowledgements

Colleagues:
Prof. JP Colinge, N. Dehdashti Akhavan, P. Razavi, S. Das, R. Yu (Ultimate
Silicon Devices Group);
N. Petkov, M. Schmidt (Advanced Microscopy Facility Group);
L. Ansari, G. Fagas, J. Greer (Electronics Theory Group)
Prof. G. Ghibaudo (INPG)

Tyndalls Central Fabrication Facility

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 Annex 1

At High Gate Bias:

The saturation current-blocking

region is in the drain,
not in the channel region.

Gate

Source Drain
Depleted

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 Annex 2

Inversion Accumulation Junctionless

Mode Mode Mode
Partial
Inversio
n ulation Deplet
ion
Accum
VFB
VFB
VTH VTH VTH
Log (ID)

Log (ID)

Log (ID)
n

n
letio

letio

letio
Dep

Dep

Dep
VFB

a VGS
b VGS
c VGS

ON: Main Current in ON: Small body ON: Large body

Surface Inversion current & Surface current
Channels Accumulation Channels OFF: Body
OFF: Surface OFF: Body subthreshold current
Subthreshold Current subthreshold current

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