I-MOS: A Novel Semiconductor Device with a Subthreshold Slope lower than kT/q
Kailash Gopalakrishnan, Peter B. Griffin and James D. Plummer
Center for Integrated Systems, Stanford University
Stanford, CA 94305.
Abstract
One of the fundamental problems in the continued scaling
of MOSFETs is the 60 mV/decade room temperature limit in
subthreshold slope. In this paper, we report initial studies on a
new kind of transistor, the I-MOS. The I-MOS uses
modulation of the breakdown voltage of a gated p-i-n
structure in order to switch from the OFF to the ON state and
vice versa. Since impact-ionization is an abrupt function of
the electric field (or the carrier energy), simulations show that
the device has a subthreshold slope much lower than kT/q.
Simulations also show that it is indeed possible to make
complementary circuits with switching speeds comparable to
or exceeding CMOS. Experimental results on a silicon based
prototype verify the basic concept and show very steep
subthreshold slopes with high speed turn-on and turn-off,
Lower bandgap materials are also being investigated to
reduce the value of the breakdown voltage and permit lower
voltage operation.
Introduction
The non-scalability of the subthreshold slope has its origin in
the Fermi-Dirac distribution of carriers and the drift-diffusion
mode of transport in most known devices. This gradual
transition from the OFF to the ON state makes it very
difficult to achieve high ION/IOFFcurrent ratios in scaled
devices. The increasing need for higher performance with
scaling has led to increased leakage c u e n t s in these devices
Drain Leakage Current (Alum)
1.0E-04 I I gate control, one must also envision a fast mechanism like
1.OE-05
1.0E-06
1.0E-07
1.OE-08
.
--
.
e
&e----- -
.
0 0 lourn
1.OE-09 Temperature (C)
1.OE-10
15 35 55 75 95 115
Figure 1: Subthreshold leakage cumns for CMOS for different
technology nodes. The subthreshold leakage c~rrentis increasing
exponentially with decreasing channel lengths. Increasing chip
temperatures are exacerbating the problem (from Birovije
Nikolic, Second Nanotransistor Workshop, NET)
11.3.1
0-7803-7462-2/02/$17.M)02002 IEEE
contributing to increased static power dissipation as is seen in
Fig. 1.
Any attempt to modify the subthreshold slope must
necessarily involve one or more of the following
mechanisms:
(1) Changing the mode of carrier injection from diffusion
based to tunneling based mechanisms (eg. the Schottky
barrier MOSFET). However, to the best of the authors
knowledge, no three terminal tunneling based devices have
ever been demonstrated that have subthreshold slopes better
than kT/q.
(2) The second mechanism to enhance subthreshold slope
stems from a different, albeit interesting, way of looking at
the problem. Enhancing the steepness of a log (Io) vs. VC
curve simply amounts to amplifying the nonlinearity of the
system. As is known from OUI understanding of analog
systems, the nonlinearity of any system can be enhanced by
using an amplifier. Physically this means that one uses an
amplification mechanism to amplify the ON-state and
suppress the OFF-state. Using an amplifier to enhance the
nonlinearity of any system seem like an interesting way of
solving the problem but this approach has the following
major challenges:
(a) The amplification mechanism must be internal to the
device and must arise from some gain mechanism within the
device. Using an external amplifier for every single transistor
is clearly not a practical option.
(b) Most devices that have internal feedback (such as PNF
structures) tend to latch up, so that the gate electrode does not
have any control on the drain current. In addition to having
drift, rather than recombination, that can remove all the
injected carriers when it switches from the ON to the OFF
state.
(c) And finally, the most fundamental challenge arises from
the understanding that there is a fmite bandwidth associated
with every gain mechanism and, depending on the magnitude
of the gain desired, this gain-bandwidth product may impose
fundamental limitations on intrinsic device switching
speed.
We fmd one such gain mechanism that satisfies all of the
above conditions is impact ionization related breakdown.
When a simple p-n junction diode is used in the pre-
breakdown mode (i.e. with voltages less than the breakdown
IEDM 289
voltage), the device exhibits a finite gain-bandwidth product
as is seen in avalanche photodiodes (APD) [I]. However,
when used in the post-breakdown mode (i.e. with voltages
higher than the breakdown voltage), the delay is proportional
to the log of the desired gain and is very fast. This mode has
already been demonstrated in IMPATT and TRAPATT
oscillators that operate at 100's of GHz [2]. Thus gated p-n
diodes pulsed into breakdown can show subthreshold slopes
much lower than kT/q and can potentially he very fast
because carriers can he easily removed by drift. The I-MOS
(impact-ionization MOS) thus uses modulation of the
breakdown voltage of a gated p-i-n structure in order to
switch 6om the OFF state to the ON state and vice-versa.
Device Structure and Physics
The basic device structure for the n-channel version of the 1-
MOS is shown in Fig. 2 in an SO1 implementation. Bulk
structures work in a similar fashion. The device is a gated p-i-
n diode and works by modulating its channel length. At low
gate-voltages, there is no inversion layer under the gate and
the effective channel length is the entire I region. The electric
field under these conditions is below breakdown and
consequently the off-state current is limited by the reverse-
leakage current of the p-i-n diode. As the gate-voltage is
increased, an inversion layer forms under the gate, reducing
the effective channel length of the device, and therefore
increasing the electric fields. The device breaks down. A p-i-
n structure with a lightly doped (or undoped) breakdown
region is chosen so as to reduce the fields required for impact
ionization which prevents band-to-band tunneling (BTBT)
related soft-breakdown. Note that while the formation of the
inversion layer may be limited by the normal 60 mvldecade
limit, the strong dependency of the impact ionization
coefficients on the electric field and the feedback inherent in
the avalanche multiplication process produces a much steeper
subthreshold slope in the I-MOS device.
ox GATE
T ? tL, 4 + ~ ~ ~ ~ ~ +
p' tsi N+
I-REGION
Figure 2: Basic device structure for the nshannel SO1 version of
the I-MOS. The I-MOS uses modulation of the channel length to
switch fmm the OFF IO the ON state via avalanche breakdown.
Subthreshold characteristics are s h o w in fig. 3.
11.3.2
290-lEDM
Simulations
Simulations were done in MEDICITMon a germanium based
device. Germanium was chosen because of its very high
impact ionization coefficients. Impact-ionization coefficients
were calibrated to available experimental data on germanium
devices [3], [4]. Fig. 3 shows a typical 1 0 - v ~simulated curve
for a device with 25 nm gate-length and 25 nm 1 region
(outside the gate), with appropriately chosen gate work-
function. These simulations include models for both impact
ionization and BTBT and were done at 400 K in order to
simulate the worst-case scenario as the leakage is higher,
impact ionization coefficients are lower and BTBT currents
are higher at 400K. The simulated subthreshold slope for this
device was approximately 5 mV/decade. The above device
simulations were done with the standard local field impact-
ionization model which uses local electric fields to determine
the impact ionization coefficients. At dimensions much
smaller than 100 nm, nonlocal dead-space effects have been
shown to play an important role in determining avalanche
multiplication and breakdown voltages. However, even
though the local field model overestimates multiplication at
low biases, it has been shown to accurately predict the
breakdown voltage in a wide variety of materials including Si
[SI, GaAs [6] etc. with dimensions down to 25 nm. This is
because the velocity overshoot effect (and the resulting'
impact ionization overshoot) tends to cancel the nonlocal
dead space effect so that the breakdown voltages are
accurately predicted. This was verified using simulations and
comparison to experimental data in Si and GaAs. However
1.OE-I1 I
11
0 0.2 0.4 0.6
Gate Voltage VG (v)
Figure 3: Simulated lo vs. V O characteristic for a n-channel
germanium I-MOS device shown in Fig. 2 with LI = I*im = 25 nm.
Simulations were done at T400K which is the worst case for leakage
and breakdown. Simulations show that the subthreshold slope is very
small (- Smvl decade), Gain mechanisms inherent in avalanche
multiplication result in very abrupt ON to OFF switching.
Monte-Carlo simulations are currently being used to
determine ultimate scalability.
Device simulations show that these devices switch very fast
(in picoseconds). There is no latch-up because with the gate
switched off, the electric fields (and the multiplication) are
reduced to below the breakdown value and the excess carriers
are removed by drift because of the high electric field in the
p-i-n diode. Thus the turn-off mode of the I-MOS is
fundamentally different from a conventional APD which
exhibits a finite delay in turning off because the electric field
in the i-region is unchanged even when the source of carriers
is switched off.
The avalanche build-up delay is usually small and is of the
same order of magnitude as the transit time of the device [7].
The statistical retardation delay (which is the delay in
generating the seed carrier) is avoided because large seed
currents are generated 6om two primary sources:
(a) Large displacement currents when the voltages across the
device swing in the picoseconds regime [8] and
(b) Tunneling induced impact ionization waves [9].
These modes have been observed in other high speed impact-
ionization based devices including IMPATT and TRAPATT
oscillators.
, bx 1,,,1 I b.
I-REGION
I BURIED OXIDE
NMOS II BURIED OXIDE
PMOS
Figure 4: N-channel and P-channel versions of the I-MOS. It is
easy lo generate complementary devices simply by moving the
position of the gate. An I-MOSinverter shown next consisls of a
n-channel and p-channel I-MOScascaded in series
It is easy to generate complementary devices simply by
moving the position of the gate (Fig. 4). Circuit mode
simulations were done on an I-MOS inverter chain using the
local model in MEDICITM.Each inverter consisted of a n-
channel and a p-channel version of the I-MOS. Simulations
verified that the device has switching speeds matching
CMOS with a F 0 4 delay of less than IO ps (Fig. 5 ) and orders
of magnitude lower static power as compared to CMOS. It
should be noted that the output voltage swing across the I-
MOS device (and the inverter) is not rail-to-rail because a
finite drain to source voltage is needed in order to sustain
breakdown. Thus for the simulations in Fig. 5 , a higher
supply voltage of approximately 1.6V had to be chosen so
that both then I-MOS and p I-MOS devices have around 1 V
across them. The reduced swing at the output of these devices
offsets the increased supply voltage so that the net dynamic
1 5
-<ran*.11 <-
Figurc 5: Transient FO, simulations far the I-MOSinverter-chain.
The simulated circuit (lop)-consists of 4 inverters each sized 4
times more lhan the previous stage. The delay is measured between
nodes 3 and 4. The rising and falling delay both are in picoseconds
and are unequal because the NMOS and PMOS transistors were
not sized optimally.
power is roughly equal to that dissipated by a CMOS inverter
with a 0.85 V supply. The reduced swing results in smaller
delay as well but comes at the expense of reduced noise
margins. These simulation results have not been optimized so
that better performance may be expected.
Experimental Results and Measurements
In order to verify the basic concept, a silicon based prototype
of the device was fabricated. A p-channel version of the
device was fabricated on a 0.2 pm SO1 wafer with g-line
I lithography using IO masks in the Stanford Nanofabrication
Facility (SNF). Most of the fabrication steps were similar to
those of a standard CMOS process.
vs. Vo forthe I-MOS
lo
t -
1.OOE-03 silicon r s b m n * 1-MOS
t.OOE-05 .
50 mv :
1.00E-07 . -10mvl
1.0OE-09
-5 4 -3 -2 -1 0
Yo I" Voln
Figurc 6: Roum-lempr.raturvrxpcrirnmral IOi s VG ;huazImslics
for a silicon based pro1ol)pe of Ihc pchanncl v m i o n uilhe I-hlOS
fabrocatrd m SNP 'Ihc pmamcicn lor lhe drvice are indicalrd tn Ihc
figure As indicalcd abovc. thc rublhrcshold slopr. IS appnximaal)
I U m V I decadc Rewlb arc not uptimiicd
Typical DC experimental results for the device are shomn in
Fig. 6 We note that the device behaves as expected, i.e. has a
subthreshold slope of approximately IO mV decade or lower
11.3.3
IEDM 291
 at a drain bias of approximately 2OV. Different devices in the
layout had drain biases in the range from about IOV to 25V
depending on the length of the 1 region outside the gate but
all of them had very steep subthreshold slopes. The
breakdown voltages obviously scale down in smaller
geometry devices. The prototype device had some problems,
all of which are solvable by modifying the material or the
device structure:
( I ) The drain current for these devices is quite low because of
large parasitic resistances from very long source-drain
extensions and non-silicidation of these regions.
(2) These devices also suffer from significant hot carrier
effects that result in threshold voltage shifts. These hot carrier
effects can be avoided by keeping the breakdown region
away from any interface or by using a buried channel device.
(3) And finally, high drain voltages are required for two
reasons. Silicon has a higher bandgap and a large ratio of the
ionization coefficients (aN/ ap > IO) which leads to high
breakdown voltages. The surface impact ionization
coefficients are much lower than the hulk ionization
coefficients because of a reduction in the mean free path due
t o interface scattering [IO]. The best design for the I-MOS
device would thus need to have a low bandgap material and
the breakdown region kept away from any interface so as to
reduce the breakdown voltages.
Input
--
Figure 'I: Transient characteristicsa f a reverse-bias p-i-n diode
pulsed inlo and out of breakdown The DC breakdown voltage
for these devices is around 1OV. The rise and the fall delays are
less than 10 ns and are limited by the bandwidth of the setup.
These resulu show that the I-MOS is a high speed device.
High speed measurements [ 1 I] were done on simple p-i-n
diodes to verify that these devices indeed switch fast. High
speed measurements were not done on I-MOS devices
because the low drain currents resulted in a low bandwidth
for measurements. The fact that these measurements needed
to be done off-chip without any buffering resulted in the
introduction of a parasitic capacitance of approximately 20
pF at each node which reduces the maximum frequencies that
the circuit can operate at. The DC breakdown voltages of
these devices were close to IOV and the devices were
switched at high frequencies from voltages below breakdown
to voltages above breakdown. The test circuit and
experimental results are shown in Fig. I. Delays of IO ns or
less have been observed and are primarily limited by parasitic
11.3.4
292-IEDM
RC time constants. This however does not establish the
ultimate switching speed of these devices which is estimated
to be of the same order as the transit time (less than 50 ps) in
these large geometry devices.
Conclusions
In conclusion, the I-MOS is a high speed semiconductor
device that has a subthreshold slope much lower than kT/q as
verified by both simulations and experimental results. The
switching delays and dynamic power in these devices are
comparable to those of CMOS devices with comparable
dimensions with the added advantage of ultra-low static
power dissipation. The I-MOS thus has the potential to
replace CMOS for low power and high performance digital
applications. The I-MOS also provides an interesting
template to obtain high gain with very low delays. This may
have interesting implications for analog applications as well
as in optical clocking applications.
However challenges lie ahead primarily in the reduction of
breakdown voltage that would enable further scaling of the
supply voltages. This may require further research in novel
materials as well as in new structures (eg. heterostructures).
New approaches in circuit design may also be needed to
account for the reduced output swing in these devices.
Acknowledgements
The authors gratefully acknowledge Dr. Krishna Saraswat,
Dr. Robert Dutton, Dr. Mark Lundstrom, Raymond Woo,
Richard Chang, Sameer Jain, Yusuke Jono, Rohit Shenoy and
Pranav Kalavade for useful discussions, directions and help
with measurements. We would also like to thank the SNF
staff for assistance during device fabrication. The funding of
this work by the Stanford Graduate Fellowship Program and
DARPA is gratefully acknowledged.
References
[ I ] R. B. Emmons, 1. App. Phys., vol. 38, no. 9, pp. 3705-3714, 1967.
[2] W. T. Read Jr., The Bell System Technical Journal, pp. 401, March 1958.
..
131 Mikawa T.. Kaeawa S.. Kaneda T..
, I . Tovoma
,
Physics Letten,vol. 37.. no. 4, pp. 387-9. Aug. 1980.
Y.. Mikami 0..
I ..
Aoolied
141 S . L. Miller, Phys. Rev. 99, 1234- 1241, 1955.
[SI S . Millidge, D. C. Herbert, M. Kane, G. W. Smith, D. R. Wright,
Semiconduct& Science and Technology, vol. I O , no. 3, pp. 344-7, 1995
[6] S.A. Plimmer, J. P. R. David., T.W. Lee, G. 1. Rees, P.A. Houston, P. N.
Robson, R. Grey, D. C. Herbert, A. W. Higgs, D. R. WrighL 3d IEEE
lnlernational Workshop on High Performance Electron Devices for
Microwave and Optoelecvonic Applications, EDMO 95, pp. 61-9,1995.
[7] Akimov P. V., Grekhov I. V., Senezhkin Yu. N., Fizika i TeWlnika
Polupravodnikov, vol. 6, no. 6, pp. I I I 8 - 20, 1972.
(81 Grekhov 1. V., A. F. Kudo-Syaoev, M. E. kvinshtein, Shenderei S . V.,
So". Phys. Semicond.. vol. 16. no. II.pp. 1977-82,Nov.1982.
[Y] Rodin P., Ebert U,,Hundsdorfer W., Grekhov I.,Journal of Applied
Physics, vol. 92, no. 2, pp. 958 - 64, July 2002.
[ I O ] J. W. Slotboom, G. Streutker, G. J. T.Davis and P.B. Hartag, IEEE
IEDMTechnical Digest. pp. 494-497, 1987.
[IllNemati F., Plummer J. D., IEEE IEDM Technical Digest, pp. 283-6,
1999.