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AGING AWARE RELIABLE MULTIPLIER DESIGN WITH ADAPTIVE HOLD LOGIC 2014

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Digital multipliers are among the most critical arithmetic functional units. The
overallperformanceofthesesystemsdependsonthethroughputofthemultiplier.
Meanwhile,thenegativebiastemperatureinstabilityeffectoccurswhenapMOS Subject

transistorisundernegativebias(Vgs=Vdd),increasingthethresholdvoltageof Re: Aging Aware Reliable Multiplier Design With Adaptive Hold Logic 2014
the pMOS transistor, and reducing multiplier speed. A similar phenomenon,
positive bias temperature instability, occurs when an nMOS transistor is under Message

positive bias. Both effects degrade transistor speed, and in the long term, the
system may fail due to timing violations. Therefore, it is important to design reliable highperformance multipliers. In this paper, we
propose an agingaware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher
throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging
effect.Moreover,theproposedarchitecturecanbeappliedtoacolumnorrowbypassingmultiplier.Theexperimentalresultsshowthat
ourproposedarchitecturewith1616and3232columnbypassingmultiplierscanattainupto62.88%and76.28%performance
improvement, respectively, compared with 1616 and 3232 fixedlatency columnbypassing multipliers. Furthermore, our proposed
architecturewith1616and3232rowbypassingmultiplierscanachieveupto80.17%and69.40%performanceimprovementas
comparedwith1616and3232fixedlatencyrowbypassingmultipliers.

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