2010 International Electron Devices Meeting (IEDM)
Prospect of Tunneling Green Transistor for 0.1V CMOS
Chenming Hu1*, Pratik Patel1, Anupama Bowonder1, Kanghoon Jeon1,2, Sung Hwan Kim1, Wei Yip Loh2, Chang Yong Kang2,
Jungwoo Oh2, Prashant Majhi2, Ali Javey1, Tsu-Jae King Liu1, Raj Jammy2
1
Dept. of Electrical Eng. and Computer Science, University of California, Berkeley, USA; 2International SEMATECH, Austin, TX 78741, USA
*
Tel: 1-510-642-3393, Fax: 1-510-642-2739, E-mail: hu@eecs.berkeley.edu
Abstract
Well designed tunneling green transistor may enable future
VLSIs operating at 0.1V. Sub-60mV/decade characteristics have
been clearly demonstrated on 8 wafers with statistical data. Large
ION at low VDD are possible according to TCAD simulations but
awaits verification. VDD scaling will greatly benefit from low
(effective) band gap energy materials, which may be provided by
type II heterojunctions of Si/Ge or compound semiconductors.
A Looming Barrier to IC Scaling
Reducing the voltage VDD is a powerful way to reduce IC energy
consumption, which is proportional to VDD2 . Power was kept under
control because Vdd has been reduced in proportion to half-pitch up
to 130nm as shown in Fig 1 [1]. The 14nm node is projected to
operate at 0.7V, making the power consumption 25x larger than it
would be if operated at 0.14V as the past trend suggests. While IC
power consumption has been much discussed as a thermal
management challenge, it also accounts for a few percent of the
electricity demand and rising fast.
MOSFET current can not rise faster than one decade for every
60mV increase in Vg (the subthreshold swing). If one is to reduce
the VDD to 0.14V with ION/IOFF ratio of mere 3 decades, SS needs to
be 45mV/decade.
Green Transistor with Steep Turn On/Off
In MOSFETs (and BJTs), a potential barrier is raised and
lowered by Vg to turn the current on and off (Fig. 2). Because of
Boltzmann distribution, some electrons always have sufficient
energy to pass over the barrier. The current can only be reduced by
the rate of electron density drop with increasing energy, hence the
60 mV/decade limit. To beat this limit, the carriers must not flow
over a barrier. They may tunnel through it.
Fig. 3 shows a prototype tunnel transistor [1-4]. Electrons are
generated by band-to-band tunneling in the P+ source when the gate
voltage bends the energy band to satisfy two conditions for
tunnelingoverlap of the valence and conduction bands and the
presence of a high electric field or thin tunnel barrier[5]. The
generated electrons flow through the surface N-channel to the drain.
Fig. 4 shows simulated Id-Vg [6] assuming uniform source doping.
In the 1E-20 cm-3 case, very steep turn on occurs at the sudden onset
of band overlap. Unfortunately the graded source diffusion (and the
charge averaging effect of the Poisson equation) provide a
continuous range of (effective) doping concentration near the tip of
the source. At points of lower doping (Fig. 4) the turn-on voltages
and electrical field (therefore ION) are both lower. The envelope of
these curves is the IV of a prototype tunnel transistor, with a
disappointing sub-Vt swing.
Fig. 5 shows a design that lowers the turn-on voltage of and thus
enhances tunneling in the heavily doped part of the source [1]. The
pocket doping has similar effect as the threshold implant in
MOSFETs. Fig 6 shows the evolution of the IV of Si gFETs of this
type as the pocket doping is increased [6]. Fig. 7 illustrates the
concept of steep turn on at the sudden onset of the overlap of the
conduction and valence bands.
Another approach is to use a very steep source doping profile to
minimize the size of the low doping part of the source (but not the
charge averaging effect). Fig. 8 shows that sub-60mV/decade
average SS is achieved over six orders of magnitude of current with
a device similar to Fig. 3 but fabricated on Si SOI substrate with a
Ge source [7]. After gate and drain formation, the source region was
etched and refilled with insitu doped poly-Ge at low temperature.
Fig. 9 shows yet another gFET design that produces steep turn
on/off. The graded source region is minimized with dopant
segregation from NiSi and a thin semiconductor pocket is created
between the gate dielectric and underlying NiSi [8]. The vertical
electric field is enhanced in the thin pocket and further reduces the
source edge effect. The measured 46 mV/decade SS could only be
reproduced by simulation when a semiconductor pocket is present
as shown is Fig. 9. Fig 10 shows the X-SEM images of the device
with a wedge-shaped pocket between the silicide and the gate
dielectric. This geometry is produced by recessing the source before
the salicide steps. A control device without the pocket was also
fabricated for comparison. Fig. 11 shows the measured ID-VG
characteristics of the gFET vs. the control device. The SS of the
gFET averages 46mV/dec over a decade of drain current. Another
lot successfully reproduced the result two months later with
47mV/dec SS. As seen in Fig. 12, the gFET shows sub-60mV/dec
SS over 3 decades of drain current. Special care must be taken to
screen out low SS data due to various causes (Fig. 14). Statistical
distributions of the minimum SS show that more than 30% of the
gFETs on an 8 wafer have sub-60mV/dec SS (Fig. 15). The
measured ID-VD characteristics of the gFET (Fig. 16) are similar to
MOSFETs and typical for a tunnel transistor.
Prospects of Large ION at 0.1V VDD
Simulations show that VDD can be scaled by reducing Eg (Fig.
17). Only Eg was reduced in simulation, not the other tunneling
parameters [1]. At Eg=0.36eV ION exceeds 1mA/m at VDD=0.2V
with CV/I=0.4pS and can operate well at 0.1V (Fig. 18). A type II
hetero-junction gFET [9] provides an effective tunneling band gap
(Egeff) lower than the Eg of both materials (Fig. 19, 20). Materials A
and B can be simply strained Si thin film on Ge with theoretical
Egeff of around 0.18eV (Fig. 21). A and B can be compound
semiconductors such as InAs on AlGaSb with Egeff as small as zero
by adjusting the Ga/Sb ratio (Fig. 22). The low density of states and
strong quantization in require special attention in gFETs.
Conclusion
Carefully designed tunneling green transistors can potentially
enable 0.1V microelectronics. Sub-60mV/dec subthreshold swing
has been clearly demonstrated on 8 wafers and statistical data.
High current and low voltage operation needs small tunneling band
gap energy which may be provided by type II heterojuctions of
compound semiconductors or Si/Ge. gFET in Fig. 5 is insensitive to
gate length variations (Fig. 23) because the tunnel path is enclosed
in the source and shielded from the influence of the drain.
Acknowledgement
Work partially supported by DARPA under a SPAWAR contract,
#N66001-08-C-2022, FCRP/MSD, and NSF STC/E3S.
References
[1] C. Hu et al, 2008 International Symp. on VLSI Tech., Systems
and Applications, VLSI-TSA, p. 14, April, 2008.
[2]W. Choi et al., IEEE-EDL vol.28, no.8, p.743, 2007
[3]F. Mayer et al., IEDM Tech Dig., p.163, 2008
[4]T. Krishnamohan et al., IEDM Tech Dig., p.947, 2008
[5] T.Y. Chan et al., IEDM, p. 718, 1987.
[6] P. Patel et al, SISPAD 2009. pp. 1-4, Sept. 2009.
[7] S. H. Kim et al., VLSI Tech. Dig., pp.178-179, June 2009
[8] K. Jeon et al., VLSI Tech. Dig., pp. 65-66, June 2009
[9]A. Bowonder et al., Internl Workshop on Junction Tech., p. 93,
2008.
[10]C.G.Van der Walle et al, Phys. Rev. B, vol. 38(8), p.5621, 1986.
[11]M. M. Rieger et al., Phys. Rev. B, vol. 48(19), p.14276, 1993.
[12]L. Yang et al., Semicon. Sci. Tech. v. 19(10), p.1174, 2004.
2010 International Electron Devices Meeting (IEDM)
VG
Node C OX
(nm) 250 180 130 90 65 32 14 Gate
Ec

Vdd E
P+ Source N+ Drain
v
(V) 2.5 1.8 1.3 1.2 1.1 0.9 0.7
i-Si
Source Channel Drain

Fig. 1. IC VDD scaling history and ITRS Fig. 2. Boltzmann statistics lead to the Fig. 3. In a prototype N-type tunnel
projection. Slowdown since 90nm leads to 60mV/decade limit because current is transistor, electrons are generated by
accelerated rise in energy consumption. controlled with an energy barrier height. tunneling in the red-circle region.
-0 1E-03
10 1 0
Uniform Doping Dependence on BTBT Current for Si (EOT
Lpocket: 40 nm
1E-04
6.4 nm HfO2

Drain Current, IDS (A/m)

= 7A) Gate 1E-05
1
0
-

1E20 cm-3
N Pocket

Drain Current (A/um)

-4 1E-06
10 -3
51019 cm-3
5E19 cm10-3
-12
1
0
-
2

-3
P+ Source N+ Drain 1E-07 9E19 cm-3
71019 cm-3
A/um
1 -4
0 1E-08 7E19 cm-3
1E19 cm-3-3 91019 cm-3
12 -8 1E-09 Vov,2 5E19 cm-3
10 1
0
-
6 No Pocket
No Pocket
1E-10
i-Si
5E18 cm-3-301 -1
8 1E18 cm-3 1E-11
-3
VDS = 1.0 V
-12 1E-12
10 1
0
-1
0
0 1 2 .
3 0.0 0.2 0.4 0.6 0.8
44
VGS
0 2 GateGate
Voltage,
Voltage V
(V)GS (V)

Fig. 4. IDS is very sensitive to source doping Fig. 5. One design of a low SS swing gFET. Fig. 6. Increasing N pocket doping makes
level. Outer envelope of the curves leads to a The P pocket lowers the turn-on voltage of the turn-on voltage of the 5E19cm-3 curve
poor sub-Vt swing of a tunneling transistor.. the heavily doped source region. in Fig.4 lower than at edge of the source.
-4
Gate Dielectric
10 Gate
1.E-04 -5
10
-6 NiSi Si
1.E-06 10
ID [A/m]

-7
EC 10 BOX
ID [A/m]

N+
Series1 1.E-08 -8 < Pocket >
Series2 60mV/dec
10
EV -9 Gate
Series3 1.E-10 10
Experiment
Axis Title

ON -10
Series4 10 NiSi Si
OFF 1.E-12 Optimal -11
Series5
Design 10 BOX
-12 N+
Series6
10 Measured
1.E-14 < No Pocket >
Series7 -13 Sim. w/ pocket
P+ Source 10
Series8 -0.1 0.1 0.3 0.5 -14
Sim. no pocket
Gate 10
N pocket VGS-VT [V] -1.5 -1.0 -0.5 0.0
VG [V]
Fig. 7. Energy diagram from gate through
Axis Title Fig. 8. Deposited insitu doped Ge source Fig. 9. Another design achieves
pocket to source. Device is off when there is gFET produced sub-60mV/dec. average SS <60mV/decade swing with a semiconductor
no overlap of valence and conduction bands. over 6 orders of current [7 ]. pocket between oxide and metal (NiSi).
260
Subthreshold Swing [mV/dec]

gFET
-5
10 220 Control
-6
(a) Gate (b) Gate 10 180
-7
10
NiSi Si NiSi N+ Si 10
-8
46mV/dec 140
ID [A/m]

-9
10 100
BOX N+ BOX -10
10
NiSi NiSi -11 60
10
-12
10 gFET 20
-13 -13 -12 -11 -10 -9 -8 -7
BOX 10 Control 10 10 10 10 10 10 10
-14 ID [A/m]
100nm 10
(c) (d) -1.5 -1.0 -0.5 0.0
VG [V]

Fig. 10. Structure and cross-section SEM at Fig. 11. ID-VG of measured and simulated Fig. 12. SS < 60mV/dec over almost 3
source side of dopant segregated gFET (a), gFET showing SS of 46mV/dec. decades of ID for the gFET, but not seen in
(c) and control device (b), (d). (LG=20m, VDS=-1.0V) the control tunnel transistor.
2010 International Electron Devices Meeting (IEDM)
-5
10 0.9 With Screen
-6
10 0.8 W/O Screen
Ref. Ref. Ref. This
[2] [3] [4] Work 10
-7 0.7

Probability
-8 32 mV/dec 0.6

ID [A/um]
SS 10 0.5
52.8 42 ~300 46 3E-11
(mV/dec) 10
-9
0.4
2E-11
ION 10
-10 0.3
12.1 0.01 1E-4 1.2 1E-11
(A/m) -11 0E-11
0.2
10 0.1
-1E-11
ION/IOFF 1E4 1E4 1E2 7E7 -12 1.2 1.3 1.4
10 0.0
1.2 1.4 1.6 1.8 2.0 0 20 40 60 80 100
VG [V] Subthreshold Swing [mV/dec]
Fig. 13. Comparison with other reported Fig. 14. Phantom low SS can show up Fig. 15. SS distribution comparison of
silicon tunnel transistors [8]. VDS= without proper screening. gFET and control device.
VGS-VBTBT= 1.0V.
4.5 1E-02
200
4.0 VG=-2.0V 1E-03
(A/m)

VDD: 0.2 V
3.5 1E-04 VDD: 0.15 V
150
3.0 1E-05 VDD: 0.1 V
ID [A/m]

Current

Germanium
(A/um)

2.5 1E-06 InAs (Vds = 0.2 V)

100
VG=-1.5V 1E-07 Silicon Germanium (Vds = 0.5 V)
2.0
IDS, DrainIds

EG = 0.36 eV Silicon (Vds = 1.0 V)

1.5 1E-08
50
1E-09
1.0
VG=-1.0V 1E-10
0.5 Tox: 0.7 nm 0
1E-11
0.0 0 50 100 150 200
-1.5 -1.0 -0.5 0.0 0.0 0.2 0.4 0.6 0.8 1.0
VD [V]
VGS, GateVgsVoltage
(V) (V)
Fig. 16. ID-VD of gFET showing tunneling Fig. 17. Reducing the band gap energy is a Fig. 18. P/N type gFETs of Fig. 17 with
transistor behavior. new path for scaling the VDD for gFET. CV/I Eg=0.36eV produce excellent inverter
is about or below 1 pS. Only Eg is varied. voltage transfer curves even at 0.1V.

Gate Ref. EC EV Eg,s-Si Eg,eff

P+ N+ ~ ~ [10] 0.55 0.31 0.42 0.19

Source Drain A [11] 0.57 0.25 0.35 0.17

Gate [12] 0.58 0.21 0.37 0.16

Egeff
Fig. 21. Theoretical Egeff of a Ge-strained
B Substrate
Si gFET is around 0.18eV, good for

~ ~ VDD<0.1V operation (see Fig. 17).

1.0E- 04
A B 1.0E- 05
1.0E- 06
Eg = 0.67 eV
1.0E- 07
Fig. 19. A heterojunction gFET. See Fig. 20 Fig. 20. The effective tunneling band Fig. 9. SS distribution comparison of gFETs
1.0E- 08
for explanation. gap in Type II heterojuntion is smaller with HfO2 and ISSG as gate dielectric.
1.0E- 09
than those of A and B. (A/m )

I
DS 1.0E- 10 Lgate: 25nm
Gate
Ids (A/um )
1.0E- 11
Lgate: 20nm
P+ Source N+ Drain 1.0E- 12 Lgate: 15nm
1.0E- 13 Lgate: 10nm
1.0E- 14
nm InAs - 0.5 -0.4 - 0.3 - 0.2 -0.1 0.0
Vgs (V)

AlGaSb Fig. 23 gFET IV is insensitive to Lg

.
variation because the tunneling region is in
Agency under a SPAWAR Systems Center,
San
the Diego contract,
N+ source, #N66001-08-C-2022.
protected from the drain.
Fig. 22. gFET may employ heterojunction
of compound semiconductor with tunable
Egeff.