DIGITAL HARDWARE ARITHMETIC

CS 2600
 The Two's Complement Representation
Range of numbers in twos complement method:
n-1 n-1
2
-2 X 2 - 1

Slightly asymmetric - one more negative number

n-1
-2
2 (represented by 10.0)
10 0) does not have a
positive equivalent

A complement operation for this number will result

in an overflow indication

There is a un
unique
qu representation
p n n f
for 0
 0011 3 0101 5
+ 1011 -5 + 1101 -3
1111 0000 0001
1110 2
-2 1 0010 2
0010
1110
1
-1 0 +1
-2 +2 0011
1101
-4 +3

-3
3 +4
1100 0100

-5
+5
1011
-6 +6 0101
-7 -8 +7
1010
0001 1 0111 0110 0111 7
1001 1000
+ 1111 -1 + 1101 -3
1 0000 0 1 0100
0100 44
 Example (twoscomplement)
010019
01001 9
110017
1000102
Carryoutdiscarded doesnot
indicateoverflow
Ingeneral,ifX andYhave
opposite signs nooverflow
oppositesigns no overflow
canoccurregardlessof
whetherthereisacarryoutor
h th th i t
not
If X and Y have the same sign and result has
different sign - overflow occurs

Examples - (two
(twoss complement)
10111 -9
10111 -9
1 01110 14 = -18 mod 32
Carry-out and overflow

01001 9
00111 7

0 10000 -16 = 16 mod 32

No carry-out but overflow
 0101 5 No carry-out but overflow
+ 0011 3 -> 8 mod
d 16
1000 -8

1011 -5 Carry-out and overflow

+ 1100 -4
4 -9
9 mod
d 16
1 0111 7

C
Condition for
f overflow
f (f
(for logic implementation):
)

S or C ( MSB( A) MSB( B));

Full adder
si = xi yi ci TD = 1 (or 2);
ci+1 = xi . yi + ci . (xi + yi) TD = 2;

A
Assume 3 i/ XOR gate
3-i/p t for
f Si and
d SOP fform for
f Ci+1

Ripple-Carry
Ripple Carry Adder

c4

O Cn Cn 1; TD/C = 2N;
TD/S = 2N-1;
TD/O = 2N+2
O xn 1 yn 1 S n 1 x n 1 y n 1S n1
 Subtraction

Subtract operation, X-Y, is performed by

adding
g the complement
p of Y to X

In the two's complement

p system
y -
-
X-Y = X + (Y+1)

This still requires only a single adder operation,

since 1 is added through the forced carry input
to the binary adder

Use EX_OR to produce complement (use one I/P bit as flag):

- Show how ??
- draw Ckt.
 May use XOR
si = xi yi ci Instead of MUX

ci+1 = xi . yi + ci . (xi + yi)

YKN..(KN-1) X KN..(KN-1) YN..(2N-1) X N..(2N-1) Y0..(N-1) X 0..(N-1)

CKN N-bit C(K-1)N C2N N-bit CN N-bit C0

RCA RCA RCA

S KN..(KN-1) S N..(2N-1) S 0..(N-1)

CascadeofKNbitRCAsalsopossible butdelayislarge
 LookAheadAdder
Let Pi xi yi , Gi xi yi ;

Pi
Si Pi Ci xi
yi + + Si
ci 1 Gi Pi Ci

Ci 1
Ci Gi +

Gi and Pi are termed:

y Generate and Carry
Carry y Propagate
p g
Examples: 74283 - a 4-bit binary
full adder with fast carry
xi
yi + hsi
+ si
xi 1
yi 1 ci generate : g i xi yi
Carry propagate : pi xi yi
x1 Look ahead
carry : ci 1 g i pi ci
y1 Logic
x0
y0 Two Conditions:
c0 1) Ci+1=1
1 if gi=1
1
2) Ci+1=1 if Ci=1 and pi=1

C1 G0 P0C0
C2 G1 P1G0 P1P0C0
 74283 contd.
hsi xi yi ( xi yi )( xi . yi ) pi g i

ci 1 g i ( pi ) pi ci i.e. when gi=1, pi =1

pi ( g i ci )
c1 p0 ( g 0 c0 )
c2 p1 ( g1 c1 ) p1 ( g1 p0 ( g 0 c0 ))
p1 ( g1 p0 )( g1 g 0 c0 )
c3 p2 ( g 2 c2 )
p2 ( g 2 p1 )( g 2 g1 p0 )( g 2 g1 g 0 p0 )
c4 p3 ( g 3 p2 )( g 3 g 2 p1 )
( g 3 g 2 g1 p0 )( g 3 g 2 g1 g 0 c0 )
 Carry-Look-Ahead - FAST Adders
Gi = xi yi - generated carry ;
Pi = xi + yi - ppropagated
p g carryy
ci+1= xi yi + ci (xi + yi) = Gi + ci Pi

Substituting
ci Gi 1 ci 1Pi 1; ci 1 Gi Gi 1Pi ci 1Pi 1Pi
Further substitutions -

All carries can be calculated in parallel, using:

xn-1,xn-2,...,x0 , yn-1,yn-2,,y0 , and forced carry c0
Method called: Carry Look Ahead or Propagation for Fast Adder design
C2 G1 P1C1
Compare overall delay,
C3 G2 P2C2 G2 P2G1 P2 P1C1 w.r.t.
t previous
i circuits
i it
C4 G3 P3G2 P3 P2G1 P3 P2 P1C1

A4
B4
+ P4
C5 C5
G4
A3 P4
B3 + P4
C4 + S4
G4
A2 P3
B2
+ P4 C3 + S3
G4
A1 P2
B1
+ P4 C2 + S2
G4
P1 + S1
C1 C1
 Example - 4-bit Adder

- Draw Ckt.
Ckt

- How many gates ?

- Delay: For Cis: TD = 3; Si = 3 + 2 = 5.

F RCA:
For RCA TD/RCA = 8;
8
 SN-1 S1 S0
YN-1 X N-1 Y1 X1 Y0 X0

FA C0
PL PL

CN-1 C2 C1
GN-1 PN-1 G1 P1 G0 P0

CN
Carry lookahead logic

Carry lookahead Fast Adder

 Delay of Carry-Look-Ahead Adders
G - delay of a single gate
At each stage g
Delay of G for generating all Pi and Gi
Delayy of 2G for ggeneratingg all ci ((two-level ggate
implementation)
Delay of 2G for generating sum digits si in parallel (two-
level gate implementation)
Total delay of 5G regardless of n - number of bits in each
p
operand
Large n (=32) - large number of gates with large
fan-in
Fan-in - number of gate inputs, n+1 here
Span of look-ahead must be reduced at expense of
speed
 Reducing Span
n stages divided into groups - separate carry-look-
carry look
ahead in each group
Groups interconnected by rippleripple-carry
carry method
Equal-sized groups - modularity - one circuit designed
Commonly - group size 4 selected - n/4 groups
4 is factor of most word sizes
Technology-dependent constraints (number of input/output pins)
ICs
IC adding
ddi ttwo 4 digits
di it sequences with
ith carry-look-ahead
l k h d exist
i t
G needed to generate all Pi and Gi
2G needed to propagate a carry through a group once the
Pi,Gi,c0 are available
(n/4)2G needed to propagate carry through all groups
2G needed to generate sum outputs
Total - (2(n/4)+3)G = ((n/2)+3)G - a reduction of almost
75% compared to 2nG in a ripple-carry
ripple carry adder
 YKN..(KN-1) X KN..(KN-1) YN..(2N-1) X N..(2N-1) Y0..(N-1) X 0..(N-1)

CKN N-bit C(K-1)N C2N N-bit CN N-bit C0

LAC-FA
C LAC-FA LAC-FA

S KN..(KN-1)
KN (KN-1) S N..(2N-1) S 0..(N-1)

CascadeofKNbitLACFAsalsopossible

Comparison of the Delay of different systems

Adder C4 C8 C12 C16 S15 C28 C32 S31

RCA 8 16 24 32 31 56 64 63
LAC-FA 3 5 7 9 10 15 17 18
??
 Speed-up for higher level carry bits

Let:

Po*
P3 P2 P1P0 ; *
Go G 3 P3G 2 P3 P2G1 P3 P2 P1G0 ;
Then, C 4 *
Go *
Po C0
If:
P1*
P7 P6 P5 P4 ; *
G1 G 7 P7G 6 P7 P6G5 P7 P6 P5G4 ;
Then, C8 *
G1 *
P1 C4 *
G1 * *
P1 G0 * *
P1 P0 C0
Similarly , C12 *
G2 *
P2 C8 ; C16 *
G3 *
P3 C12
 16-bit 2-level Carry-look-ahead Adder

n=16 - 4 groups
Outputs: Go* , G1* , G2* , G3* , P0* , P1* , P2* , P3* ;
Inputs to a carry-look-ahead
carry look ahead generator with
outputs c4,c8,c12
C 4 Go
*
*
Po C0 ; C8 *
G1 *
P1 C4 *
G1 * *
P1 G0 * *
P1 P0 C4
Similarly , C12 *
G2 *
P2 C8
*
G2 * *
P2 G1 * * *
P2 P1 G0 * * *
P2 P1 P0 C0
C16 *
G3 *
P3 C12
*
G3 * *
P3 G2 * * *
P3 P2 G1 * * * *
P3 P2 P1 Go * * * *
P3 P2 P1 P0 C0
Expression/Output Implementation Total Delay
(4-stage block) Delay C12 C15 :
Gi ; Pi 1 1 5 2 7;
Gi* ; Pi* 2; 1 3; 2

Ci = 4, 8, 12, 16 2 5 S15 :
Si 2 + 1 = 3 8
7 1 8
For LAC-L1, delays are: C16 -> 9, S15 -> 10
 YKN..(KN-1) X KN..(KN-1) YN..(2N-1) X N..(2N-1) Y0..(N-1) X 0..(N-1)

CKN N-bit C(K-1)N C2N N-bit CN N-bit C0

LAC-FA LAC-FA LAC-FA

S KN..(KN-1) S N..(2N-1) S 0..(N-1)

CascadeofKN(=16)bitHLG&PCAsalsopossible
K = 2;; K = 4;;

Bit Delay Bit Delay

(K =1)C
(K 1) C16 5 (K =2)C
(K 2) C32 7
(K=2)C28,C32 5+2=7 (K=3)C44,C48 7+2=9

((K=2)C
) 28 >C31 7+2=9 (K=4)C60,C64 9+2=11
(K=2)S31 9+1=10 (K=4)C60 >C63 11+2=13
(K=4)S63 13+1=14
 Comparison of the Delay of different systems
Adder C4 C8 C16 S15 C32 S31 C64 S63
RCA 8 16 32 31 64 63 128 127
LAC-FA 3 5 9 10 17 18 33 34
HLG&P
HLG&P - - 5 8 7 10 11 14
CA
??

C16 *
G3 *
P3 C12 L2 HLG&P CA

*
G3 * *
P3 G2 * * *
P3 P2 G1 * * * *
P3 P2 P1 Go * * * *
P3 P2 P1 P0 C0
**
Go **
P0 C0 ;
where,
**
Go *
G3 * *
P3 G2 * * *
P3 P2 G1 * * * *
P3 P2 P1 Go ;
P0**
* * * *
P3 P2 P1 P0
C 16 G 3* P3* C 12
G 3* P3* G 2* P3* P2* G 1* P3* P2* P1* G o* P3* P2* P1* P0* C 0
Delay for C16: 5
G o* * P0* * C 0 ;
Delay for S63: 12
where , Delay for C64: 7

G o* * G 3* P3* G 2* P3* P2* G 1* P3* P2* P1* G o* ;

P0* * P3* P2* P1* P0*
 Comparison of the Delay of different FAST ADDER systems

Adder C4 C8 C16 S15 C32 S31 C64 S63

RCA 8 16 32 31 64 63 128 127
LAC-FA 3 5 9 10 17 18 33 34
HLG&P - - 5 8 7 10 11 14
CA
2nd 5 7 7 12
LEVEL
HLG&P-
CA
Other Advanced Adders:

- Pipelined

- Manchester Adder

- Carry-Skip/Carry Select

- Parallel Prefix

- Carry-save
C adders
dd Wallace
W ll ttree

-
 1101
x1011
MULTIPLIER UNIT ---------------------
1101
1101
0000
1101
_____________
11 00 00 0
111111 111
Three types of high-speed multipliers:
Sequential multiplier - generates partial products
sequentially and adds each newly generated
product to previously accumulated partial product

Parallel multiplier - generates partial products in

parallel, accumulates using a fast multi-operand
adder

Array multiplier - array of identical cells

generating new partial products; accumulating
them simultaneously
 PPi-1,j+1
mj

qi qi

Cout Cin

PPi,j

Typical Cell of an Array Multiplier

For Sequential circuit binary Multiplier:

Need - ADDER and Shift-right Registrar (SR) modules.

The control circuit requires a clock;

Multiplixer to decide:

- Add zero (only SR)

Or
- Add and shift (SR).
(SR)

Result to be held in 2
2-K
K bit SR.
Unsigned Binary Multiplication
Flowchart for Unsigned Binary
p
Multiplication
Execution of Example
p
Booths Algorithm for unsigned
p
multiplication

Two basic principles:

- Strings of 0s require no addition only shift

- String
St i off 1s
1 may beb given
i special
i l trreatment:
t t t
001110 (+14) --> 010000 - 000010 (16 - 2);

1s from K-bit posn. to M-bit posn:

Treat as: 2K+1 2M ;
In the above example K = 3, M = 1;

Thus
h M(
(Multiplicand)
l i li d) X 14 = M X 24 = M X 21 ;
y
Obtain result by:
M << 4 - M << 1 // view as C-code.
Take a example: multiplier = 30; Multiplicand = 45

(30) -->
> 32 2 => Change Multiplier to:

0011110 0100000 (32) 0 (+1) 0 0 0 0 0

0 0 0 0 0 (-1) 0
1111110 (-2) ( 2)
-------------------------
0 1 0 1 1 0 1
0 +1 0 0 0 -1 0
- - - - - - - - -
0 0 0 0 0 0 0
1 1 1 1 1 1 0 1 0 0 1 1
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 1 0 1 1 0 1
0 0 0 0 0 0 0
- - - - - - - - - - - - - -
0 0 1 0 1 0 1 0 0 0 1 1 0
 Good multiplier for coding:

0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 ..

Worst case multiplier:

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

Mult 0 0 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 0

Coded
0 +1 -1 +1 0 -1 0 +1 0 0 -1 +1 -1 +1 0 -1 0 0
Mult.
Three rules for Booths algm. implementation with
operation on the multiplicand:

- For the LSB = 1 in a string of 1s in a multiplier:

Subtract the multiplicand from the partial product;

- For the first bit-0 (prior to a 1) in a string of 0s, the

multiplicand is added to the partial product.

- For any pair of identical bit-pair in the mutliplier, the partial

product is unchanged. 0 0 1 1 1 1 0
0 +1 0 0 0 -1
1 0
Multiplier Bits
Bit i Bit (i-1)
(i 1) O
Opn. / Bit Pattern
P tt
0 0 0xM Shift only; String of Zeros
0 1 +1 x M Add andd Shift;
Shift End
E d off a
String of Ones
1 0 -1
1xM Subtract and Shift; Beginning
of a String of Ones
1 1 0xM Shift only; String of Ones
Booths Algorithm
Example
p of Booths Algorithm
g
Execution of Example
p Booth Multiplier
p
+13 01101
-6
6 11010 0 -1
1 +1 -1
1 0

0 1 1 0 1
0 -1 +1 -1 0
- - - - - - - - -
0 0 0 0 0 0 0
1 1 1 1 1 1 0 0 1 1
0 0 0 1 1 0 1
1 1 1 1 0 0 1 1
0 0 0 0 0 0 0
- - - - - - - - - - - -
1 1 1 1 1 0 1 1 0 0 1 0
Fast Multiplication done by:

- Bit-pair recoding

- Carry-save Addition of Summands

- + F
Fastt L
Look
k ahead
h d Carry
C (with
( ith both
b th above)
b )

- Pipelined and Booth Array Tree

- etc.
 BIT-PAIR RECODING OF MULTIPLIERS
Observe this:
-6 11010 0 -1 +1 -1 0

Consider the pair of (+1, -1):

==> (+1, -1)*M = 2xM M = M

==> (0, +1) *M;

Thus: (+1, -1) == (0, +1);

which is also independent of the bit position i.

Booth Pair Equiv. to Recoded pair

(
(+1, 0) (0 +2)
(0, 2)
(-1, +1) (0, -1)
(0 0)
(0, (0 0)
(0,
( 0, 1) (0, 1)
(+1, 1) --
(-1, 0) (0, -2)
 BIT-PAIR RECODING OF MULTIPLIERS

Booth Pair Equiv. Recoded

Multiplier Bits to pair
Bit i Bit (i-1)
(i 1) (
(+1, 0)
) ( +2)
(0, )
0 0 0xM (-1, +1) (0, -1)
0 1 +1 x M (0 0)
(0, (0 0)
(0,
( 0, 1) (0, 1)
1 0 -1 x M (+1, 1) --

1 1 0xM (+1, -1) (0, +1)

(-1, 0) (0, -2)

-6 1 1 1 0 1 0

0 0 -1 +1 -1 0

0 0 -1 0 -2
Execution of Example
Booths Recoded Multiplier
+13 01101
-6 11010 0 -1 +1 -1 0 0 0 -1 0 -2

+13 01101; +26 011010; -26 100110;

-13 10011;

0 1 1 0 1
0 0 -1 0 -2
- - - - - - - - -
1 1 1 1 1 1 0 0 1 1 0
0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
- - - - - - - - - - - -
1 1 1 1 1 0 1 1 0 0 1 0
 Unsigned Binary Division
03 +13 1101 DIVISOR;
63 243
274 100010010 DIVIDEND
189
54 1 0 1 0 1
1 1 0 1 1 0 0 0 1 0 0 1 0
- 1 1 0 1
_ _ _ _ _
21 1 0 0 0 0
13 274 - 1 1 0 1
26 _ _ _ _ _
1 1 1 0
14 - 1 1 0 1
- 13 _ _ _ _ _
1
01
Unsigned
g Binary
y Division
Divisor M

Subtract
or
Add

Shift Left

Dividend Q
Flowchart for Unsigned Binary Division
 ALGO. for RESTORING DIVISION
Load Divisor in Reg. M;
Load Dividend in Reg. Q;
Set Reg. A = 0;
Repeat n times:

Shift (left) A & Q (one bit posn.)

A = A M;

If sgn(A) == 1 ((-ve
ve A)
o Set Q0 = 0;
o A = A + M;

Else
o Set Q0 = 1; ANS:

End - Quotient is in Reg. Q;

- Rem.
R is
i in
i Reg.
R A.
A
 OPN. REG. A REG. Q
INIT. 0 0 0 0 0 1 0 0 0
Dividend,
Dividend
S. L. 0 0 0 0 1 0 0 0
Q = 1000;
I SUB 1 1 1 1 0
Divisor,
Divisor Rstr 0 0 0 0 1 0 0 0 0
M = 11. S. L. 0 0 0 1 0 0 0 0
II SUB 1 1 1 1 1
Rstr 0 0 0 1 0 0 0 0 0
-M=
11101
S. L. 0 0 1 0 0 0 0 0
III SUB 0 0 0 0 1
Set-Q0 0 0 0 0 1 0 0 0 1

Result, in
decimal ?? S. L. 0 0 0 1 0 0 0 1
IV SUB 1 1 1 1 1
Quotient Rstr 0 0 0 1 0 0
= 02 ;
Final
0 0 0 1 0 0 0 1 0
Rem = 02. Result
REM Q
 How to improve the Algo. ??
Repeat n times:

Shift (left) A & Q (one bit posn.)

If A is +ve,
Opns :
Opns.
A = A M;
If A is -ve,
- S.L. (A); Opns. :
If sgn(A) == 1 ((-ve
ve A)
- Subtract
S bt tMM;
o Set Q0 = 0;
- A+M
o A = A + M;
(2A M) - S.L. (A+M);
- Subtract M;
Else
o Set Q0 = 1;
((2A + 2M)
)M
= 2A + M
End
 How to improve the Algo. ??

If A is +ve, If A is -ve,
ve
Opns. : Opns. :

- S.L. (A); - A+M

- Subtract M; - S.L. (A+M);
- Subtract M;
(2A M)
(2A + 2M) M
= 2A + M
Step 1: Repeat n times:
1. If sgn(A) == 0
- Shift (left) A & Q (1
(1-bit
bit posn.)
posn )
- A = A M;
else
- Shift (left) A & Q (1-bit
(1 bit posn.)
posn )
- A = A + M; RESTORING DIVISION

2
2. If sgn(A)
(A) == 0 Repeat n times:
i
o Set Q0 = 1;
o else Q0 = 0; Shift (left) A & Q (1 bit posn.)
End
A = A M;
Step
p 2: If sgn(A)
g ( ) == 1
A = A + M; If sgn(A) == 1 (-ve A)
o Set Q0 = 0;
o A = A + M;
NON_RESTORING
Else
DIVISION
o Set Q0 = 1;

End
 OPN. REG. A REG. Q
INIT. 0 0 0 0 0 1 0 0 0
Dividend,
Dividend S L
S. L. 0 0 0 0 1 0 0 0
Q = 1000; I SUB 1 1 1 1 0
Set Q0 1 1 1 1 0 0 0 0 0
Divisor,
M = 11. S. L. 1 1 1 0 0 0 0 0
II ADD 1 1 1 1 1
Set Q0 1 1 1 1 1 0 0 0 0
-M= S L.
S. 1 1 1 1 0 0 0 0
11101 III ADD 0 0 0 0 1
Set-Q
Set Q0 0 0 0 0 1 0 0 0 1

S. L. 0 0 0 1 0 0 0 1
IV SUB 1 1 1 1 1
Set-Q0 1 1 1 1 1 0 0 1 0
ADD 0 0 0 1 0 0 0 1 0
Final Result 0 0 0 1 0 0 0 1 0
REM Q
 Floating Point Numbers
IEEE 32
32-bit
bit single precision
E
S M
(excess-127 Rep.)

0/1 8 23

IEEE 64-bit single precision

|E| = 11 |M| = 52

Density of Floating Point Numbers

 SEM Field
Common
C case - signed-magnitude
i d it d ffraction
ti
Floating-point format - sign bit S, e bits of exponent
E m bits of unsigned fraction M
E, (m+e+1=n)

Value of (S,E,M) :
((-1)0 =1 ; (-1)1 =-1)

Maximal value - Mmax = 1-ulp

ulp -Unit in the last position - weight of the least-
significant
f b
bit of
f the
h fractional
f l significand
f d
Usually (not always) ulp = 2-m
 In IEEE 32-bit single precision;

E is a signed
signed exponent,
exponent , E
E is in excess
excess-127
127 Representation

E ' E 127; The end values are reserved for special use:

0 E ' 255
2 1 E ' 254; E E '127;
127 E 128; 126 E 127;
Range,
for Exponent:
p For Mantissa:
126 127 38 23 7
[2 ....2 ] 10 [2 ] 10
In IEEE 64-bit single precision;
E ' E 1023 ; 1 E ' 2046
Range, 1022 E 1023 ;
for Exponent: For Mantissa:
1022 1023 308 53 16
[2 ....2 ] 10 [2 ] 10
Floating-Point
g Formats of Three Machines
Binary Normalized Mantissa (IEEE):

1.<xxxx ..23 bits.xxxx>

0 10001000 .0010110 .
Numerical Value (unnormalized): = +0.0010110. x 29

0 10000101 .0110 .

Numerical Value (Normalized): = +1.0110. x 26

1 00101000 .001010 .

Numerical Value (Normalized): = -1.001010. x 2-87

 Special Values :
Both
E = 0 AND M = 0 ZERO VALUE;
0 and
E = 255 AND M = 0 INFINITY;
are possible
126
E= 0 and M <> 0 denormal numbers;
0.M 2
E= 255 and M <> 0 NaN; 0 0; 1
Exceptions :
Underflow, Overflow, Divide by zero and

q
Inexact Result that requires rounding
g in order to be
represented in one of the normal formats;

Invalid 0/0 and sqrt(

sqrt(-1)
1) are attempted.

Special values are set to the results.

 Algms. For ADD/SUB, MULT/DIV,
in normalized floating point opens.

ADD/SUB MULT. DIV.

Make Add the Es and Subtract the Es

smaller exp = large exp., subtract 127 and add 127
by shifting opn.
Mult. the Div. The Mantissas
Perform ADD/SUB on Mantissas and get and get the sign
mantissas
i (get
( result
l h sign
the i
with sign)

Normalize the result value, if necessary,

i all
in ll th
the th
three cases above.
b
Floating point addition
Floating point addition
FP Addition & Subtraction Flowchart
Circuitry for Addition/Subtraction
Floating Point Multiplication
Floating Point Division