Title:

CMOS has been the backbone of almost all today electronics gadget. However, the limits are
imposed as small and compact device design is vitally needed for beyond 20nm technology.
Discuss the challenges for CMOS device scaling into 20nm and below, the issues arise and
provide device design solutions for those device nanoscaling.

Objectives:
study the challenges for CMOS device scaling into 20nm and below and their
respective solutions
study a new technology to solve the downward scaling difficulties

1.0 Introduction

CMOS scaling has been hard during the recent years. The concept of CMOS scaling has to
be understood first. The concept of scaling is actually based on Moores Law. Moores Law
refers to the continued scaling of horizontal and vertical physical feature sizes of silicon
based complementary metal oxide semiconductor (CMOS) transistors (Haron et al., 2008).
This effort has been the main impetus in producing today's advanced technologies of
electronics devices. The scaling theory that was proposed by Dennard et al. in 1972 is the
starting point of this success outcome (Haron et al., 2008). However, semiconductor
industry only started to practice this theory in CMOS transistors a decade after. Since then,
more and more transistors were able to be integrated into single integrated circuit (IC) chip.

In 1965, Gordon E. Moore predicted that the number of transistors which can be
placed in cutting-edge IC chips is doubling approximately every two years without
correspondingly increasing the cost of the chips. Although the scaling of CMOS transistors
has passed through some 'brick wall" predictions as reported in the journal Progress in
Digital Integrated Electronics, pessimists believe that it will finally reach the boundary at size
of 22 nm as forecasted in the International Technology and Roadmap for Semiconductors
ITRS 2007, approximately at the end of next decade. As a matter of fact, Moores Law is the
observation that the number of transistors in a dense integrated circuit doubles
approximately every two years. It is actually an observation by the founder of Moores Law,
Gordon Moore. It is not a natural or physical law. Dennard scaling, on the other hand, is a
scaling law named after its founder, Robert H. Dennard. It is a process to reduce the size of
transistor and to improve its performance. A reduction of transistor size through scaling
process results in improvement of device density, switching speed and power consumption.
For example in ideal scaling, as the dimension and the operating voltage reduces by a factor
of 0.7, the area density is doubled, switching delay reduced by factor of 0.7 and the
switching energy is halved. Reduction of switching energy is very important especially if the
system has been operated for a long period. Scaling process has significantly helps to
reduce the transistor size and to improve the switching energy and speed.

In short, these two laws states that the number of transistor doubles and the size of
the chip will become smaller as year passed. Figure 1.1 shows the part of length or distance
of the gate that the scientist are trying to decrease. Figure1.2 illustrates the reduction in
CMOS gate length with time. Gate length has been decreasing, or scaling, consistently for
the past 35 years. However, physical and other limitations to continue scaling will impact by
about the year 2020, and Moore's law will come to an end. In 2015, Gordon Moore himself
predicted that the rate of progress of down scaling would actually reach saturation and its
limits in the next decade (Moore G., 2015). As this end-point nears, fundamental changes in
the approach to system innovation are required, and there is an increasing susceptibility to
technological surprise.

Figure 1.1: The distance where the scientists are trying to downscale

Source: Moore G., 2015

Figure 1.2: CMOS gate length with time

Source: Moore G., 2015

2.0 The limitation of the CMOS technology

2.1 Physical Limitation

The basic idea of constant-field scaling of CMOS transistors' physical feature and their
corresponding band diagram are shown in Figure 2.1. (Haron et al., 2008)

Figure 2.1: CMOS constant- field scaling idea

Source: Haron et al., 2008

2.1.1Decreasing devices dimension

The scaling of physical dimension includes the reduction in gate dielectric thickness and
channel length.

2.1.2 Lowering power and threshold voltages

Scaling the power supply voltage enables the reduction in dynamic power dissipation. While
reducing the power supply of a chip might seem straightforward, nevertheless, it leads to
issues such as noises and possibly signals levels compatibility problems in multichip systems
using various supply voltages. Reduction in power supply, which also reduces threshold
voltage, also increases static power during transistor off due to leakage current. An analysis
of the impact of supply voltage scaling on the noise margin of CMOS NAND that the supply
voltage cannot be scaled lower than 0.5V. As threshold voltage is reduced as well, the
transistor cannot be completely turned off. The transistor operates in a weak-inversion
mode, with a sub threshold leakage between source and drain. The reduction of threshold
voltage of about 85 mV will increase the sub threshold leakage current by 10 times. (Haron
et al., 2008)

2.1.3 Increasing channel doping

In order to control short channel effects, it is desirable to increase the channel doping.
However, this effort introduces other effects such as slower carrier mobility and band to
band tunneling. A high channel doping will also result in band to band tunneling leakage.
Furthermore, the formation of shallow channel due to thermal budget of dopant activation
causes higher resistance thus reduces drain current. Greater dopant concentration also
causes gate-induced drain leakage current (GIDL). Therefore, increasing the channel doping
will negatively impact the CMOS performance and functionality.

2.2 Material Limitation

Figure 2.2: Introduction of new materials

Source: Haron et al., 2008

From the Figure 2.2, It shows the changes in three decades starting in 1980. This effort is
done in order to ensure the manufacturability and reliability of devices. As these materials
reach their physical limit, devices cannot keep up with their performance. The Si02 reliability
degrades as it becomes thinner. Although Cu is less sensitive to electromigration than AI,
the material is more susceptible to open defect when used as interconnect wires. Low-k
materials utilized for back end process suffer from the high mechanical and thermal stress
during packaging phase. High-permittivity, k materials has been used in 45 nm technology
to replace silicon Si02 as gate dielectric. The high-k materials could minimize the current
leakage problem when the dielectric is made to become thinner to support physical scaling.
However, the tendency of these materials to change their properties in high temperature is
among the challenges need to be solved apart of adding new manufacturing process.
(Haron et al., 2008)

2.3 Power-thermal Limitation

There are two types of power density dissipate by per unit area of integrated circuit (IC)
chips namely dynamic power density and static power density. Dynamic power density is
dissipated when transistor is switched while static power density dissipation originates from
the leakage source-drain current when transistor is switched off. However, the power
densities for both of them are becoming greater as gate length becomes smaller. It is more
severe to the static power density where at the gate length of 20 nm, it will be equivalent to
the dynamic power density. A high performance microprocessor, which uses 10 KW of
power, can draw heat at 1 KW/cm2. For example, the power density of Intel
microprocessor is growing with the new generations. Before 1990s, the power density was
below 10 W/cm2, but when Pentium family processor was introduced in 1990s, the power
density increases exponentially. (Haron et al., 2008)
2.4 Technological Limitation

Figure 2.4: Evolution of mask pattern

Source: Haron et al., 2008

CMOS transistors are basically patterned on wafer by means of lithography and masks. It
means that the lithography technology is one of the main drives behind the transistor
scaling. Ironically, the lithography processes cannot cope with the shrinking feature of CMOS
transistors' layout. Another problem is the inability of polishing process to maintain the
uniform thickness of wafer and reliable mask. Patterning smaller feature than the
wavelength of light requires a trade-off between complex, costly masks and possible design
constraint. Figure 2.4 shows the evolution of mask from the 180 nm technology to the
current technology. As the technology shifts into below 100 nm, the masks become more
complex and more advanced techniques are required. Moreover, it stills a doubt how the
future masks will be. Patterning of features to 20 nm and below has been demonstrated by
a variety of techniques. (Haron et al., 2008)
2.5 Economical Limitation

Figure 2.5: Wafer foundry cost.

Source: Haron et al., 2008

The rising cost in semiconductor sector is basically contributed by the cost of production,
and testing that escalating exponentially with time as the CMOS size is scaling down. As
predicted by the National Institute of Standards and Technology (NIST), a new wafer
foundry could cost approximately 25 billion dollar today, and will increase by one-fold in
2010 as shown in Figure 2.5. The cost explosion is also primarily contributed by the
equipment cost, clean room facilities, and lithography process complexity. Moreover, design
revisions cause a high in mask cost, and reduction in the number of wafer that can be
produced in single mask set. The mask contribution is becoming the dominant factor in
lithography costs, particularly as minimum feature sizes fall below the exposure wavelength.
These problems lead to the combination of wafer production to the best equipped foundries.
The alliances between companies and participation from universities and government that
inject funding are also the strategy used to reduce the cost. Smaller size circuit is vulnerable
to hard and soft defects. These defective-prone circuits need to be tested thoroughly in
order to guarantee the required quality. However, more sophisticated test method will incur
additional testing steps and time thus increasing test cost (Haron et al., 2008).
There are several problems that appear as the transistor size reaches nanometer scale and
thus become the limiting factor on the device performance. Among the problems is short
channel effect, tunneling effect, ballistic transport, oxide thickness and threshold voltage.
Short-channel effect is a notable effect that introduces several leakage current mechanisms
as shown in Figure 2.6. (Sanudin et al, 2002)

Figure 2.6: Short-channel-transistor leakage current mechanisms: reverse-bias p-n

junction leakage (I1), weak inversion (I2), drain induced barrier lowering (I3), gate-
induced drain leakage ( I4), punch-through ( I5), narrow-width effect ( I6), gate oxide
tunneling ( I7), and hot-carrier injection ( I8).

Source: Sanudin et al, 2002

Reverse-bias p-n junction exists due to minority carriers diffusion near the depletion
region and electron-hole pair generation in depletion region. Weak inversion current
occurs when gate voltage is lower than threshold voltage. Drain induced barrier lowering
(DIBL) current exists when source potential barrier is reduced as a result of the drains
depletion region interacts with the source and could lower the threshold voltage. Gate-
induced drain lowering (GIDL) current occurs along the channel width between gate and
drain. Punch through happens when both drain and source depletion regions touch deep
in the channel. Narrow-width current arises when the channel length is reduced to less
than 0.5m. Gate-oxide tunneling current occurs when the oxide layer is made very thin
and causes gate leakage current tunneling through oxide bands. Hot-carrier injection, on
the other hand, occurs when hot carriers are injected into the oxide. Another effect
occurs as transistor is scaled down is tunneling effect between neighboring transistors.
 Normally, the transistors are separated sufficiently enough so that the operation of one
transistor does not affect another transistor. (A.Keshavarzi, K. Roy and C. F. Hawkins,
2000).

Design and solution of FinFET technology change from Planar CMOS

Since many circuits are too complicated and considered totally all the circuit, a design is
hard to reduce the scale and perform well in power consumption and functionality. In Very-
Large-Scale Integration (VLSI) design, it is limits to use the optimisation of leaf cell circuit
and layout designs with process technology for exploiting the challenges of sub-20nm
CMOS. The planar CMOS has driven almost 3 decades in most of the semiconductor
industry. The semiconductor industry was moved from planar CMOS to FinFET below 20nm
node, dubbed as the most significant move by the industry due to the reduction of over-
leakage and device to device variations (Vaidyanathan, 2014). FinFET is known as Fin Field
Effect Transistor which is non-planar and is designed in three-dimensional. FinFETs are
considered to be one of the promising device to extend the CMOS technology beyond the
scaling limit of conventional CMOS technology. FinFETs are double-gate devices which
surround the channel, thereby providing better gate control over the channel (Hu, 2011).
The FinFET with double gate is shown in Figure 3.1.

Figure 3.1: The FinFET with gate

Source: Kawa, 2016

For the planar CMOS, it does not have a good electrostatic control of channel because the
source-drain channel gate is away. By contrast, FinFET have a better electrostatic control
because the vertical fin is inserted between the source-drain channels which wrapped
around the channel (Kawa, 2016). The electrostatic control of FinFET is shown in figure 3.2.
FinFET is designed to use multiple fins to achieve larger channel widths; the source-drain
pads connect the fin in parallel. As the number of fins is increased, the current through the
device increase (Veshala et al, 2013).

Figure 3.2: FinFET design (adding a fin between the source-drain channel)

Source: Kawa, 2016

By providing a better electrostatic control over the channel, it helps reduce leakage current
levels and overcome some other short-channel effects (Veshala et al, 2014). Reduction in
short channel effects in multi gate transistors extend Moores law from scaling. There have
two techniques to reduce the leakage current that are horizontal stacked gate and vertical
stack gate shown in Figure 3.3 and 3.4 respectively (Mathew, 2016). The proposed stack
gate structure is to increase the bottom gate thickness for controlling the electric field of
lower fin region to reduce leakage current.

Figure 3.3: Vertical stack gate bulk FinFET structure 3D view

Source: Mathew, 2016

Figure 3.3: Horizontal stack gate bulk FinFET structure 3D view

Source: Mathew, 2016

With FinFET devices, the next major technology element that the industry would be forced
to adopt is multiple patterning. Multiple patterning is a class of technologies for
manufacturing integrated circuits. It is developed for overcoming the lithographic limitations.
The multiple patterning can be divided into pitch splitting and spacer. Pitch splitting has
double patterning and triple patterning technique meanwhile spacer has self-aligned double
patterning (SADP) and self-aligned quadruple patterning (SAQP) (Bruggere , et al, 2016).

Double patterning is a technology which refers to the litho-etch-litho-etch (LELE) pitch

splitting process. This technique separates the layouts that cannot be printed with a single
exposure, forming two lower-density masks. LELE, or double patterning, imposes new
layouts, physical verification and debug requirements on the designer.

Triple patterning refers to litho-etch-litho-etch-litho-etch (LELELE) required to define a single

layer. Besides that, there have another one design which requires decomposition of original
layer into three masks. It is challenging to build a software algorithm for automating the
decomposition, or colouring, and checking of a layer using triple patterning. A scanning
electron microscope (SEM) image of Metal1 (M1) layer that is manufactured using three
masks levels shown in below Figure 3.2 (Vaidyanathan, 2014).
Figure 3.4: FinFET Device with multiple patterning

Source: Vaidyanathan,2014

SADP is a form of double pattering. The SADP process uses one lithography step and
additional deposition and etches steps to define a spacer-like feature. For the SADP, the
block locations in core features are patterned in the first mask to reduce or eliminated in
dense patches. SQAP is the two cycle of the SADP. The grid routing method is used to
achieve the smallest number of masks for SAQP. The number of used masks in SAQP is
same as SADP. The remaining patterns do not need cutting or trimming. Both of the process
of SADP and SAQP are shown in Figure 3.5 and 3.6 respectively.

Figure 3.5: Spacer type SADP process

Source: Kodama et al, 2013

Figure 3.6: Spacer type SADP process

Source: Kodama et al, 2013

4.0 potential tech beyond cmos.

CMOS technology is used for constructing integrated circuits, microprocessors,

microcontrollers, sensors, RAM(Random Access Memory) and many more digital circuits. The
electronics world demands more and more faster devices. This can be achieved by scaling
CMOS technology from millimeters to few of nanometers in today's technologies. Scientist
make a very sharp reduction in size of CMOS to 7nm in future CMOS technologies (Datta,
2013).Graphene is preferred to be used for future and today in 3D(three dimensional)
technology. Latest material used for CMOS design is Graphene (Klekachev et al, 2013).
Graphene have very attractive properties: high electron and hole mobility, planar structure,
high thermal conductance, high current carrying capacity and thin body (Sung, 2011). All
properties are sufficient for designing a high performance CMOS. Innovations of new
technologies is very important for downsizing of CMOS integrated circuits (Iwai ,2013). As
scaling down of CMOS size after every decade is difficult and we have to face some
problems while downscaling of CMOS exceeds certain limit.

After bipolar junction transistor MOSFET (Metal-OxideSemiconductor Field Effect

Transistor) comes with very interesting feature like low power consumption, low operating
voltage, and higher speed which make MOSFET useful in electronics design. Two types of
MOS transistor PMOS and NMOS are created and used for designing integrated circuits. Both
types have very high static power consumption. This problem is solved if and only a logic
designed in such a way that it consumes no power in static state. After decades, Frank
Wanlass introduces a new logic designed using two complementary p-type and n-type
MOSFET. Two main advantages of CMOS technology is high noise immunity and very low
static power consumption. The last several decades have seen innovation of new CMOS
technologies with excellent features.

Figure 4.1: The evolution of technology nodes in semiconductor manufacturing process in

log scale.

Source: http://www.spinograph.org/blog/why-nanoelectronics-better-microelectronics

As shown in the figure 4.1, it shows the trend of downsizing of CMOS from past, present
and for future. Early in 1970 CMOS is designed using Planar (2D) technology. But to follow
the Moores law downsizing and new technology are very important. Now Non-Planar (3D)
technology is used to design CMOS integrated circuits. As well material is selected list of
semiconductors. We cannot use all semiconductors, it depends upon the structure of the
material that can we use it or not. Grapheme and III-V/Ge are used at rich level in 3D
technology. But III-V materials will not completely replace the Si-CMOS because of some
feature of Switching from 2D technology to 3D technology increases performance and better
speed with smaller area without scaling. The advantage of using three dimensional
technique is not only to increase the CMOS density on a chip but also have other
advantages, such as mixed circuit technologies, mixed process technologies and
combination of different semiconductor material (Buchner, 2002).
Figure 4.2: Trend in high performance CMOS transistor innovation. Different materials used
( high-k dielectric, Ge, III-V) and the transistor (3D,tunnel FET) being implemented to
improve rate of performance, density and power scaling.

Source: Datta, 2013

Figure 4.3: Significant reduction in gate leakage by replacing SiO2 with high-k dielectric.

Source: Datta, 2013.

Figure 4.4: Same electrically oxide thickness is achieved with 5 times thicker physically
thicker HfO2(Hafnium dioxide) dielectric compared to SiO2(Silicon dioxide).

Source: Datta, 2013.

After CMOS the High Performance CMOS was introduced. High-k CMOS are also a high
performance CMOS. As the CMOS face many challenges, such as higher gate leakage
current, source to drain leakage current, gate stack reliability and channel mobility
degradation due to increasing electric field cause rising dynamic power dissipation from non-
scaled power supply voltage, band to band tunneling leakage at high body doping levels,
device to device variation from random dopants fluctuations effects, and high source drain
access resistance from source drain (Datta, 2013). There are different advanced
technologies used for annealing and surface cleaning. For advanced CMOS technologies the
high-k dielectric material is used instead of using SiO2. Early researchers are researching for
high-k dielectric material. They found out a material hafnium dioxide (HfO2). HfO2 due to
.The advantage of using high-k material is to achieve same electrically oxide thickness with
5 times physically thicker hafnium oxide dielectric compared to silicon dioxide.
Conclusion
There have many limitations of the size of CMOS technology. The size should be decreased
every two years which obeyed Moores Law. Since the FinFET technology is the modification
of the CMOS technology. The FinFET is a technology that is used within ICs. However,
FinFET technology is becoming more widespread as feature sizes within integrated circuits
fall but there would be have a limitation of scaling of FinFET. The research is important for
finding other way to reduce nanoscaling.
Reference

Buchner.R, Haberger.K , Seitz.S, Weber.J, Seegebrecht.P.(2002). Process Technology for

3D-CMOS devices. 72-74.

Datta.S.(2013). Recent Advances in High Performance CMOS Transistors From Planar to Non
Planar. 41-42.

Haron, N. Z., & Hamdioui, S. (2008, December). Why is CMOS scaling coming to an END?.
In 2008 3rd International Design and Test Workshop (pp. 98-103). IEEE.

Hu.C, FinFET 3D Transistor & the Concept Behind It, IEEE Solid State Device Society
Seminar Series, 2011.

Iwai.H .(2013). IEEE, Future of nano CMOS technology Frontier Research Center, Tokyo
Institute of Technology,Yokohama, Japan.

Kawa, J. (2016). FinFET Design, Manufacturability, and Reliability. Retrieved from

https://www.synopsys.com/Company/Publications/DWTB/Pages/dwtb-finfet-jan2013.aspx

Klekachev.A.V, Nourbakhsh.A, Asselberghs.I, Stesmans.A.L, Heyns. M.M, & Gendt.H.D

(2013). Graphene Transistors and photodectors. 63-64.

Kodamaa.C,Ichikawa.H,Nakayama.K,Kotanib.T. (2013). Self-Aligned Double and Quadruple

Patterning-Aware Grid Routing with Hotspots Control. 6.

Mathew, J. (2016). Stack Gate Technique for Minimizing Leakage Current in Multigate
MOSFETs. 2016 International Conference on Circuit, Power and Computing
Technologies [ICCPCT] , (p. 5).

Moore, G. (March 30, 2015). Gordon Moore: The Man Whose Name Means Progress, The
visionary engineer reflects on 50 years of Moores Law. IEEE Spectrum. Interview with
Rachel Courtland. Special Report: 50 Years of Moore's Law.
Sarman K Hadia, R. R. (2011). FinFET Architecture Analysis and Fabrication Mechanism .
International Journal of Computer Science Issues, Vol. 8, Issue 5, 6.

Sanudin. R, Morsin.M, Sulong.M.S. (2002). Structure Design Challenge in Nano-CMOS Device.

4.

Sung. C.Y. (2011). IBM Graphene Nanoelectronics Technologies, 9-12.

Bruggere.T, G. H. (6 4, 2016). A way to image IC designs at 20nm and below. Retrieved

from Multipatterning:
http://semiengineering.com/kc/knowledge_center/Multipatterning/196

Vaidyanathan, K. (2014). Exploiting Challenges of Sub-20 nm CMOS for Affordable

Technology Scaling. Electronics & Communication Engineering, Anna University.

Veshala.M, Jatooth.R, Reddy.K.R. (2013). Reduction of Short-Channel Effects in FinFET.

International Journal of Engineering and Innovative Technology (IJEIT)Volume 2,
Issue 9, 7.