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Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS40303
TPS40304 VSON (10) 3.00 mm 3.00 mm
TPS40305
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
5 FB BOOT 6
4 COMP HDRV 7
VOUT
3 PGOOD SW 8
2 EN/SS LDRV/OC 9
SD 1 VDD BP 10
VIN GND
PAD
UDG-09158
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS40303, TPS40304, TPS40305
SLUS964B NOVEMBER 2009 REVISED MAY 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 12
2 Applications ........................................................... 1 8 Application and Implementation ........................ 13
3 Description ............................................................. 1 8.1 Application Information............................................ 13
4 Revision History..................................................... 2 8.2 Typical Applications ................................................ 13
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 27
6 Specifications......................................................... 4 10 Layout................................................................... 28
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 28
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 29
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 30
6.4 Thermal Information .................................................. 4 11.1 Device Support...................................................... 30
6.5 Dissipation Ratings ................................................... 4 11.2 Documentation Support ........................................ 30
6.6 Electrical Characteristics........................................... 5 11.3 Related Links ........................................................ 30
6.7 Typical Characteristics .............................................. 7 11.4 Community Resources.......................................... 30
7 Detailed Description .............................................. 9 11.5 Trademarks ........................................................... 30
7.1 Overview ................................................................... 9 11.6 Electrostatic Discharge Caution ............................ 31
7.2 Functional Block Diagram ......................................... 9 11.7 Glossary ................................................................ 31
7.3 Feature Description................................................... 9 12 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changed minimum controllable pulse width max value from 100 to 70 ................................................................................. 5
DRC Package
10-Pins VSON
Top View
FB COMP PGOOD EN/SS VDD
5 4 3 2 1
Thermal Pad
6 7 8 9 10
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
Gate drive voltage for the high-side N-channel MOSFET. A 0.1-F capacitor (typical) must be connected
BOOT 6 I between this pin and SW. For low input voltage operation, an external schottky diode from BP to BOOT is
recommended to maximize the gate drive voltage for the high-side.
Output bypass for the internal regulator. Connect a low ESR bypass ceramic capacitor of 1 F or greater from
BP 10 O
this pin to GND.
COMP 4 O Output of the error amplifier and connection node for loop feedback components.
Logic level input which starts or stops the controller via an external user command. Letting this pin float turns
the controller on. Pulling this pin low disables the controller. This is also the soft-start programming pin. A
capacitor connected from this pin to GND programs the soft-start time. The capacitor is charged with an
internal current source of 10 A. The resulting voltage ramp of this pin is also used as a second non-inverting
EN/SS 2 I
input to the error amplifier after a 0.8 V (typical) level shift downwards. Output regulation is controlled by the
internal level shifted voltage ramp until that voltage reaches the internal reference voltage of 600 mV the
voltage ramp of this pin reaches 1.4 V (typical). Optionally, a 267-k resistor from this pin to BP enables the
FSS feature.
Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal
FB 5 I
reference voltage.
PGOOD 3 O Open-drain power good output.
HDRV 7 O Bootstrapped gate drive output for the high-side N-channel MOSFET.
Gate drive output for the low-side synchronous rectifier N-channel MOSFET. A resistor from this pin to GND
LDRV/OC 9 O is also used to determine the voltage level for OCP. An internal current source of 10 A flows through the
resistor during initial calibration and that sets up the voltage trip point used for OCP.
Power input to the controller. Bypass VDD to GND with a low ESR ceramic capacitor of at least 1.0-F close
VDD 1 I
to the device.
Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying high-
SW 8 O
side FET driver.
Ground connection to the controller. This is also the thermal pad used to conduct heat from the device. This
Thermal connection serves a twofold purpose. The first is to provide an electrical ground connection for the device.
GND
Pad The second is to provide a low thermal impedance path from the device die to the PCB. This pad should be
tied externally to a ground plane.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VDD 0.3 22 V
SW 3 27 V
SW (< 100 ns pulse width, 10 J) 5 V
BOOT 0.3 30 V
HDRV 5 30 V
BOOT-SW, HDRV-SW (differential from BOOT or HDRV to SW) 0.3 7 V
COMP, PGOOD, FB, BP, LDRV, EN/SS 0.3 7 V
TJ Operating junction temperature 40 145 C
Tstg Storage temperature 55 150 C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those included under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(1) Ratings based on JEDEC High Thermal Conductivity (High K) Board. For more information on the test method, see TI technical brief
(SZZA017).
314 625
VVDD = 20 V
313 620
VVDD = 3V
fSW Switching Frequency kHz
311 610
310 605
VVDD = 12 V
306 585
TPS40303 TPS40304
305 580
40 25 10 5 20 35 50 65 80 95 110 125 40 25 10 5 20 35 50 65 80 95 110 125
Figure 1. Switching Frequency vs Junction Temperature Figure 2. Switching Frequency vs Junction Temperature
1.4 2.24
1.35 VVDD = 20 V
2.22
fSW Switching Frequency MHz
1.2 2.18
VVDD = 3V
VVDD = 12 V
1.15
2.16
1.1
2.14
1.05
TPS40305 VVDD = 12 V
2.12
1
40 25 10 5 20 35 50 65 80 95 110 125 40 25 10 5 20 35 50 65 80 95 110 125
Figure 3. Switching Frequency vs Junction Temperature Figure 4. Quiescent Current vs Junction Temperature
72 14
70 13
IOCSET OCSET Current Source mA
IDD(SD) Shutdown Current mA
12
68
11
66
10
64
9
62
8
60
7
VVDD = 12 V
58
6
40 25 10 5 20 35 50 65 80 95 110 125 40 25 10 5 20 35 50 65 80 95 110 125
Figure 5. Shutdown Current vs Junction Temperature Figure 6. OCSET Current Source vs Junction Temperature
600.6
720
600.4
700
600.2
680
600
660
599.8
640
599.6
620
599.4
40 25 10 5 20 35 50 65 80 95 110 125 40 25 10 5 20 35 50 65 80 95 110 125
Figure 7. Feedback Reference Voltage vs Junction Figure 8. Enable High-Level Threshold Voltage vs Junction
Temperature Temperature
303.0 600
302.5
550
302.0
500
301.5
450
301.0
400
300.5
350
300.0 40 25 10 5 20 35 50 65 80 95 110 125
40 25 10 5 20 35 50 65 80 95 110 125
Figure 9. Enable Low-Level Threshold Voltage vs Junction Figure 10. High-Side Overcurrent Threshold vs Junction
Temperature Temperature
800 1000
VOV/VUV Power Good Threshold Voltage mV
975
750 Overvoltage
950
VSS Soft-Start Voltage mV
700
925
650
900
600 875
850
550
825
500
800
450 Undervoltage
775
400 750
40 25 10 5 20 35 50 65 80 95 110 125 40 25 10 5 20 35 50 65 80 95 110 125
Figure 11. Power Good Threshold Voltage vs Junction Figure 12. Soft-Start Voltage vs Junction Temperature
Temperature
7 Detailed Description
7.1 Overview
The TPS4030x is a family of cost-optimized synchronous buck controllers providing high-end features to
construct high-performance DCDC converters. Prebias capability eliminates concerns about damaging sensitive
loads during start-up. Programmable overcurrent protection levels and hiccup overcurrent fault recovery
maximize design flexibility and minimize power dissipation in the event of a prolonged output short. The
Frequency Spread Spectrum (FSS) feature reduces peak EMI noise by spreading the initial energy of each
harmonic along a frequency band, thus giving a wider spectrum with lower amplitudes.
+
10mA 0.6 VREF + 12.5%
Soft Start SS
SS FB BP
EN/SS 2 +
SD 0.6 VREF 12.5%
Fault
Clock 6 BOOT
Controller
6-V + OC
HDRV
VDD 1 7
Regulator References 0.6 VREF
SD
BP 10 BP 8 SW
Calibration Spread
COMP 4 Clock Anti-Cross BP
Circuit Spectrum
Conduction
Oscillator PWM
and
Logic 9 LDRV/OC
Prebias
FB 5 Circuit
PWM
+
+
0.6 VREF 10mA
SS Thermal OC
750 kW
Shutdown Threshold
PGOOD 3
Setting
Fault Controller
OC
PAD
UDG-09160
GND
2.0
VEN/SS
Calibration
1.6 Time
1.3 V
1.2
0.8
0.7 V
0.4
VSS_INT
0
t Time ms UDG-09159
The voltage at EN/SS is internally clamped to 1.3 V before and/or during calibration to minimize the discharging
time once calibration. The discharging current is from an internal current source of 140 A and it pulls the voltage
down to 0.4 V. The discharging current then initiates the soft-start by charging up the capacitor using an internal
current source of 10 A. The resulting voltage ramp on this pin is used as a second noninverting input to the
error amplifier after an 800 mV (typical) downward level-shift; therefore, actual soft-start does not occur until the
voltage at this pin reaches 800 mV.
If EN/SS is left floating, the controller starts automatically. EN/SS must be pulled down to less than 270 mV to
ensure that the chip is in shutdown mode.
NOTE
When there is no power to the device, PGOOD is not able to pull close to GND if an
auxiliary supply is used for the power good indication. In this case, a built-in resistor
connected from drain to gate on the PGOOD pulldown device makes the PGOOD pin look
approximately like a diode to GND.
7.4.1.1 UVLO
In UVLO, VDD is less than UVLO_ON, the BP6 regulator is off, and the HDRV and LDRV are held low by
internal passive discharge resistors.
7.4.1.2 Disable
Disable is forced by holding SS/EN below 0.4 V. In disable, the BP6 regulator is off, and both HDRV and LDRV
are held low by passive discharge resistors.
7.4.1.3 Calibration
Each enable of the TPS4030X3/4/5 devices requires a calibration which lasts approximately 2 ms. During
calibration the TPS40303/4/5 devices LDRV and HDRV are held off by their respective pulldown drivers while the
device configures as detailed in Enable Functionality, Start-Up Sequence and Timing.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
The bill of materials for this application is shown in Table 2. The efficiency, line, and load regulation from boards
built using this design are shown in Figure 14. Gerber files and additional application information are available
from the factory.
3.5 A
36mV -
8 35 mF 1200kHz
= = 7mW
3.5 A (8)
Two 0805, 22-F, 6.3-V, X5R ceramic capacitors are selected to provide more than 35 F of minimum
capacitance and less than 7 m of ESR (2.5 m each).
A PG0083.401, 400-nH inductor is selected for its small size, low DCR (3.0 m) and high-current handling
capability (17-A thermal, 27-A saturation).
100 225 95
VIN = 14 V Phase VIN = 8 V
80 IOUT = 10 A 180 90
BW = 82 kHz
Phase Margin 55 85
60 135
80 VIN = 12 V
h Efficiency %
40 90 VIN = 14 V
Gain dB
Phase
75
20 45
70
0 0
65
-20 Gain -45
60
-40 -90
55
-60 -135
0.1 1 10 100 1k 50
f Frequency kHz
0 2 4 6 8 10
I Lrms = I Lavg2 + 1 I
12 RIPPLE
2
= I OUT2 + 1 I
12 RIPPLE
2 = 202 + 112 62 = 20.07 A
(20)
Three 1210, 10-F, 25-V, X5R ceramic capacitors are selected. Higher voltage capacitors are selected to
minimize capacitance loss at the DC bias voltage to ensure the capacitors allow sufficient capacitance at the
working voltage.
95 100 225
VIN = 8 V
90 80 180
Phase
85 60 135
80 VIN = 14 V
h Efficiency %
40 90
Gain dB
Phase
75 VIN = 12 V
20 45
70
0 0
65
20 45
Gain
60
40 90
55
60 135
50 1k 10 k 100 k 1M
0 5 10 15 20
f Frequency Hz
ILOAD Load Current A Figure 20. Gain and Phase vs Frequency
0.6
+ +
100 601
VIN = 3.3 V
90
600
VIN = 3.3 V
80
599
60 VIN = 5 V 598
50 597 VIN = 5 V
VIN = 12 V
40
596
30
595
20
VIN = 12 V
594
10
0 593
0 2 4 6 8 10 0 2 4 6 8 10
Figure 23. Efficiency vs Load Current Figure 24. Line and Load Regulation
80 200
Gain
60 Phase 175
40 150
20 125
Gain (dB)
Phase ()
0 100
-20 75
-40 50
-60 25
-80 0
10 20 50 100 1000 10000 100000 1000000
Frequency (Hz) D001
D008
D002
Figure 25. Total System Bode
10 Layout
Figure 26. Top Copper With Components Figure 27. Top Internal Copper Layout
.. ..
.. ..
Figure 28. Bottom Internal Copper Layout Figure 29. Bottom Copper Layer
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.7 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 26-Oct-2016
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TPS40303DRCR ACTIVE VSON DRC 10 3000 Green (RoHS CU NIPDAU | Level-2-260C-1 YEAR -40 to 125 0303
& no Sb/Br) CU NIPDAUAG
TPS40303DRCT ACTIVE VSON DRC 10 250 Green (RoHS CU NIPDAU | Level-2-260C-1 YEAR -40 to 125 0303
& no Sb/Br) CU NIPDAUAG
TPS40304DRCR ACTIVE VSON DRC 10 3000 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 0304
& no Sb/Br)
TPS40304DRCT ACTIVE VSON DRC 10 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 0304
& no Sb/Br)
TPS40305DRCR ACTIVE VSON DRC 10 3000 Green (RoHS CU NIPDAU | Level-2-260C-1 YEAR -40 to 125 0305
& no Sb/Br) CU NIPDAUAG
TPS40305DRCT ACTIVE VSON DRC 10 250 Green (RoHS CU NIPDAU | Level-2-260C-1 YEAR -40 to 125 0305
& no Sb/Br) CU NIPDAUAG
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 26-Oct-2016
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Aug-2016
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Aug-2016
Pack Materials-Page 2
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