VHDL-MUX:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplexer is
Port (i0, i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
i3 : in STD_LOGIC;
i4 : in STD_LOGIC;
i5 : in STD_LOGIC;
i6 : in STD_LOGIC;
i7 : in STD_LOGIC;
i8 : in STD_LOGIC;
i9 : in STD_LOGIC;
i10 : in STD_LOGIC;
i11 : in STD_LOGIC;
i12 : in STD_LOGIC;
i13 : in STD_LOGIC;
i14 : in STD_LOGIC;
i15 : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC);
end multiplexer;
architecture behavioral of multiplexer is
begin
process(i0,i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15,s)
begin
case s is
when "0000"=> y<=i0;
when "0001"=> y<=i1;
when "0010"=> y<=i2;
when "0011"=> y<=i3;
when "0100"=> y<=i4;
when "0101"=> y<=i5;
when "0110"=> y<=i6;
when "0111"=> y<= i7;
when "1000"=> y<= i8;
when "1001"=> y<= i9;
when "1010"=> y<= i10;
when "1011"=> y<= i11;
when "1100"=> y<= i12;
when "1101"=> y<= i13;
when "1110"=> y<= i14;
when "1111"=> y<= i15;
when others=>null;
end case;
end process;
end Behavioral;

Verilog MUX:

mux(i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, s0, s1, s2, s3, z);
input i0;
input i1;
input i2;
input i3;
input i4;
input i5;
input i6;
input i7;
input i8;
input i9;
input i10; module
input i11;
input i12;
input i13;
input i14;
input i15;
input s0;
input s1;
input s2;
input s3;
output z;
reg op;
always@(i0 or i1 or i2 or i3 or i4 or i5 or i6 or i7 or i8 or i9 or i10 or i11 or i12 or i13 or i14 or
i15 or s0 or s1 or s2 or s3)
begin
case({s0,s1,s2,s3})
4'b0000:op<=i0;
4'b0001:op<=i1;
4'b0010:op<=i2;
4'b0011:op<=i3;
4'b0100:op<=i4;
4'b0101:op<=i5;
4'b0110:op<=i6;
4'b0111:op<=i7;
4'b1000:op<=i8;
4'b1001:op<=i9;
4'b1010:op<=i10;
4'b1011:op<=i11;
4'b1100:op<=i12;
4'b1101:op<=i13;
4'b1110:op<=i14;
4'b1111:op<=i15;
default:op<=op;
endcase
end
assign z=op;
endmodule

VHDL-Decoder:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dec is
Port ( inp : in STD_LOGIC_VECTOR (3 downto 0);
oup : out STD_LOGIC_VECTOR (15 downto 0));
end dec;
architecture Behavioral of dec is
begin
process(inp)
begin
case inp is
when "0000"=> oup<="0000000000000001";
when "0001"=> oup<="0000000000000010";
when "0010"=> oup<="0000000000000100";
when "0011"=> oup<="0000000000001000";
when "0100"=> oup<="0000000000010000";
when "0101"=> oup<="0000000000100000";
when "0110"=> oup<="0000000001000000";
when "0111"=> oup<= "0000000010000000";
when "1000"=> oup <= "0000000100000000";
when "1001"=> oup<= "0000001000000000";
when "1010"=> oup <= "0000010000000000";
when "1011"=> oup <= "0000100000000000";
when "1100"=> oup <= "0001000000000000";
when "1101"=> oup <= "0010000000000000";
when "1110"=> oup <= "0100000000000000";
when "1111"=> oup <= "1000000000000000";
when others=> oup<="----------------";
end case;
end process;
end Behavioral;
 Verilog-Decoder:

module decoder(x, y, z, w, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15);
input x; input y;
input z;
input w;
output d0;
output d1;
output d2;
output d3;
output d4;
output d5;
output d6;
output d7;
output d8;
output d9;
output d10;
output d11;
output d12;
output d13;
output d14;
output d15;
and(d0,xbar,ybar,zbar,wbar),(d1,xbar,ybar,zbar,w),(d2,xbar,ybar,z,wbar),(d3,xbar,ybar,z,w),
(d4,xbar,y,zbar,wbar),(d5,xbar,y,zbar,w),(d6,xbar,y,z,wbar),(d7,xbar,y,z,w),
(d8,x,ybar,zbar,wbar),(d9,x,ybar,zbar,w),(d10,x,ybar,z,wbar),(d11,x,ybar,z,w),
(d12,x,y,zbar,wbar),(d13,x,y,zbar,w),(d14,x,y,z,wbar),(d15,x,y,z,w);
not (xbar,x), (ybar,y), (zbar,z), (wbar,w);
endmodule

VHDL-Comparator:
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparator is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
e : out STD_LOGIC;
g : out STD_LOGIC;
l : out STD_LOGIC);
end comparator;
architecture Behavioral of comparator is
begin
process(a,b)
begin
if(a=b)then
e<='1';
g<='0';
l<='0';
elsif(a<b)then
e<='0';
g<='0';
l<='1';
else
e<='0';
g<='1';
l<='0';
end if;
end process;
end Behavioral;

COMPARATOR IN VERILOG:
module comparator(a3, a2, a1, a0, b3, b2, b1, b0, e, g, l);
input a3;
input a2;
input a1;
input a0;
input b3;
input b2;
input b1;
input b0;
output e;
output g;
output l;
wire e3,e2,e1,e0,g3,g2,g1,g0,l3,l2,l1,l0;
assign e3= a3 ~^ b3;
assign e2= a2 ~^ b2;
assign e1= a1 ~^ b1;
assign e0= a0 ~^ b0;
assign e= e3 & e2 & e1 &e0;
assign g3=a3 & (~b3);
assign g2=e3 & a2 & (~b2);
assign g1=e3 & e2 &a1 & (~b1);
assign g0=e3 & e2 &e1 & a0 & (~b0);
assign g= g3|g2|g1|g0;
assign l3=(~a3) & b3;
assign l2=e3 & (~a2) & b2;
assign l1=e3 & e2 & (~a1) & b1;
assign l0=e3 & e2 & e1 & (~a0) & b0;
assign l=l3|l2|l1|l0;
endmodule
PROGRAM FOR FIR FILTER:
module filter(x,h,h1,h2,h3,h4,y,clk);
input [3:0]x;
input [3:0]h,h1,h2,h3,h4;
input clk;
output [10:0]y;
reg [3:0]q1,q2,q3,q4;
wire [10:0]y0,y1,y2,y3,y4;
initial q1=0;
initial q2=0;
initial q3=0;
initial q4=0;
always@(posedge clk)
begin
q4<=q3;
q3<=q2;
q2<=q1;
q1<=x;
end
assign y0=x*h;
assign y1=q1*h1;
assign y2=q2*h2;
assign y3=q3*h3;
assign y4=q4*h4;
assign y=y0+y1+y2+y3+y4;
endmodule