TABLE OF CONTENTS

EX.NO DATE TITLE OF THE EXPERIMENT PAGE MARKS STAFF

NO. SIGN.
01. Design of NMOS and CMOS Inverters - DC
and transient characteristics and
Switching times
02. Estimation of Resistance, Capacitance and
Inductance
03. Design of Multiplexers, Decoders and
comparators
Analytical Modeling and simulation of I-V
04. characteristics of a p channel/n channel
MOSFET using Newton Rapson method
Analytical Modeling and simulation of potential
05. distribution/field of the MOSFET Using finite
difference method
06. Modeling and analysis of MOS capacitor -
Small signal Analysis
07. Simulation of Schrodinger equation based
device modeling
08. Modeling and Simulation of NMOS and CMOS
circuits using Spice
09. Design of Designing FIR filters using FPGA

3
 EX.NO:1a DESIGN AND ANALYSIS OF NMOS INVERTER

DATE:

AIM:

To design a NMOS Inverter and to simulate the DC, Transient characteristics and
switching time using Orcad Pspice9.2 tools.
SOFTWARE REQUIRED:

Orcad Pspice9.2

ALGORITHM:1a

STEP 1: Create Pspice Project.

STEP 2: Enable blank project. An Orcad Capture Schematic window appears.

STEP3: Select Place-> part and select required components and place in schematic window.
STEP4: Connect the NMOS transistor, resistor, Voltage sources and GND using wires.

STEP5: Place Voltage/level markers at input and output terminals.

STEP 6: Assign constant values for voltage sources and bit values for inputs.

STEP 7: Perform transient, DC and switching analysis and simulate the netlist.

STEP 8: View the output waveform in the waveform window.

3
(1).DC CHARACTERISTICS:

SCHEMATIC:

V 1

5 V d c
5 .0 0 0 V

R 1
2 0 0 K
0 V
5 .0 0 0 V
V 2 M 1 V
0 V d c
2 .4 9 9 m V
M b re a k N
V

0
P-SPICE NETLIST:

*Libraries:
* Local Libraries:
*From [PSPICE NETLIST] section of C:\Program Files\Orcad\PSpice\PSpice.ini file:.lib
"nom.lib"

*Analysis directives:

.DC LIN V_V2 0 10 1

.PROBE V(*) I(*) W(*) D(*) NOISE(*)
.INC ".\nmosinv-SCHEMATIC1.net"

**** INCLUDING nmosinv-SCHEMATIC1.net ****

* source NMOSINV
M_M1 N00180 N00838 0 0 MbreakN
R_R1 N00180 N00523 200K
V_V2 N00838 0 0Vdc
V_V1 N00523 0 5Vdc

**** RESUMING nmosinv-schematic1-sssss.sim.cir ****

3
.END
SIMULATION OUTPUT WAVEFORM:

(2).TRANSIENT CHARACTERISTICS:

SCHEMATIC:

3
 V 1

5 V d c
5 .0 0 0 V

R 1
2 0 0 K
0 V
5 .0 0 0 V
V 2 M 1 V
0 V d c
0 V
V
M b re a k N

P - SPICE NETLIST:

*Libraries:
*Local Libraries :
*From [PSPICE NETLIST] section of C:\Program Files\Orcad\PSpice\PSpice.ini file:.lib
"nom.lib"

*Analysis directives:

.PROBE V(*) I(*) W(*) D(*) NOISE(*)

.INC ".\nmosinv-SCHEMATIC1.net"

**** INCLUDING nmosinv-SCHEMATIC1.net ****

* source NMOSINV
M_M1 N00180 N00838 0 0 MbreakN
R_R1 N00180 N00523 200K
V_V2 N00838 0 0Vdc
V_V1 N00523 0 5Vdc

**** RESUMING nmosinv-schematic1-sssss.sim.cir ****

.END

SIMULATION OUTPUT WAVEFORM:

3
3
(3).SWITCHING CHARACTERISTICS:

SCHEMATIC:

P-SPICE NETLIST:

*Libraries:
* Local Libraries :
* From [PSPICE NETLIST] section of C:\Program Files\Orcad\PSpice\PSpice.ini file:.lib
"nom.lib"

*Analysis directives:

.TRAN 0 10us 0
.PROBE V(*) I(*) W(*) D(*) NOISE(*)
.INC ".\nmosinv-SCHEMATIC1.net"

**** INCLUDING nmosinv-SCHEMATIC1.net ****

* source NMOSINV
M_M1 N00180 N00838 0 0 MbreakN
R_R1 N00180 N00523 200K
V_V1 N00523 0 5Vdc
U_DSTM2 STIM(1,1) $G_DPWR $G_DGND N00838 IO_STM IO_LEVEL=0
+00
+ +.5uS 1
+REPEAT FOREVER
+ +.5uS 0
+ +.5uS 1
+ ENDREPEAT

**** RESUMING nmosinv-schematic1-sssss.sim.cir ****

.END

3
SIMULATION OUTPUT WAVEFORM:

RESULT:

Thus the NMOS inverter was designed using Orcad Pspice9.2 tools and
its Transient,

DC and switching characteristics was simulated.

3
 EX.NO:1b
DESIGN AND ANALYSIS OF CMOS INVERTERS
DATE:

AIM:

To design a CMOS Inverter and to simulate the DC, Transient characteristics and
switching time using Orcad Pspice9.2 tools.
SOFTWARE REQUIRED:

Orcad Pspice9.2

ALGORITHM:

STEP 1: Create Pspice Project.

STEP 2: Enable blank project. An Orcad Capture Schematic window appears.

STEP3: Select Place-> part and select required components and place in schematic window.
STEP4: Connect the NMOS transistor, PMOS transistor, Voltage sources and GND using wires.

STEP5: Place Voltage/level markers at input and output terminals.

STEP 6: Assign constant values for voltage sources and bit values for inputs.

STEP 7: Perform transient, DC and switching analysis and simulate the netlist.

STEP 8: View the output waveform in the waveform window.

1).DC CHARACTERISTICS
3
 SCHEMATIC:

P-SPICE NETLIST:

. Libraries:
* Local Libraries :
* From [PSPICE NETLIST] section of C:\Program Files\Orcad\PSpice\PSpice.ini file:
.lib "nom.lib"

*Analysis directives:
.DC LIN V_V2 0 5 1
.PROBE V(*) I(*) W(*) D(*) NOISE(*)
.INC ".\cmos-SCHEMATIC1.net"
**** INCLUDING cmos-SCHEMATIC1.net ****
* source CMOS
M_M1 N00441 N00543 0 0 MbreakN
M_M2 N00145 N00543 N00441 N00145 MbreakP
V_V1 N00145 0 5Vdc
V_V2 N00543 0 5Vdc

**** RESUMING cmos-schematic1-cmos.sim.cir ****

.END

3
SIMULATION OUTPUT WAVEFORM:

2).TRANSIENT ANALYSIS:
SCHEMATIC:

P-SPICE NETLIST:
3
 *Libraries:
* Local Libraries :
* From [PSPICE NETLIST] section of C:\Program Files\Orcad\PSpice\PSpice.ini file:.lib
"nom.lib"

*Analysis directives:
.PROBE V(*) I(*) W(*) D(*) NOISE(*) .INC ".\cmos-SCHEMATIC1.net"

**** INCLUDING cmos-SCHEMATIC1.net ****

* source CMOS
M_M1 N00441 N00543 0 0 MbreakN
M_M2 N00145 N00543 N00441 N00145 MbreakP
V_V1 N00145 0 5Vdc
V_V2 N00543 0 5Vdc

**** RESUMING cmos-schematic1-cmos.sim.cir ****

.END

SIMULATION OUTPUT WAVEFORM:

3).SWITCHING CHARACTERISTICS:
3
SCHEMATIC:
V 1

5 V d c

M 2
5 .0 0 0 V

VM b r e a k P

0 V

2 .4 9 9 m V 5 .0 0 0 V
D S T M 2
C L K

M 1

M b re a k N

P-SPICE NETLIST:

*Libraries:
* Local Libraries:
* From [PSPICE NETLIST] section of C:\Program Files\Orcad\PSpice\PSpice.ini file:.lib
"nom.lib"

*Analysis directives:
.TRAN 0 10us 0
.PROBE V (*) I (*) W (*) D (*) NOISE (*)
.INC ".\cmos-SCHEMATIC1.net"

**** INCLUDING cmos-SCHEMATIC1.net ****

* source CMOS
M_M1 N00441 N00191 0 0 MbreakN
U_DSTM2 STIM (1, 1) $G_DPWR $G_DGND N00191 IO_STM IO_LEVEL=0
+00
+ +.5uS 1
+REPEAT FOREVER
+ +.5uS 0
+ +.5uS 1
+ ENDREPEAT
M_M2 N00145 N00191 N00441 N00145 MbreakP
V_V1 N00145 0 5Vdc

**** RESUMING cmos-schematic1-cmos.sim.cir ****

.END

3
SIMULATION OUTPUT WAVEFORM:

RESULT:
Thus the CMOS inverter was designed using Orcad Pspice9.2 tools and its Transient,
DC and switching characteristics was simulated.

3
 EX.NO:2 ESTIMATION OF RESISTANCE, INDUCTANCE AND
CAPACITANCE
DATE:

AIM:
To estimate the resistance, inductance and capacitance values by C programming.
SOFTWARE REQUIRED:
Turbo C++
DESIGN EQUATIONS:
Resistor:

R = Rs *

R1 =

Where
R1 load resistance
RS sheet resistance
l -length of resistor
w width of resistor
t -thickness of resistor

3
Capacitor:

Cg

Cd =

Cgb =

Where
-gate capacitance
-drain capacitance
-gate to bulk capacitance
-permittivity of silicon-di-oxide
-permittivity in free space
-permittivity of silicon
d -depth of capacitance
-oxide thickness
A -area

Inductor:
l = r * (n * n) *u0
Where
r -radius.
n -number of turns.
uo-permeability in free space.

3
ALGORITHM:
STEP 1: Open turbo C++ and create new file.
STEP 2: Type the coding for the calculation of resistance, inductance & capacitance.
STEP 3: Save the file with extension as.cpp.
STEP 4: Compile and run the program.

PROGRAM:
Estimation of resistor:
#include<stdio.h>
#include<conio.h>
#include<math.h>
void main()
{
int Rs=15;int P=6;float t=30*pow(10,-3);
float l,w,R,R1;
R=Rs*(l/w);
printf("The resistance value is:%f",R);
R1=(l/t*l/w);
printf("The value of R1 is:%f",R1);
getch();
}

Estimation of inductor :
#include<stdio.h>
#include<conio.h>
Void main()
{
int n=6,r=10;
float l,uo=1.2/1000000;
l=uo*n*n*r;
printf(inductor value:%f,l);
getch();
}

3
Estimation of capacitor:
#include<stdio.h>
#include<conio.h>
#include<math.h>
void main()
{
float Cg,Cd,Cgb,A=10*pow(10,-2);
float tox=1000*pow(10,-8),e0=8.854*pow(10,-4),esio2=3.9;
float esi=12,d=1.7*pow(10,-3);
Cg=(esio2*e0/tox)*A;
printf("The gate capacitance is:%f",Cg);
Cd=(e0*esi/d)*A;
printf("The depletion capacitance is:%f",Cd);
Cgb=(Cg*Cd/Cg+Cd);
printf("The gate bulk capacitance is:%f",Cgb);
getch();
}

OUTPUT:

RESISTANCE:

The resistance value is :12367364261280588700000000000.000000

INDUCTANCE:

Inductance value is .628000

CAPCITANCE:

The gate capacitance is:34.530602

The capacitance is:0.624988
The gate bulk capacitance is:0.613877

RESULT:

The resistance, inductance and capacitance values are estimated by C programming.

3
 EX.NO:3 DESIGN OF MULTIPLEXER, DECODER

DATE: ANDCOMPARATOR
AIM:
To design a multiplexer, decoder and comparator using VHDL and Verilog.
SOFTWARE REQUIRED:
Xilinx ISE 9.1i.
ALGORITHM:
STEP 1: Open Xilinx ISE 9.1i software.
STEP 2: Create a new project using File New project.
STEP 3: Type the program and save the project.
STEP 4: In synthesis/implementation double click synthesize-XST to check syntax.
STEP 5: Choose behavioral simulation.
STEP 6: In create new sourceTest bench waveform and save the test bench waveform.
STEP 7: In Xilinx ISE SimulatorSimulate Behavioral Model.
STEP 8: Verify the output waveform.

PROGRAM FOR MULTIPLEXER IN VHDL:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplexer is
Port (i0, i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
i3 : in STD_LOGIC;
i4 : in STD_LOGIC;
i5 : in STD_LOGIC;
i6 : in STD_LOGIC;
i7 : in STD_LOGIC;
i8 : in STD_LOGIC;
i9 : in STD_LOGIC;
i10 : in STD_LOGIC;
i11 : in STD_LOGIC;
i12 : in STD_LOGIC;
i13 : in STD_LOGIC;
i14 : in STD_LOGIC;
i15 : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC);
end multiplexer;
architecture behavioral of multiplexer is
begin
process(i0,i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15,s)
3
begin
case s is
when "0000"=> y<=i0;
when "0001"=> y<=i1;
when "0010"=> y<=i2;
when "0011"=> y<=i3;
when "0100"=> y<=i4;
when "0101"=> y<=i5;
when "0110"=> y<=i6;
when "0111"=> y<= i7;
when "1000"=> y<= i8;
when "1001"=> y<= i9;
when "1010"=> y<= i10;
when "1011"=> y<= i11;
when "1100"=> y<= i12;
when "1101"=> y<= i13;
when "1110"=> y<= i14;
when "1111"=> y<= i15;
when others=>null;
end case;
end process;
end Behavioral;

SIMULATION WAVEFORM:

3
PROGRAM FOR MULTIPLEXER IN VERILOG:
module mux(i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, s0, s1, s2, s3, z);
input i0;
input i1;
input i2;
input i3;
input i4;
input i5;
input i6;
input i7;
input i8;
input i9;
input i10;
input i11;
input i12;
input i13;
input i14;
input i15;
input s0;
input s1;
input s2;
input s3;
output z;
reg op;
always@(i0 or i1 or i2 or i3 or i4 or i5 or i6 or i7 or i8 or i9 or i10 or i11 or i12 or i13 or i14 or
i15 or s0 or s1 or s2 or s3)
begin
case({s0,s1,s2,s3})
4'b0000:op<=i0;
4'b0001:op<=i1;
4'b0010:op<=i2;
4'b0011:op<=i3;
4'b0100:op<=i4;
4'b0101:op<=i5;
4'b0110:op<=i6;
4'b0111:op<=i7;
4'b1000:op<=i8;
4'b1001:op<=i9;
4'b1010:op<=i10;
4'b1011:op<=i11;
4'b1100:op<=i12;
4'b1101:op<=i13;
4'b1110:op<=i14;
4'b1111:op<=i15;
default:op<=op;
endcase
3
end
assign z=op;
endmodule

SIMULATION WAVEFORM:

PROGRAM FOR DECODER IN VHDL:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dec is
Port ( inp : in STD_LOGIC_VECTOR (3 downto 0);
oup : out STD_LOGIC_VECTOR (15 downto 0));
end dec;
architecture Behavioral of dec is
begin
process(inp)
begin
case inp is
when "0000"=> oup<="0000000000000001";
when "0001"=> oup<="0000000000000010";
when "0010"=> oup<="0000000000000100";
when "0011"=> oup<="0000000000001000";
when "0100"=> oup<="0000000000010000";
when "0101"=> oup<="0000000000100000";
when "0110"=> oup<="0000000001000000";
when "0111"=> oup<= "0000000010000000";
when "1000"=> oup <= "0000000100000000";
when "1001"=> oup<= "0000001000000000";
when "1010"=> oup <= "0000010000000000";
when "1011"=> oup <= "0000100000000000";
when "1100"=> oup <= "0001000000000000";
when "1101"=> oup <= "0010000000000000";
3
when "1110"=> oup <= "0100000000000000";
when "1111"=> oup <= "1000000000000000";
when others=> oup<="----------------";
end case;
end process;
end Behavioral;

SIMULATION WAVEFORM:

PROGRAM FOR DECODER IN VERILOG:

module decoder(x, y, z, w, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15);
input x; input y;
input z;
input w;
output d0;
output d1;
output d2;
output d3;
output d4;
output d5;
output d6;
output d7;
output d8;
output d9;
output d10;
output d11;
output d12;
output d13;
output d14;
output d15;
3
and(d0,xbar,ybar,zbar,wbar),(d1,xbar,ybar,zbar,w),(d2,xbar,ybar,z,wbar),(d3,xbar,ybar,z,w),
(d4,xbar,y,zbar,wbar),(d5,xbar,y,zbar,w),(d6,xbar,y,z,wbar),(d7,xbar,y,z,w),
(d8,x,ybar,zbar,wbar),(d9,x,ybar,zbar,w),(d10,x,ybar,z,wbar),(d11,x,ybar,z,w),
(d12,x,y,zbar,wbar),(d13,x,y,zbar,w),(d14,x,y,z,wbar),(d15,x,y,z,w);
not (xbar,x), (ybar,y), (zbar,z), (wbar,w);
endmodule

SIMULATION WAVEFORM:

PROGRAM FOR COMPARATOR IN VHDL:

use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparator is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
e : out STD_LOGIC;
g : out STD_LOGIC;
l : out STD_LOGIC);
end comparator;
architecture Behavioral of comparator is
begin
process(a,b)
begin
if(a=b)then
e<='1';
g<='0';
l<='0';
elsif(a<b)then
e<='0';
g<='0';

3
l<='1';
else
e<='0';
g<='1';
l<='0';
end if;
end process;
end Behavioral;

SIMULATION WAVEFORM:

PROGRAM FOR COMPARATOR IN VERILOG:

module comparator(a3, a2, a1, a0, b3, b2, b1, b0, e, g, l);
input a3;
input a2;
input a1;
input a0;
input b3;
input b2;
input b1;
input b0;
output e;
output g;
output l;
wire e3,e2,e1,e0,g3,g2,g1,g0,l3,l2,l1,l0;
assign e3= a3 ~^ b3;
assign e2= a2 ~^ b2;
assign e1= a1 ~^ b1;
assign e0= a0 ~^ b0;
assign e= e3 & e2 & e1 &e0;
assign g3=a3 & (~b3);
3
 assign g2=e3 & a2 & (~b2);
assign g1=e3 & e2 &a1 & (~b1);
assign g0=e3 & e2 &e1 & a0 & (~b0);
assign g= g3|g2|g1|g0;
assign l3=(~a3) & b3;
assign l2=e3 & (~a2) & b2;
assign l1=e3 & e2 & (~a1) & b1;
assign l0=e3 & e2 & e1 & (~a0) & b0;
assign l=l3|l2|l1|l0;
endmodule

SIMULATION WAVEFORM:

RESULT:

Thus the Multiplexers, Decoders and Comparators are designed using VHDL and Verilog and
the output waveforms are verified.

3
 EX.NO:4 ANALYTICAL MODELLING AND SIMULATION OF
MOSFET USING NEWTON RAPHSON METHOD
DATE:

AIM:

To model and simulate the I-V characteristics of a p-channel /n-channel MOSFETusing

Newton Raphson method.

SOFTWARE REQUIRED:
MATLAB R2009b.

THEORY:
Newton Raphson method is a method for finding successively better
approximations to the roots or zeroes of a real valued function x:f(x)=0. In this method,
the slope (derivative) of the function is calculated at the initial guess value and
projected to the x-axis.The corresponding x-value becomes the new guess value.The
steps are repeated until the answer is obtained to a specified tolerance. If Initial guess at
the root is xi, a tangent can be extended from the point [x i,f(xi)]. The point this tangent
crosses the x axis represents an improved estimate of the root. It is used in many
applications such as artificial intelligence and computer vision to find the non linearity.
It is also called as numerical analysis.

DESIGN EQUATION:
Let x0 be a good estimate of r and let r = x0 + h. Since the true root is
r and h = r x0, the number h measures how far the estimate x0 is from the truth.
Since h is `small,' we can use the linear (tangent line) approximation to conclude
that
0 = f(r) = f(x0 + h) = f(x0) + hf (x0);
and therefore, unless f (x0) is close to 0,
h = - f(x0)/ f (x0)

It follows that
r = x0 + h = x0 f(x0)/ f (x0)
estimate x1 of r is therefore given by
x1 = x0 f(x0)/ f (x0)
3
The next estimate x2 is obtained from x1 in exactly the same way as x1 was obtained
from x0:
x2 = x1 f(x1)/ f (x1)

If xn is the current estimate, then the next estimate xn+1 is given by

xn+1 = xn f(xn)/ f (xn)
ALGORITHM:

STEP1: Open the MATLAB simulation tool.

STEP2: Select File->New->Blank M-File
STEP3: Enter the Matlab code in blank M-File.
STEP4: Save the M-File.
STEP5: Run the code and verify the output.

3
MATLAB CODE:
clc;
clear all;
format long;
syms x;
e = 1e-5; % setting the tolerance value
dx = e + 1;
f = log(2-x) + x^2; % enter your function here;
x = 7; % initially assumed value of x
count = 0; % setting counter to know the no of iterations taken
p = zeros(1,1);
while (abs(dx) > e) % initialising the iteration and continue until the error is less
than tolerance
dx = eval(f/(diff(f))); % calculating dx, diff is used for finding the differentiation
of the fuction
x = x - dx % updating the value of x
count = count + 1; % incrementing the counter
p(count) = x;
drawnow();
plot(abs(p),'r','linewidth',3);
grid;
if (count > 300)
fprintf('Error...! Solution not converging !!! \n'); % printing the error message
break;
end
end
% plot(abs(p));
if (count < 300)
fprintf('The solution = '); %printing the result x
fprintf('\nNumber of iteration taken = %d\n',count);

OUTPUT VALUES:
x = 3.435955076589147 - 0.221238919266887i
x =1.841620360279200 - 0.486957472183211i
x =1.142143257804761 - 0.111858069284186i
x =0.131312877148466 - 0.067228984880217i
x =2.147007040078734 - 0.854391043468283i
x =1.274135317499913 - 0.536259498180818i
x =0.469990337832698 - 0.296519455585065i
x =-0.221699858297857 - 1.065631008629895i
x =0.146463503254323 - 0.818883293583940i
x =0.271776737071754 - 0.844793463436668i
x = 0.268173493274464 - 0.854466836544165i
x =0.268213490583397 - 0.854413796611745i
x =0.268213493174994 - 0.854413795679647i
The solution => x =0.268213493174994 - 0.854413795679647i
Number of iteration taken = 13

OUTPUT WAVEFORM:
3
 Thus the potential distribution/fieldThus tThe distribution/field of the
MOSFET using Finite Difference method is modeled and simulated.

EX.NO:6 MODELING AND ANALYSIS OF MOS CAPACITOR

SMALL SIGNAL ANALYSIS
DATE:

AIM:
To model and analyze MOS Capacitor small signal analysis using Matlab R2009b

SOFTWARE REQUIRED:
Matlab R2009b

DESIGIN PARAMETERS:
VTO (VT0 - zero-bias threshold voltage)
KP (MOSFET transconductance)
GAMMA (_ - bulk threshold parameter)
PHI (2|_F| - surface potential)
LAMBDA (_ - channel length modulation)
UO ( - electron mobility)
TOX (tox - gate oxide thickness)
NSUB (NA - bulk doping concentration)
LD (LD - lateral diffusion)
PB (_B bulk junction potential)
CJ (Cj0 - zero-bias bulk junction bottom capacitance per square meter of junction area)
MJ (mj bulk junction bottom grading coefficient)
CJSW (Cjsw - zero-bias bulk junction sidewall capacitance per meter of junction
perimeter)
MJSW (mjsw bulk junction sidewall grading coefficient)
CGBO (Gate-bulk overlap capacitance per meter channel width)
CGDO (Gate-drain overlap capacitance per meter channel width)
CGSO (Gate-source overlap capacitance per meter channel width)

ALGORITHM:
STEP 1: Start the program using Matlab R2009b.
STEP 2: Enter the code and save it.
STEP 3: Run the program.
STEP 4: Enter the number of energy states, length of well (in nm)and step size(in nm).
STEP 5: Observe the output plot.

MATLAB CODE:
T=300;
NA=1E24;
3
 ND=0;
Ni=1E16;
dox = 0.001e-6;
es = 11.8;
eo = 3.9;
Vg_min = -10;
Vg_max = 30;
kb=1.38E-23;
q=1.602e-19;
eps0=8.85E-12;
eps_sc=es*eps0;
eps_ox=eo*eps0;
VT=kb*T/q;
const = 2*q*Ni*VT/eps_sc
if NA - ND > 0
fim = -VT*log((NA-ND)/Ni)
else
fim = VT*log((ND-NA)/Ni)
end
fis1= -4*fim
fis2= 4*fim
dfis= (fis2-fis1)/200
for i=1:200
fis = fis1 + i*dfis;
fi(i) = fis;
term = exp(fim/VT)-exp(fis/VT)+exp(-fim/VT)-exp(-fis/VT)+NA*(fim-fis)/Ni/VT;
if fis - fim > 0
field_sc(i) = sqrt(-const*term);
else
field_sc(i) = -sqrt(-const*term);
end
Vg(i)=eps_sc/eps_ox*dox*field_sc(i) + fis-fim;
end
ii=0
for i=1:200
if Vg(i) >= Vg_min
if Vg(i) < Vg_max
ii=ii+1;
Vg1(ii)=Vg(i);
field1(ii)=field_sc(i);
fi1(ii) = fi(i);
end
end
end
figure(1);
plot(fi1/VT-fim/VT,Vg1)
hold on;
surface_pot = -2*fim/VT
a(1) = surface_pot;
b(1) = Vg_min;
3
a(2) = surface_pot;
b(2) = Vg_max;
c(1) = 0
d(1) = Vg_min
c(2) = 0
d(2) = Vg_max
e(1) = fis1/VT
f(1) = 0
e(2) = fis2/VT
f(2) = 0
plot(a,b)
plot(c,d)
plot(e,f)
hold off;

OUTPUT VALUES:
T =300
NA =1.0000e+024
ND =0
Ni =1.0000e+016
dox =1.0000e-009
es =11.8000
eo =3.9000
Vg_min = -10
Vg_max = 30
kb =1.3800e-023
q = 1.6020e-019
eps0 =8.8500e-012
eps_sc =1.0443e-010
eps_ox =3.4515e-011
VT = 0.0258
const =7.9288e+005
fim = -0.4760
fis1 =1.9042
fis2 =-1.9042
dfis =-0.0190
ii =0
surface_pot =36.8414
c =0
d =-10
c =0 0
d =-10 30
e = 73.6827
f =0
e =73.6827 -73.6827
f =0 0

3
C-V CHARACTERISTICS :

RESULT:

Thus the MOS Capacitor small signal analysis is modeled and analysed using
Matlab R2009b.
3
EX.NO:7
SCHRODINGER EQUATION BASED DEVICE MODELLING
DATE:

AIM:
Simulation of Schrodinger equation based on device modeling.
SOFTWARE REQUIRED:
MATLAB R2009b.
THEORY:

In quantum mechanics, the Schrdinger equation is a partial differential equation

that describes how the quantum state of some physical system changes with time. It is not
a simple algebraic equation, but a linear partial differential equation. The differential
equation describes the wave function of the system, also called the quantum state or state
vector.

The concept of a state vector, and an equation governing its time evolution,
namely the Schrdinger equation, are fundamental postulates of quantum mechanics.
These ideas cannot be derived from any other principle.

In the standard interpretation of quantum mechanics, the wave function is the most
complete description that can be given to a physical system. Solutions to Schrdinger's
equation describe not only molecular, atomic, and subatomic systems, but also
macroscopic systems, possibly even the whole universe.

The equation is derived by partially differentiating the standard wave equation and
substituting the relation between the momentum of the particle and the wavelength of the
wave associated with the particle in De Broglie's hypothesis.

DESIGN EQUATION:
One dimensional time independent Schrodinger equation:

Where m is the particle's mass,

U is its potential energy,

2 is the Laplacian, and

3
 is the wave function.

Matrix representation of Schrodinger equation:

ALGORITHM:
STEP 1: Start the program using Matlab R2009b.
STEP 2: Enter the code and save it.
STEP 3: Run the program.
STEP 4: Enter the number of energy states, length of well (in nm)and step size(in nm).
STEP 5: Observe the output plot.

MATLAB CODE:
clc;
clear;
x0=0;
m=1.1;
sum2=1;
n=input('Enter energy state n: ');
xl=input('Enter length of the well(in nm): ');
while(floor(m)<m)
h=input('Enter stepsize in nm: ');
m=(xl-x0)/h;
if floor(m)<m
warning('Step size is wrong. Enter proper value')
end
end
x=x0:h:xl;
y=zeros(size(x));
y(1)=0;
y(m+1)=0;
y(2)=1;
fori=3:m
y(i) = -(y(i-2)+((-2+(n*n*pi*pi*h*h/(xl*xl)))*y(i-1)));
sum2=sum2+y(i)^2;
end
y=y/sqrt(sum2); %normalization
y2=y.^2; %y2 gives probability density
figure('color','white')
subplot(2,1,1), plot(x,y,'r')
3
xlabel('Distance in nm')
ylabel('wave function')
subplot(2,1,2),plot(x,y2)
xlabel('Distance in nm')
ylabel('probability density')

OUTPUT WAVEFORM:
Enter energy state n: 10
Enter length of the well (in nm): 10
Enter step size in nm: 0.01

0.05
wave function

-0.05
0 1 2 3 4 5 6 7 8 9 10
Distance in nm
-3
x 10
3
probability density

0
0 1 2 3 4 5 6 7 8 9 10
Distance in nm

RESULT:
Thus the Schrodinger equation is simulated based on device modeling.

3
 EX.NO:8 MODELLING AND SIMULATION OF NMOS AND CMOS
CIRCUITS USING SPICE
DATE:

AIM:
To model and simulate a NMOS and CMOS using Orcad Pspice9.2 Tools.

SOFTWARE REQUIRED:

Orcad Pspice9.2

THEORY:
(1)TWO-INPUT NOR GATE WITH CMOS LOGIC:
The NOR gate is a digital logic gate that implements logical NOR. It behaves
according to the truth table. A HIGH output (1) results if both the inputs to the gate are LOW
(0); if one or both input is HIGH (1), a LOW output (0) results. NOR is the result of the negation
of the OR operator. It can also be seen as an AND gate with all the inputs inverted.
SYMBOL AND TRUTH TABLE:

(2) TWO-INPUT NAND GATE WITH CMOS LOGIC:

The NAND gate is a digital logic gate that implements logical NAND - it behaves
according to the truth table. A LOW output (0) results if both the inputs to the gate are HIGH
(1); if one or both input is LOW (0), a HIGH output (1) results. NAND is the result of the
negation of the AND operator.

3
SYMBOL AND TRUTH TABLE:

(3) DIFFERENTIAL AMPLIFIER WITH NMOS LOGIC:

Differential Amplifier is the basic building block of every OP AMP and is the basis of
high speed digital logic circuit family, called Emitter Coupled Logic (ECL) and they are
commonly used for analog circuits. The name Differential Amplifier is because of, the
Amplifier will find out the Difference between two input sources connected to the base of
two transistors and amplify the Difference.

ALGORITHM:

STEP 1: Create Pspice Project.

STEP 2: Enable blank project. An Orcad Capture Schematic window appears.

STEP3: Select Place-> part and select required components and place in schematic window.
STEP4: Connect the NMOS transistor, PMOS transistor, Voltage sources and GND using
wires.

STEP5: Place Voltage/level markers at input and output terminals.

STEP 6: Assign constant values for voltage sources and bit values for inputs.

STEP 7: Perform transient, DC and switching analysis and simulate the netlist.

STEP 8: View the output waveform in the waveform window.

3
CMOS CIRCUIT (NOR GATE) IN T-SPICE:

SCHEMATIC DIAGRAM:

V 1

5V dc

O F F T IM E = .5 u S D S T M 2
O N T IM E = .5 u S C LK M 4
D E LA Y =
S TA R TV A L = 1 V
O P P V A L = 1 M b re a k P

5 .1 9 0 m V
M 3
5 .0 0 0 V
O F F T IM E = .5 u S D S T M 1
O N T IM E = .5 u S C LK
D E LA Y = M b re a k P
4 .9 9 8 V
S TA R TV A L = 0 V
O P P V A L = 1
V
0V
7 7 4 .6 n V

M 1 M 2

M b re a k N M b re a k N

2 .4 9 9 m V

P-SPICE NETLIST:
*Libraries:
* Local Libraries :
* From [PSPICE NETLIST] section of C:\Program Files\Orcad\PSpice\PSpice.ini file:
.lib "nom.lib"

*Analysis directives:

.TRAN 0 10us 0
.PROBE V(*) I(*) W(*) D(*) NOISE(*)
.INC ".\nor-SCHEMATIC1.net"
3
**** INCLUDING nor-SCHEMATIC1.net ****

* source NOR

M_M1 N00344 N00855 0 0 MbreakN

U_DSTM1 STIM(1,1) $G_DPWR $G_DGND N00978 IO_STM IO_LEVEL=0
+00
+ +.5uS 1
+REPEAT FOREVER
+ +.5uS 0
+ +.5uS 1
+ ENDREPEAT
M_M2 N00344 N00978 0 0 MbreakN
M_M3 N00210 N00978 N00344 N00281 MbreakP
U_DSTM2 STIM(1,1) $G_DPWR $G_DGND N00855 IO_STM IO_LEVEL=0
+01
+ +.5uS 1
+REPEAT FOREVER
+ +.5uS 1
+ +.5uS 1
+ ENDREPEAT
M_M4 N00281 N00855 N00210 N00281 MbreakP
V_V1 N00281 0 5Vdc

**** RESUMING nor-schematic1-nor1.sim.cir ****

.END

OUTPUT WAVEFORM:

3
CMOS CIRCUIT (NAND GATE) IN T-SPICE:

SCHEMATIC DIAGRAM:

V 1

5 V d c

5 .0 0 0 V

M 3 M 4

M b re a k P M b re a k P
V
O F F T IM E = .5 u S D S T M 1
O N T IM E = .5 u S C L K 5 .0 0 0 V
D E L A Y =
S T A R T V A L = 1
O P P V A L = 1 4 .9 9 8 V
V

V 0 V
O F F T IM E = .5 u S D S T M 2 M 1
O N T IM E = .5 u S C L K
D E L A Y =
S T A R T V A L = 0 M b re a k N
2 .4 9 9 m V
O P P V A L = 1

4 .9 9 5 V

M 2

M b re a k N

3
P-SPICE NETLIST:
*Libraries:
* Local Libraries :
* From [PSPICE NETLIST] section of C:\Program Files\Orcad\PSpice\PSpice.ini file:
.lib "nom.lib"

*Analysis directives:

.TRAN 0 10us 0
.PROBE V(*) I(*) W(*) D(*) NOISE(*)
.INC ".\nand-SCHEMATIC1.net"

**** INCLUDING nand-SCHEMATIC1.net ****

* source NAND
M_M1 N00898 N00395 N00360 0 MbreakN
M_M2 N00360 N00495 0 0 MbreakN
M_M3 N00258 N00395 N00898 N00258 MbreakP
M_M4 N00258 N00495 N00898 N00258 MbreakP
V_V1 N00258 0 5Vdc
U_DSTM1 STIM(1,1) $G_DPWR $G_DGND N00395 IO_STM IO_LEVEL=0
+01
+ +.5uS 1
+REPEAT FOREVER
+ +.5uS 1
+ +.5uS 1
+ ENDREPEAT
U_DSTM2 STIM(1,1) $G_DPWR $G_DGND N00495 IO_STM IO_LEVEL=0
+00
+ +.5uS 1
+REPEAT FOREVER
+ +.5uS 0
+ +.5uS 1
+ ENDREPEAT

**** RESUMING nand-schematic1-nand.sim.cir ****

.END

OUTPUT WAVEFORM:

3
NMOS CIRCUIT (DIFFERENTIAL AMPLIFIER ) IN T-SPICE:

SCHEMATIC DIAGRAM:

P-SPICE NETLIST:

.probe
.option probev
3
.option probei
.option probeq
********* Simulation Settings - Parameters and SPICE Options *********
RResistor_1 Vdd Out R=10k
RResistor_2 Vdd Out R=10k
MNMOS_1 Out N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 Gnd N_3 Out Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
VVoltageSource_3 Vdd Gnd DC 5
VVoltageSource_1 N_2 Gnd DC 5
VVoltageSource_2 N_3 Gnd DC 5
ICurrentSource_1 Gnd Gnd DC 5u

********* Simulation Settings - Analysis section *********

.tran/Powerup 20u 20u
.end

OUTPUT WAVEFORM:

3
 RESULT:

Thus the CMOS and NMOS circuit is modeled and simulated using Orcad Pspice9.2
Tools.

3
 EX.NO:9
DESIGN OF DESIGNING FIR FILTERS
DATE:
AIM:
To design a FIR filter using Xilinx Software.

SOFTWARE REQUIRED:
Xilinx- ISE-9.1i

THEORY:

FIR filters are digital filters with finite impulse response. They are also known as non-
recursive digital filters as they do not have the feedback (a recursive part of a filter), even
though recursive algorithms can be used for FIR filter realization.

The transfer function of FIR filter approaches the ideal as the filter order increases, thus
increasing the complexity and amount of time needed for processing input samples of a signal
being filtered.

Due to its simplicity and efficiency, the window method is most commonly used method
for designing filters. One of the drawbacks of FIR filters is a high order of designed filter. FIR
filters can have linear phase characteristic, which is not like IIR filters.

ALGORITHM:
STEP 1: Open Xilinx ISE 9.1i software.
STEP 2: Create a new project using File New project.
STEP 3: Type the program and save the project.
STEP 4: In synthesis/implementation double click synthesize-XST to check syntax.
STEP 5: Choose behavioral simulation.
STEP 6: In create new sourceTest bench waveform and save the test bench waveform.
STEP 7: In Xilinx ISE SimulatorSimulate Behavioral Model.
STEP 8: Verify the output waveform.

PROGRAM FOR FIR FILTER:

module filter(x,h,h1,h2,h3,h4,y,clk);
input [3:0]x;
input [3:0]h,h1,h2,h3,h4;
input clk;
output [10:0]y;
reg [3:0]q1,q2,q3,q4;
wire [10:0]y0,y1,y2,y3,y4;
initial q1=0;
3
initial q2=0;
initial q3=0;
initial q4=0;
always@(posedge clk)
begin
q4<=q3;
q3<=q2;
q2<=q1;
q1<=x;
end
assign y0=x*h;
assign y1=q1*h1;
assign y2=q2*h2;
assign y3=q3*h3;
assign y4=q4*h4;
assign y=y0+y1+y2+y3+y4;
endmodule

SIMULATION WAVEFORM:

3
IMPLEMENTATION USING FPGA KIT:

Before assigning package pins

Save after assigning pins

3
 Double click on synthesis-XST and implement design

Click on send later

Double click on Generate programming files

3
 \

Click finish

3
 Select your file

Right click on the kit

3
Select program

Click ok

Program execution

3
Program succeeded

RESULT:
Thus, the FIR filter is designed and the required output is obtained using Xilinx
Software.