Docslide - Us - Scheme Dell Inspiron n5110 m5110 dq15 Wistron Queen 15 Intel Discrete Uma Sandy PDF

5 4 3 2 1
Discrete/UMA Schematics Document

D
Sandy Bridge D
Intel PCH
2011-01-04
REV : A00
C C
DY :None Installed
UMA:UMA ONLY installed
DN15: ONLY FOR DN15 installed.
DQ15:ONLY FOR DQ15 installed.
PSL: KBC795 PSL circuit for 10mW solution installed.
10mW: External circuit for 10mW solution installed.
B
MUXLESS:MUXLESS solution installed. B
OPTIMUS:OPTIMUS solution installed.
A <Core Design> A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
Size Document Number Rev
A3
QUEEN 15 A00
Date: Tuesday, January 04, 2011 Sheet 1 of 108
5 4 3 2 1
5 4 3 2 1
##OnMainBoard
Block Diagram SYSTEM LDO
INPUTS
APL5916
OUTPUTS
48
CPU DC/DC
ISL95831HRTZ
INPUTS OUTPUTS
42~43
(Discrete/UMA co-lay) 1D05V_VTT 0D85V_S0 DCBATOUT
SYSTEM DC/DC
VCC_CORE
VRAM TPS51218 45
1.N12P-GE-A1-GP(64Mx16b*8)
1GB
Project code : 91.4IE01.001 INPUTS OUTPUTS
D WKS P/N:72.51G63.H0U HYNIX 4 D
WKS P/N:72.41164.I0U SAMSUNG

88,89,90,91
PCB P/N : 10260-1 DCBATOUT 1D05V_VTT
DDR3 Revision : A00 SYSTEM DC/DC

TPS51123RGER 41
800MHz Intel CPU INPUTS OUTPUTS
DDRIII 1066/1333 Channel A 5V_AUX_S5
DDRIII Slot 0 3D3V_AUX_S5
Robson-XT& Sandy Bridge 1066/1333 14 DCBATOUT 5V_S5
3D3V_S5
15V_S5
Seymour-XT& PCIe x 16
DDRIII 1066/1333 Channel B DDRIII Slot 1 SYSTEM DC/DC
Whistler-LP& (Discrete only)
1066/1333 15
TPS51216RUKR 46
N12P-GE 15~25W INPUTS OUTPUTS
PCIE x 1 1D5V_S3
4,5,6,7,8,9,10,11,12,13 Mini-Card DCBATOUT 0D75V_S0
83.84,85,86,87 USB2.0 x 1 802.11a/b/g DDR_VREF_S3
ATI : Co-layout HDMI coming from UMA(default) &
dGPU by reserving Resistor(0ohm) for optional selection.
10/100/
SYSTEM DC/DC
FDIx4x2 RJ45 ISL95831HRTZ 44
NVidia : Co-layout HDMI coming from dGPU(Default) & PCIE x 1 1000 NIC
C
UMA by reserving Resistor(0ohm) for optional selection. (UMA only)
Discreet/UMA Co-lay DMIx4 Realtek CONN INPUTS OUTPUTS C
RTL8111E/8105E
DCBATOUT VCC_GFXCORE
HDMI VGA
I/O Board
Connector
HDMI PCIE x 4 PCIE x 1 NEC USB3.0 USB3.0 X2
RT8208B 92
51 Intel UPD720200FA CONN
INPUTS OUTPUTS
LVDS(Sigal Channel)
LCD PCH PCIE x 1,USB x 1 Mini-Card DCBATOUT VGA_CORE
49
RGB CRT SIM TI CHARGER
Cougar Point USB 2.0 x 3 WWAN
BQ24745 40
CRT 14 USB 2.0/1.1 ports INPUTS OUTPUTS
ETHERNET (10/100/1000Mb)
HP1 +DC_IN_S5
Left Side: CRT Board 82 82 +PBATT DCBATOUT
USB x 1 High Definition Audio MIC IN 26
SATA ports (6) SYSTEM DC/DC
DCIN TPS51311 47
Bluetooth USB2.0 x 5 PCIE ports (8)
63 SATAx1 / USB2.0x1 ESATA/USB/Powershare INPUTS OUTPUTS
LPC I/F
Combo 57
3D3V_S5 1D8V_S0
B ACPI 1.1 B
CAMERA 54 USB 2.0 x 1BPCIE X 1 SYSTEM DC/DC
G9731 93
VOSTRO
17,18,19,20,21,22,23,24,25,26 VOSTRO Express Card INPUTS
26 OUTPUTS
Finger Print 64 USB 2.0 x 1
75 1D5V_S3 1V_VGA_S0
(On daughter board)
AZALIA
Switches
SPI
SATA x 2 INPUTS OUTPUTS

Azalia
LPC Bus
Internal Digital MIC

1D5V_S3 1D5V_S0
CODEC CardReader SD/MMC+/MS/ 5V_S5
3D3V_S5
5V_S0
3D3V_S0
Flash ROM LPC debug port Realtek MS Pro/xD 74
IDT
92HD87
4MB 60 71
RTS5138 32 PCB LAYER
29
KBC HDD L1:Top L4:Signal
D/A L2:VCC L5:GND
56
L3:Signal L6:Bottom
A
NUVOTON <Core Design> A
NPCE795P A/D ODD
27
56
2CH SPEAKER 58 Wistron Corporation
Fan Control Taipei Hsien 221, Taiwan, R.O.C.
P2793 55 Title
Touch Int. Thermal Block Diagram
PAD KB P2800 28 A3
69 69 25 QUEEN 15 A00
5 4 3 2 1
A B C D E
PCH Strapping Huron River Schematic Checklist Rev.0_7 Processor Strapping Huron River Schematic Checklist Rev.0_7
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k[ CFG[2] PCI-Express Static 1: Normal Operation.
- 10-k[ weak pull-up resistor. Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1
Lane Reversal 0:
INIT3_3V# Weak internal pull-up. Leave as "No Connect".
Disabled - No Physical Display Port attached to
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile. CFG[4] 1: Embedded DisplayPort.
4 GNT2#/GPIO53 Mobile: Used as GPIO only
Enabled - An external Display Port device is
0 4
GNT1#/GPIO51 Pull-up resistors are not required on these signals. 0: connectd to the EMBEDDED display Port
If pull-ups are used, they should be tied to the Vcc3_3power rail.
CFG[6:5] PCI-Express 11 : x16 - Device 1 functions 1 and 2 disabled
Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor. Port Bifurcation 10 : x8, x8 - Device 1 function 1 enabled ;
SPI_MOSI function 2 disabled
Straps 11
Disable Danbury:Left floating, no pull-down required. 01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm enabled
weak pull-up resistor [CRB has it pulled up
NV_ALE with 1-kohm no-stuff resistor] CFG[7] PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion
1
0: PEG Wait for BIOS for training
Disable Danbury:Leave floating (internal pull-down)
NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.
Low (0) - Flash Descriptor Security will be overridden. Also,
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features. Voltage Rails
HAD_DOCK_EN# High (1) - Security measure defined in the Flash Descriptor will be enabled. POWER PLANE VOLTAGE DESCRIPTION
Platform design should provide appropriate pull-up or pull-down depending on ACTIVE IN
/GPIO[33]
3 the desired settings. If a jumper option is used to tie this signal to GND as 5V_S0
3D3V_S0
5V
3.3V 3
required by the functional strap, the signal should be pulled low through a weak 1D8V_S0 1.8V
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. 1D5V_S0 1.5V
1D05V_VTT 1.05V
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal 0D85V_S0 0.95 - 0.85V
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for 0D75V_S0 0.75V
strapping functions. VCC_CORE 0.35V to 1.5V
VCC_GFXCORE 0.4 to 1.25V S0
1D8V_VGA_S0 1.8V
3D3V_VGA_S0 3.3V CPU Core Rail
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. 1V_VGA_S0 1V Graphics Core Rail
HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no 5V_USBX_S3 5V
GPIO15 1D5V_S3 1.5V S3
confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher DDR_VREF_S3 0.75V
suite with confidentiality
Note : This is an un-muxed signal.
BT+ 6V-14.1V AC Brick Mode only
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. DCBATOUT 6V-14.1V
Sampled at rising edge of RSMRST#. 5V_S5 5V All S states
CRB has a 1-kohm pull-up on this signal to +3.3VA rail. 5V_AUX_S5 5V
3D3V_S5 3.3V
3D3V_AUX_S5 3.3V
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down
GPIO8 using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of 3D3V_LAN_S5 3.3V WOL_EN Legacy WOL
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
enabled.
2 Default = Do not connect (floating) 3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states 2
High(1) = Enables the internal VccVRM to have a clean supply for
GPIO27 analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter Powered by Li Coin Cell in G3
circuits for analog rails. 3D3V_AUX_S5 3.3V G3, Sx and +V3ALW in Sx
USB Table
Pair Device
SMBus ADDRESSES
PCIE Routing 0 Touch Panel / 3G SIM
1 USB Ext. port 1 (HS) I 2 C / SMBus Addresses
HURON RIVER ORB
2 Fingerprint Device Ref Des Address Hex Bus
LANE1 Card Reader
3 BLUETOOTH
EC SMBus 1 BAT_SCL/BAT_SDA
LANE2 Mini Card1(WLAN) SATA Table 4 Mini Card2 (WWAN) Battery BAT_SCL/BAT_SDA
CHARGER BAT_SCL/BAT_SDA
LANE3 Mini Card2(WWAN) 5 CARD READER

SATA EC SMBus 2
6 X SML1_CLK/SML1_DATA
PCH SML1_CLK/SML1_DATA
LANE4 Onboard LAN Pair Device eDP
SML1_CLK/SML1_DATA
7 X
1 <Variant Name>
1
0 HDD1 8 USB Ext. port 4 / E-SATA /USB CHARGER
LANE5 USB3.0
1 HDD2 9 USB Ext. port 2 PCH SMBus
PCH_SMBDATA/PCH_SMBCLK
Wistron Corporation
SO-DIMMA (SPD) 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
LANE6 Intel GBE LAN 2 N/A 10 USB Ext. port 3 SO-DIMMB (SPD) PCH_SMBDATA/PCH_SMBCLK Taipei Hsien 221, Taiwan, R.O.C.
Digital Pot PCH_SMBDATA/PCH_SMBCLK
G-Sensor PCH_SMBDATA/PCH_SMBCLK Title
LANE7 Dock 3 N/A 11 Mini Card1 (WLAN) MINI PCH_SMBDATA/PCH_SMBCLK
4 ODD 12 CAMERA PCH_SMBDATA/PCH_SMBCLK Table of Content
LANE8 Express Card 5 ESATA 13 Express Card A3
A00
QUEEN 15
Tuesday, January 04, 2011
Date: Sheet 3 of 108
5 4 3 2 1
SSID = CPU
Signal Routing Guideline:
PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
1D05V_VTT
CPU1A 1 OF 9
J22 PEG_IRCOMP_R R401 1 2 24D9R2F-L-GP
PEG_ICOMPI
19 DMI_TXN[3:0] SANDY PEG_ICOMPO J21
Note: DMI_TXN0 B27 H22
DMI_RX#0 PEG_RCOMPO
D Intel DMI supports both Lane DMI_TXN1
DMI_TXN2
B25
A25
DMI_RX#1 PEG_RXN[0..15]
D
Reversal and polarity inversion DMI_RX#2 PEG_RXN[0..15] 83
DMI_TXN3 B24 K33 PEG_RXN15
but only at PCH side. This is DMI_RX#3 PEG_RX#0 PEG_RXN14
19 DMI_TXP[3:0] PEG_RX#1 M35
enabled via a soft strap. DMI_TXP0 B28 L34 PEG_RXN13
DMI_TXP1 DMI_RX0 PEG_RX#2 PEG_RXN12
B26 DMI_RX1 PEG_RX#3 J35
DMI
DMI_TXP2 A24 J32 PEG_RXN11
DMI_TXP3 DMI_RX2 PEG_RX#4 PEG_RXN10
B23 DMI_RX3 PEG_RX#5 H34
H31 PEG_RXN9
19 DMI_RXN[3:0] DMI_RXN0 PEG_RX#6 PEG_RXN8
G21 DMI_TX#0 PEG_RX#7 G33
DMI_RXN1 E22 G30 PEG_RXN7
DMI_RXN2 DMI_TX#1 PEG_RX#8 PEG_RXN6
F21 DMI_TX#2 PEG_RX#9 F35
DMI_RXN3 D21 E34 PEG_RXN5
DMI_TX#3 PEG_RX#10 PEG_RXN4
19 DMI_RXP[3:0] PEG_RX#11 E32
DMI_RXP0 G22 D33 PEG_RXN3
DMI_RXP1 DMI_TX0 PEG_RX#12 PEG_RXN2
D22 DMI_TX1 PEG_RX#13 D31
PCI EXPRESS* - GRAPHICS

DMI_RXP2 F20 B33 PEG_RXN1
DMI_RXP3 DMI_TX2 PEG_RX#14 PEG_RXN0
C21 DMI_TX3 PEG_RX#15 C32
PEG_RXP[0..15]
PEG_RXP[0..15] 83
J33 PEG_RXP15
PEG_RX0 PEG_RXP14
PEG_RX1 L35
K34 PEG_RXP13
19 FDI_TXN[7:0] FDI_TXN0 PEG_RX2 PEG_RXP12
A21 FDI0_TX#0 PEG_RX3 H35
FDI_TXN1 H19 H32 PEG_RXP11
FDI_TXN2 FDI0_TX#1 PEG_RX4 PEG_RXP10
Note: E19 FDI0_TX#2 PEG_RX5 G34
FDI_TXN3 F18 G31 PEG_RXP9
Intel(R) FDI
Intel FDI supports both Lane FDI0_TX#3 PEG_RX6
FDI_TXN4 B21 F33 PEG_RXP8
Reversal and polarity inversion FDI_TXN5 C20
FDI1_TX#0 PEG_RX7
F30 PEG_RXP7
but only at PCH side. This is FDI_TXN6 FDI1_TX#1 PEG_RX8 PEG_RXP6
D18 FDI1_TX#2 PEG_RX9 E35
C enabled via a soft strap. FDI_TXN7 E17 FDI1_TX#3 PEG_RX10 E33
F32
PEG_RXP5
PEG_RXP4 NOTE.
C
PEG_RX11 PEG_RXP3
19 FDI_TXP[7:0] PEG_RX12 D34 If PEG is not implemented, the RX&TX pairs can be left as No Connect
FDI_TXP0 A22 E31 PEG_RXP2
FDI_TXP1 FDI0_TX0 PEG_RX13 PEG_RXP1
G19 FDI0_TX1 PEG_RX14 C33
FDI_TXP2 E20 B32 PEG_RXP0 PEG Static Lane Reversal PEG_TXN[0..15]
FDI_TXP3 FDI0_TX2 PEG_RX15 PEG_TXN[0..15] 83
G18 FDI0_TX3
FDI_TXP4 B20 M29 PEG_C_TXN15 C401 1MUXLESS
2 SCD22U10V2KX-1GP PEG_TXN15
FDI_TXP5 FDI1_TX0 PEG_TX#0 PEG_C_TXN14 C402 SCD22U10V2KX-1GP PEG_TXN14
C19 FDI1_TX1 PEG_TX#1 M32 1MUXLESS
2
FDI_TXP6 D19 M31 PEG_C_TXN13 C403 1MUXLESS
FDI_TXP7 FDI1_TX2 PEG_TX#2 PEG_C_TXN12 C404 SCD22U10V2KX-1GP PEG_TXN12
F17 FDI1_TX3 PEG_TX#3 L32 1MUXLESS
2
L29 PEG_C_TXN11 C405 1MUXLESS
PEG_TX#4 PEG_C_TXN10 C406 SCD22U10V2KX-1GP PEG_TXN10
19 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#5 K31 1MUXLESS
2
Note: J17 K28 PEG_C_TXN9 C407 1MUXLESS
19 FDI_FSYNC1 FDI1_FSYNC PEG_TX#6
Lane reversal does not apply to J30 PEG_C_TXN8 C408 1MUXLESS
19 FDI_INT H20 J28 1MUXLESS
2
FDI sideband signals. FDI_INT PEG_TX#8
H29 PEG_C_TXN6 C410 1MUXLESS
19 FDI_LSYNC0 J19 FDI0_LSYNC PEG_TX#10 G27 1MUXLESS
2
H17 E29 PEG_C_TXN4 C412 1MUXLESS
19 FDI_LSYNC1 FDI1_LSYNC PEG_TX#11
F27 PEG_C_TXN3 C413 1MUXLESS
0719 Modify: PEG_TX#12 PEG_C_TXN2 C414 SCD22U10V2KX-1GP PEG_TXN2
PEG_TX#13 D28 1MUXLESS
2
un-stuff R403 base on Intel James feedback list. F26 PEG_C_TXN1 C415 1MUXLESS
PEG_TX#15 E25 1MUXLESS
2
R402 1 2 24D9R2F-L-GP DP_COMP A18 PEG_TXP[0..15]
1D05V_VTT EDP_COMPIO PEG_TXP[0..15] 83
A17 M28 PEG_C_TXP15 C417 1MUXLESS
2 SCD22U10V2KX-1GP PEG_TXP15
EDP_ICOMPO PEG_TX0
1 R403 2 eDP_HPD B16 EDP_HPD PEG_TX1 M33 PEG_C_TXP14 C418 1MUXLESS
10KR2J-3-GP M30 PEG_C_TXP13 C419 1MUXLESS
DY PEG_TX2
L31 PEG_C_TXP12 C420 1MUXLESS
PEG_TX3 PEG_C_TXP11 C421 SCD22U10V2KX-1GP PEG_TXP11
C15 EDP_AUX PEG_TX4 L28 1MUXLESS
2
D15 K30 PEG_C_TXP10 C422 1MUXLESS
B Signal Routing Guideline: EDP_AUX#
eDP PEG_TX5
PEG_TX6 K27 PEG_C_TXP9 C423 1MUXLESS
2 SCD22U10V2KX-1GP PEG_TXP9 B
EDP_ICOMPO keep W/S=12/15 mils and routing J29 PEG_C_TXP8 C424 1MUXLESS
PEG_TX7 PEG_C_TXP7 C425 SCD22U10V2KX-1GP PEG_TXP7
C17 J27 1MUXLESS
2
length less than 500 mils. F16
EDP_TX0 PEG_TX8
H28 PEG_C_TXP6 C426 1MUXLESS
EDP_COMPIO keep W/S=4/15 mils and routing EDP_TX1 PEG_TX9 PEG_C_TXP5 C427 SCD22U10V2KX-1GP PEG_TXP5
C16 EDP_TX2 PEG_TX10 G28 1MUXLESS
2
length less than 500 mils. G15 E28 PEG_C_TXP4 C428 1MUXLESS
EDP_TX3 PEG_TX11 PEG_C_TXP3 C429 SCD22U10V2KX-1GP PEG_TXP3
PEG_TX12 F28 1MUXLESS
2
C18 D27 PEG_C_TXP2 C430 1MUXLESS
EDP_TX#0 PEG_TX13 PEG_C_TXP1 C431 SCD22U10V2KX-1GP PEG_TXP1
E16 EDP_TX#1 PEG_TX14 E26 1MUXLESS
2
D16 D25 PEG_C_TXP0 C432 1MUXLESS
EDP_TX#2 PEG_TX15
NOTE. F15 EDP_TX#3
Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.
SANDY SKT-BGA989C470395-1H180
62.10055.421
Stuff to disable internal graphics 2nd = 62.10040.771 A00 0103 add 3rd foxcon CPU1 at XBuild batch run
function for power saving. 3rd = 62.10055.321
NOTE:
Select a Fast FET similar to 2N7002E whose rise/
fall time is less than 6 ns. If HPD on eDP interface is
disabled, connect it to CPU VCCIO via a 10-k[ pull-Up
resistor on the motherboard.
<Variant Name>
A A
Wistron Corporation
Title
CPU (PCIE/DMI/FDI)
A3
QUEEN 15 A00
5 4 3 2 Disabling Guidelines: 1
SSID = CPU CPU1B 2 OF 9
If motherboard only supports external graphics:
Connect DPLL_REF_SSCLK on Processor to GND through
1K +/- 5% resistor.
SANDY Connect DPLL_REF_SSCLK# on Processor to VCCP
BCLK A28 CLK_EXP_P 20 through 1K +/- 5% resistorpower (~15 mW) may be
MISC
CLOCKS
18 H_SNB_IVB# C26 A27 CLK_EXP_N 20
SNB_IVB# BCLK# wasted.
0625 Modify:
1D05V_VTT Add C502 47p 0402 on H_PROCHOT#. 1 SKTOCC#_R AN34
TPAD14-GP TP501 SKTOCC#
DPLL_REF_SSCLK A16 CLK_DP_P_R 1 R512 2
R501
DPLL_REF_SSCLK# A15 CLK_DP_N_R 1 R514 1KR2J-1-GP
2 1D05V_VTT
1 2 H_PROCHOT# 1KR2J-1-GP
D 62R2J-GP 1 H_CATERR# AL33
0617 Modify: D
TPAD14-GP TP502 CATERR# Joseph change RN501 to R512,R514 1K 0402 Resistor.
1
C502
THERMAL
SC47P50V2JN-3GP 1R502 2
2
AN33 R8 4K99R2F-L-GP SM_DRAMRST# 37

22,27 H_PECI PECI SM_DRAMRST#
20100622 V1.2
DDR3
MISC
R513
CRB : 47pf 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 R506 1 2 140R2F-GP
27,40,42 H_PROCHOT# PROCHOT# SM_RCOMP0
CEKLT:43pf 56R2J-4-GP SM_RCOMP1 A5 SM_RCOMP_1 R507 1
SM_RCOMP_2 R508 1
2 25D5R2F-GP
SM_RCOMP2 A4 2 200R2F-L-GP
Connect EC to PROCHOT# through inverting OD buffer.
22,36 H_THERMTRIP# AN32 THERMTRIP#
Signal Routing Guideline:
SM_RCOMP keep routing length less than 500 mils.
AP29 XDP_PRDY# 1
PRDY# TP511 TPAD14-GP
AP27 XDP_PREQ# 1
PREQ# TP512 TPAD14-GP
AR26 XDP_TCLK
TCK
PWR MANAGEMENT
XDP_TMS
JTAG & BPM

TMS AR27
AM34 AP30 XDP_TRST#
19 H_PM_SYNC PM_SYNC TRST#
EC505
A00 1229 EMI 2 1 MS04A03T2V2-GP-U AR28 XDP_TDI
DY TDI
AP26 XDP_TDO 0721 Modify:
TDO SWAP RN501 pin1,2,3 1D05V_VTT
22,36 H_CPUPW RGD 1 R504 2 H_CPUPW RGD_R AP33 UNCOREPWRGOOD
0R0402-PAD base on swap report.
C 1R503 2
10KR2J-3-GP AL35 XDP_DBRESET# RN501 C
R505 2 VDDPW RGOOD DBR# XDP_TDO
19,37 PM_DRAM_PW RGD 1 V8 SM_DRAMPWROK 1 8
0R2J-2-GP XDP_TMS 2 7
DY AT28 XDP_BPM0 1 XDP_TDI 3 6
BPM#0 TP503 TPAD14-GP
37 VDDPW RGOOD AR29 XDP_BPM1 1 XDP_TCLK 4 5
AR30 XDP_BPM2 1
R510 1 2 BUF_CPU_RST# AR33 AT30 XDP_BPM3 1 SRN51J-1-GP
18,27,71,75,82,83 PLT_RST# RESET# BPM#3 TP506 TPAD14-GP
AP32 XDP_BPM4 1
1K5R2F-2-GP AR31 XDP_BPM5 1 XDP_TRST# R511 1 2 51R2J-2-GP
MS04A03T2V2-GP-U

1
AT31 XDP_BPM6 1
1
R509 AR32 XDP_BPM7 1

1
750R2F-GP
C501
EC506
DY DY SC220P50V2KX-3GP
2
SANDY SKT-BGA989C470395-1H180 0630 Modify:

2
A00 1230 EMI 62.10055.421 Removed XDP1101 connector

0623 Modify: 3D3V_S0
Reserved C501 220pF 0402 on BUF_CPU_RST#. 2nd = 62.10040.771 related circuit by layout limitation.
3rd = 62.10055.321 A00 0103 add 3rd foxcon CPU1 at XBuild batch run
19 XDP_DBRESET# XDP_DBRESET# 1 2 R516

10KR2J-3-GP
0617 Modify: 0707 Modify:
Change R516 10K from 1K
Joseph Removed U501 Buffer reset to CPU circuit.
B XDP_TRST# B
0719 Modify: 1D05V_VTT
Add buffer for PLT_RST# based on Intel review.
3D3V_S0 XDP_DBRESET#
1
A00 1229 EMI
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
R518
DY
1
75R2J-1-GP
Buffered reset to CPU DYC503
2
SCD1U10V2KX-5GP
EC502
EC504
U501
2
1 IN B VCC 5
1
2
18,27,71,75,82,83 PLT_RST# IN A DY
2
3 4 BUFO_CPU_RST# 1 2 BUF_CPU_RST#
GND OUT Y R517 DY43R2J-GP
1
74VHC1G09DFT2G-GP
73.01G09.AAH DYR515
0R2J-2-GP
2
A <Variant Name>
A
Wistron Corporation
Title
CPU (THERMAL/CLOCK/PM )
A3
QUEEN 15 A00
5 4 3 2 1
SSID = CPU
CPU1C 3 OF 9 CPU1D 4 OF 9
SANDY
AB6
SANDY AE2
M_A_DQ[63:0] SA_CLK0 M_A_DIM0_CLK_DDR0 15 M_B_DQ[63:0] SB_CLK0 M_B_DIM0_CLK_DDR0 14
15 M_A_DQ[63:0] SA_CLK#0 AA6 M_A_DIM0_CLK_DDR#0 15 14 M_B_DQ[63:0] SB_CLK#0 AD2 M_B_DIM0_CLK_DDR#0 14
M_A_DQ0 C5 V9 M_B_DQ0 C9 R9
M_A_DQ1 SA_DQ0 SA_CKE0 M_A_DIM0_CKE0 15 M_B_DQ1 SB_DQ0 SB_CKE0 M_B_DIM0_CKE0 14
D D5 SA_DQ1 A7 SB_DQ1 D
M_A_DQ2 D3 M_B_DQ2 D10
M_A_DQ3 SA_DQ2 M_B_DQ3 SB_DQ2
D2 SA_DQ3 C8 SB_DQ3
M_A_DQ4 D6 AA5 M_B_DQ4 A9 AE1
M_A_DQ5 SA_DQ4 SA_CLK1 M_A_DIM0_CLK_DDR1 15 M_B_DQ5 SB_DQ4 SB_CLK1 M_B_DIM0_CLK_DDR1 14
C6 SA_DQ5 SA_CLK#1 AB5 M_A_DIM0_CLK_DDR#1 15 A8 SB_DQ5 SB_CLK#1 AD1 M_B_DIM0_CLK_DDR#1 14
M_A_DQ6 C2 V10 M_B_DQ6 D9 R10
M_A_DQ7 SA_DQ6 SA_CKE1 M_A_DIM0_CKE1 15 M_B_DQ7 SB_DQ6 SB_CKE1 M_B_DIM0_CKE1 14
C3 SA_DQ7 D8 SB_DQ7
M_A_DQ8 F10 M_B_DQ8 G4
F8 SA_DQ9 F4 SB_DQ9
M_A_DQ10 G10 AB4 M_B_DQ10 F1 AB2
M_A_DQ11 SA_DQ10 SA_CLK2 M_B_DQ11 SB_DQ10 SB_CLK2
G9 SA_DQ11 SA_CLK#2 AA4 G1 SB_DQ11 SB_CLK#2 AA2
M_A_DQ12 F9 W9 M_B_DQ12 G5 T9
M_A_DQ13 SA_DQ12 SA_CKE2 M_B_DQ13 SB_DQ12 SB_CKE2
F7 SA_DQ13 F5 SB_DQ13
M_A_DQ14 G8 M_B_DQ14 F2
G7 SA_DQ15 G2 SB_DQ15
M_A_DQ16 K4 AB3 M_B_DQ16 J7 AA1
M_A_DQ17 SA_DQ16 SA_CLK3 M_B_DQ17 SB_DQ16 SB_CLK3
K5 SA_DQ17 SA_CLK#3 AA3 J8 SB_DQ17 SB_CLK#3 AB1
M_A_DQ18 K1 W10 M_B_DQ18 K10 T10
M_A_DQ19 SA_DQ18 SA_CKE3 M_B_DQ19 SB_DQ18 SB_CKE3
J1 SA_DQ19 K9 SB_DQ19
M_A_DQ20 J5 M_B_DQ20 J9
J4 SA_DQ21 J10 SB_DQ21
M_A_DQ22 J2 AK3 M_B_DQ22 K8 AD3
M_A_DQ23 SA_DQ22 SA_CS#0 M_A_DIM0_CS#0 15 M_B_DQ23 SB_DQ22 SB_CS#0 M_B_DIM0_CS#0 14
K2 SA_DQ23 SA_CS#1 AL3 M_A_DIM0_CS#1 15 K7 SB_DQ23 SB_CS#1 AE3 M_B_DIM0_CS#1 14
M_A_DQ24 M8 AG1 M_B_DQ24 M5 AD6
M_A_DQ25 SA_DQ24 SA_CS#2 M_B_DQ25 SB_DQ24 SB_CS#2
N10 SA_DQ25 SA_CS#3 AH1 N4 SB_DQ25 SB_CS#3 AE6
M_A_DQ26 N8 M_B_DQ26 N2
N7 SA_DQ27 N1 SB_DQ27
M_A_DQ28 M10 M_B_DQ28 M4
M9 SA_DQ29 SA_ODT0 AH3 M_A_DIM0_ODT0 15 N5 SB_DQ29 SB_ODT0 AE4 M_B_DIM0_ODT0 14
DDR SYSTEM MEMORY B

C M_A_DQ30 N9 AG3 M_B_DQ30 M2 AD4 C
M_A_DQ31
M_A_DQ32
M7
AG6
SA_DQ30
SA_DQ31 DDR SYSTEM MEMORY A SA_ODT1
SA_ODT2 AG2
AH2
M_A_DIM0_ODT1 15 M_B_DQ31
M_B_DQ32
M1
AM5
SB_DQ30
SB_DQ31
SB_ODT1
SB_ODT2 AD5
AE5
M_B_DIM0_ODT1 14
M_A_DQ33 SA_DQ32 SA_ODT3 M_B_DQ33 SB_DQ32 SB_ODT3

AG5 SA_DQ33 AM6 SB_DQ33
M_A_DQ34 AK6 M_B_DQ34 AR3
AK5 SA_DQ35 AP3 SB_DQ35
M_A_DQ36 AH5 M_A_DQS#[7:0] 15 M_B_DQ36 AN3 M_B_DQS#[7:0] 14
M_A_DQ37 SA_DQ36 M_A_DQS#0 M_B_DQ37 SB_DQ36 M_B_DQS#0
AH6 SA_DQ37 SA_DQS#0 C4 AN2 SB_DQ37 SB_DQS#0 D7
M_A_DQ38 AJ5 G6 M_A_DQS#1 M_B_DQ38 AN1 F3 M_B_DQS#1
M_A_DQ39 SA_DQ38 SA_DQS#1 M_A_DQS#2 M_B_DQ39 SB_DQ38 SB_DQS#1 M_B_DQS#2
AJ6 SA_DQ39 SA_DQS#2 J3 AP2 SB_DQ39 SB_DQS#2 K6
M_A_DQ40 AJ8 M6 M_A_DQS#3 M_B_DQ40 AP5 N3 M_B_DQS#3
AK8 SA_DQ41 SA_DQS#4 AL6 AN9 SB_DQ41 SB_DQS#4 AN5
M_A_DQ42 AJ9 AM8 M_A_DQS#5 M_B_DQ42 AT5 AP9 M_B_DQS#5
AK9 SA_DQ43 SA_DQS#6 AR12 AT6 SB_DQ43 SB_DQS#6 AK12
M_A_DQ44 AH8 AM15 M_A_DQS#7 M_B_DQ44 AP6 AP15 M_B_DQS#7
M_A_DQ45 SA_DQ44 SA_DQS#7 M_B_DQ45 SB_DQ44 SB_DQS#7
AH9 SA_DQ45 AN8 SB_DQ45
M_A_DQ46 AL9 M_B_DQ46 AR6
AL8 SA_DQ47 AR5 SB_DQ47
M_A_DQ48 AP11 M_A_DQS[7:0] 15 M_B_DQ48 AR9 M_B_DQS[7:0] 14
M_A_DQ49 SA_DQ48 M_A_DQS0 M_B_DQ49 SB_DQ48 M_B_DQS0
AN11 SA_DQ49 SA_DQS0 D4 AJ11 SB_DQ49 SB_DQS0 C7
M_A_DQ50 AL12 F6 M_A_DQS1 M_B_DQ50 AT8 G3 M_B_DQS1
M_A_DQ51 SA_DQ50 SA_DQS1 M_A_DQS2 M_B_DQ51 SB_DQ50 SB_DQS1 M_B_DQS2
AM12 SA_DQ51 SA_DQS2 K3 AT9 SB_DQ51 SB_DQS2 J6
M_A_DQ52 AM11 N6 M_A_DQS3 M_B_DQ52 AH11 M3 M_B_DQS3
AL11 SA_DQ53 SA_DQS4 AL5 AR8 SB_DQ53 SB_DQS4 AN6
M_A_DQ54 AP12 AM9 M_A_DQS5 M_B_DQ54 AJ12 AP8 M_B_DQS5
AN12 SA_DQ55 SA_DQS6 AR11 AH12 SB_DQ55 SB_DQS6 AK11
M_A_DQ56 AJ14 AM14 M_A_DQS7 M_B_DQ56 AT11 AP14 M_B_DQS7
M_A_DQ57 SA_DQ56 SA_DQS7 M_B_DQ57 SB_DQ56 SB_DQS7
AH14 SA_DQ57 AN14 SB_DQ57
M_A_DQ58 AL15 M_B_DQ58 AR14
B M_A_DQ59 SA_DQ58 M_B_DQ59 SB_DQ58 B
AK15 SA_DQ59 AT14 SB_DQ59
M_A_DQ60 AL14 M_B_DQ60 AT12
M_A_DQ61 SA_DQ60 M_A_A0 M_A_A[15:0] 15 M_B_DQ61 SB_DQ60 M_B_A0 M_B_A[15:0] 14
AK14 SA_DQ61 SA_MA0 AD10 AN15 SB_DQ61 SB_MA0 AA8
M_A_DQ62 AJ15 W1 M_A_A1 M_B_DQ62 AR15 T7 M_B_A1
M_A_DQ63 SA_DQ62 SA_MA1 M_A_A2 M_B_DQ63 SB_DQ62 SB_MA1 M_B_A2
AH15 SA_DQ63 SA_MA2 W2 AT15 SB_DQ63 SB_MA2 R7
W7 M_A_A3 T6 M_B_A3
SA_MA3 M_A_A4 SB_MA3 M_B_A4
SA_MA4 V3 SB_MA4 T2
V2 M_A_A5 T4 M_B_A5
SA_MA6 W3 SB_MA6 T3
15 M_A_BS0 AE10 W6 M_A_A7 14 M_B_BS0 AA9 R2 M_B_A7
SA_BS0 SA_MA7 M_A_A8 SB_BS0 SB_MA7 M_B_A8
15 M_A_BS1 AF10 SA_BS1 SA_MA8 V1 14 M_B_BS1 AA7 SB_BS1 SB_MA8 T5
15 M_A_BS2 V6 W5 M_A_A9 14 M_B_BS2 R6 R3 M_B_A9
SA_BS2 SA_MA9 M_A_A10 SB_BS2 SB_MA9 M_B_A10
SA_MA10 AD8 SB_MA10 AB7
V4 M_A_A11 R1 M_B_A11
SA_MA12 W4 SB_MA12 T1
15 M_A_CAS# AE8 AF8 M_A_A13 14 M_B_CAS# AA10 AB10 M_B_A13
SA_CAS# SA_MA13 M_A_A14 SB_CAS# SB_MA13 M_B_A14
15 M_A_RAS# AD9 SA_RAS# SA_MA14 V5 14 M_B_RAS# AB8 SB_RAS# SB_MA14 R5
15 M_A_W E# AF9 V7 M_A_A15 14 M_B_W E# AB9 R4 M_B_A15
SA_WE# SA_MA15 SB_WE# SB_MA15
SANDY SANDY
62.10055.421 62.10055.421
2nd = 62.10040.771 2nd = 62.10040.771
3rd = 62.10055.321 A00 0103 add 3rd foxcon CPU1 at XBuild batch run 3rd = 62.10055.321 A00 0103 add 3rd foxcon CPU1 at XBuild batch run
A <Variant Name> A
Wistron Corporation
Title
CPU (DDR)
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
SSID = CPU CFG2

CPU1E 5 OF 9
1
PEG Static Lane Reversal
0630 Modify: R702
Reserved TP715 on CFG0. 1KR2J-1-GP 1: Normal Operation; Lane #
RSVD#L7 L7 MUXLESS
RSVD#AG7 AG7 CFG2 definition matches socket pin map definition
1 CFG0 AK28 AE7
SANDY
2
TPAD14-GP TP715 CFG0 RSVD#AE7 0:Lane Reversed
AK29 CFG1 RSVD#AK2 AK2
CFG2 AL26 W8
CFG2 RSVD#W8
AL27 CFG3
CFG4 AK26
CFG5 CFG4
D AL29 CFG5 RSVD#AT26 AT26 D
CFG6 AL30 AM33
CFG7 CFG6 RSVD#AM33
AM31 CFG7 RSVD#AJ27 AJ27
AM32 CFG4
0707 Modify: CFG8
AM30 CFG9
Removed CFG1,CFG3,CFG8~17 TP. AM28 Display Port Presence Strap
CFG10
1
AM26 CFG11
AN28 R703 CFG4 1: Disabled; No Physical Display Port
AN31
CFG12
T8
DY 3K3R2F-2-GP attached to Embedded Display Port
CFG13 RSVD#T8
AN26 CFG14 RSVD#J16 J16
AM27 H16 0: Enabled; An external Display Port device is
2
CFG15 RSVD#H16
AK31 CFG16 RSVD#G16 G16 connected to the Embedded Display Port
AN29 CFG17
0617 Modify:
Joseph Change M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, RSVD#AR35 AR35
AJ31 RSVD#AJ31 RSVD#AT34 AT34
M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 AH31 AT33
RSVD#AH31 RSVD#AT33 CFG5
from net to power. AJ33 RSVD#AJ33 RSVD#AP35 AP35
AH33 RSVD#AH33 RSVD#AR34 AR34
CFG6 PCIE Port Bifurcation Straps
1
AJ26
M3 - Processor Generated SO-DIMM VREF_DQ RSVD#AJ26
RESERVED
R701 R704 CFG[6:5] 11: x16 - Device 1 functions 1 and 2 disabled
DY DY
DY B4:VREF_DQ CHA B34 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
R708 1 RSVD#B34 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
M_VREF_DQ_DIMM0 DY 2 0R2J-2-GP M_VREF_DQ_DIMM0_C B4 A33
2
R709 1 RSVD#B4 RSVD#A33 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
2 0R2J-2-GP M_VREF_DQ_DIMM1_C D1 A34
1KR2J-1-GP
1KR2J-1-GP
M_VREF_DQ_DIMM1 RSVD#D1 RSVD#A34
C B35 C
RSVD#B35
D1:VREF_DQ CHB RSVD#C35 C35
1
1
F25 RSVD#F25
R711 R712 F24 CFG7
RSVD#F24
F23 RSVD#F23
1KR2F-3-GP 1KR2F-3-GP D24 AJ32 PEG DEFER TRAINING
RSVD#D24 RSVD#AJ32
1
M_VREF_CA_DIMM0 R707 1 DY 2 0R2J-2-GP G25 AK32
2
RSVD#G25 RSVD#AK32 R705

G24 RSVD#G24 1: PEG Train immediately following xxRESETB de assertion
R706 1 2 0R2J-2-GP 1KR2J-1-GP CFG7
M_VREF_CA_DIMM1 DY E23 RSVD#E23 DY
D23 0: PEG Wait for BIOS for training
RSVD#D23
C30 AH27
2
RSVD#C30 RSVD#AH27
A31 RSVD#A31
B30 RSVD#B30
B29 0702 Modify
RSVD#B29
D30 RSVD#D30 RSVD#AN35 AN35 TP713 1
B31 AM35 TP714 1 TP713 TPAD14-GP 0630 Modify:
20 mils A30
RSVD#B31 RSVD#AM35 TP714 TPAD14-GP Removed CLK_XDP_ITP_P&N
0629 Modify: RSVD#A30 and reserved TP713,TP714.
C29 RSVD#C29
Reserved R710 0ohm to GND to
follow EV board schematic.
J20 RSVD#J20
B18 RSVD#B18 RSVD#AT2 AT2
R710 1 DY 2 0R2J-2-GP H_VCCP_SEL A19 AT1
RSVD#A19 RSVD#AT1
RSVD#AR1 AR1
J15 RSVD#J15
1D05V_VTT
B B
1
DY
SCD1U50V3KX-GP
2
EC701
SANDY SKT-BGA989C470395-1H180
0719 Modify:
62.10055.421
Reserved EC701 0.1uF near 2nd = 62.10040.771
A00 0103 add 3rd foxcon CPU1 at XBuild batch run
R711(BOTTOM) for EMC NEO suggestion. 3rd = 62.10055.321
<Variant Name>
A A
Wistron Corporation
Title
CPU (RESERVED)
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CPU1F POWER 6 OF 9
VCCIO Output Decoupling Recommendation:
2 x 330 uF (3 x 330 uF for 2012 capable designs)
5 x 22 uF & 5 x 0805 no-stuff at Bottom
VCC_CORE SANDY 7 x 22 uF & 2 x 0805 no-stuff at Top
1D05V_VTT
AG35 VCC PROCESSOR VCCIO: 8.5A
AG34 VCC VCCIO AH13
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
AG33 VCC VCCIO AH10
C805
C808
C809
C838
C839
C840
C841
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
D AG32 VCC VCCIO AG10 D
1
AG31 VCC VCCIO AC10
AG30 VCC VCCIO Y10
QC DY
AG29 U10
2
VCC VCCIO
AG28 VCC VCCIO P10
AG27 VCC VCCIO L10
AG26 VCC VCCIO J14
AF35 VCC VCCIO J13
AF34 VCC VCCIO J12
AF33 VCC VCCIO J11
AF32 H14 0713 Modify:
VCC VCCIO Removed C810,C806,C807 10uf 0603 cap
AF31 VCC VCCIO H12
AF30 H11 base on layout limitation.
VCC VCCIO
AF29 VCC VCCIO G14
1115 X02 Modify: AF28 G13
VCC VCCIO
PEG AND DDR

Reserved C802~C804,C806,C807 10uF 0603 AF27 G12
for power team fine tune Vcore quality. VCC VCCIO
PROCESSOR CORE POWER AF26 VCC VCCIO F14
VCC_CORE
AD35 VCC VCCIO F13 No-stuff sites outside the socket may be removed.
53A X02 1115 AD34
AD33
VCC VCCIO F12
F11
No-stuff sites inside the socket cavity need to remain.
VCC VCCIO
AD32 VCC VCCIO E14
AD31 E12 1D05V_VTT
VCC VCCIO
AD30 VCC
C801
C802
C803
C804
C806
C807
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
AD29 VCC VCCIO E11
1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
AD28 VCC VCCIO D14
C829
C830
C842
C843
C844
C845
QC QC QC QC QC QC AD27 VCC VCCIO D13
1
AD26 D12 0617 Modify:
2
VCC VCCIO
AC35 VCC VCCIO D11 Joseph Removed C812,
AC34 C14
2
VCC VCCIO C813,C814
AC33 VCC VCCIO C13
AC32 VCC VCCIO C12
C AC31 VCC VCCIO C11 C
0713 Modify: AC30 B14
Removed C802,C811 10uf 0603 VCC VCCIO
AC29 VCC VCCIO B12
cap base on layout limitation. AC28 A14
VCC VCCIO
AC27 VCC VCCIO A13
C820
C819
C817
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
AC26 VCC VCCIO A12

1
AA35 VCC VCCIO A11

0819 De-cap DY DY QC AA34 VCC
AA33 J23
2
VCC VCCIO
AA32 VCC
AA31 VCC
AA30 VCC
AA29 VCC
0713 Modify: AA28
Removed C818 10uf 0603 cap 0726 Modify: VCC
AA27 VCC
base on layout limitation. un-stuff C826.
SC22U6D3V5MX-L2GP
AA26 VCC
CORE SUPPLY
SC22U6D3V5MX-2GP
Y35 VCC
For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7 1D05V_VTT
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
Y34 VCC
C816
C821
C825
Y33 VCC For CRB VIDALERT# need to pull high 75 ohm close to CPU
1
1
C826
Y32 VCC
C827
Y31 VCC
Y30 H_CPU_SVIDDAT R804 1 2 130R2F-1-GP
2
VCC
Y29 VCC
Y28 VCC
0721 Modify: Y27 20100610 V1.0
Removed C822,C823,C824 0819 De-cap VCC 0705 Modify:
Y26 VCC
V35 Removed R805,R806, already PH closed PWM side.
VCC
SVID
0721 Modify: V34 AJ29 H_CPU_SVIDALRT# R803 1 2 43R2J-GP
VCC VIDALERT# VR_SVID_ALERT# 42
Removed C836. H_CPU_SVIDCLK
SC22U6D3V5MX-L2GP
V33 VCC VIDSCLK AJ30 H_CPU_SVIDCLK 42

H_CPU_SVIDDAT
SC22U6D3V5MX-2GP
V32 VCC VIDSOUT AJ28 H_CPU_SVIDDAT 42

SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
V31 VCC
C835
C834
C833
C832
B V30 VCC B
1
1
C837
V29 VCC
C831
V28 VCC
V27
2
0819 De-cap VCC

V26 VCC
U35 VCC
U34 VCC
U33 VCC
0726 Modify: U32
un-stuff C837. VCC
VCC Output Decoupling Recommendation: U31 VCC
4 x 470 uF at Bottom Socket Edge U30 VCC
U29
8 x 22 uF at Top Socket Cavity U28
VCC
8 x 22 uF at Top Socket Edge VCC
U27 VCC
8 x 22 uF at Bottom Socket Cavity U26 VCC
R35 VCC_CORE
VCC
R34 VCC
R33 VCC
1
R32 VCC
R31 R801
VCC 100R2F-L1-GP-U
R30 VCC
R29 VCC
SENSE LINES
R28
2
VCC
R27 VCC VCC_SENSE AJ35 VCCSENSE 42
R26 VCC VSS_SENSE AJ34 VSSSENSE 42
P35 VCC
1
P34 VCC
P33 R802
VCC 100R2F-L1-GP-U
P32 VCC VCCIO_SENSE B10 VCCIO_SENSE 45
P31 VCC VSSIO_SENSE A10 VSSIO_SENSE 45
P30
2
VCC
A P29 VCC A
P28 VCC <Core Design>
P27 VCC
P26 VCC
Wistron Corporation
Title
CPU (VCC_CORE)
SANDY Size Document Number Rev
Custom
62.10055.421 3rd = 62.10055.321 A00 0103 add 3rd foxcon CPU1 at XBuild batch run QUEEN 15 A00
2nd = 62.10040.771 Date: Tuesday, January 04, 2011 Sheet 8 of 108
5 4 3 2 1
5 4 3 2 1
VAXG Output Decoupling Recommendation:

SSID = CPU 2 x 470 uF at Bottom Socket Edge
2 x 22 uF at Top Socket Cavity VCC_GFXCORE
4 x 22 uF at Top Socket Edge
2 x 22 uF at Bottom Socket Cavity
4 x 22 uF at Bottom Socket Edge
POWER
1
0726 Modify:
VCC_GFXCORE un-stuff C906. R906
CPU1G 7 OF 9 100R2F-L1-GP-U
0721 Modify:
Removed C903 PROCESSOR VAXG: 33A
2
SENSE
LINES
AT24 AK35 VCC_AXG_SENSE 42 VCC_AXG_SENSE
VAXG VAXG_SENSE VSS_AXG_SENSE
AT23 AK34
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
D VSS_AXG_SENSE 42 D
VAXG VSSAXG_SENSE
C901
C902
C904
C905
C906
AT21 VAXG SANDY
1
AT20 VAXG
DY AT18 Refer to the latest Huron River Mainstream PDG R907
VAXG 100R2F-L1-GP-U
AT17 (Doc# 436735) for more details on S3 power
2
VAXG
AR24 VAXG reduction implementation.
AR23
2
VAXG
AR21 VAXG
AR20 VAXG
+V_SM_VREF_CNT should have 10 mil trace width
VREF
AR18 VAXG
0624 Modify: AR17 VAXG 20100609 V1.0
AP24 AL1 +V_SM_VREF_CNT
Removed C918,C919 10uF 0603 for VCC_GFXCORE. VAXG SM_VREF +V_SM_VREF_CNT 37
AP23 VAXG
AP21 VAXG
AP20 0719 Modify:
VAXG Add C907,C918,C919,C925 0402 0.1 uF stitching
AP18 VAXG capacitors between 1D5V_S3 & 1D5V_S0 based on
C920
C921
AP17
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC4D7U6D3V3KX-GP
VAXG
1
Intel's review
C908
AN24 VAXG
Routing Guideline:
DY DY AN23 VAXG Power from DDR_VREF_S3 and +V_SM_VREF_CNT
2 AN21 1D5V_S0
2
AN20
VAXG should have 10 mils trace width.
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VAXG
DDR3 -1.5V RAILS

AN18 VAXG
0713 Modify: AN17 VAXG PROCESSOR VDDQ: 10A
GRAPHICS
Removed C907 10uf 0603 cap. AM24 AF7
0726 Modify: VAXG VDDQ
AM23 AF4
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
stuff C908 10uF. VAXG VDDQ 1D5V_S3
C909
C910
C911
C912
C913
C914
AM21 AF1
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
VAXG VDDQ
1
C907
C918
C919
C925
AM20 AC7 TC901 DY DY DY DY
0818 VAXG VDDQ
AM18 VAXG VDDQ AC4 DY DY DY
De-cap AM17 AC1
2
C VAXG VDDQ C
AL24 VAXG VDDQ Y7
AL23 VAXG VDDQ Y4
AL21 Y1 ST330U2VDM-4-GP
VAXG VDDQ
AL20 U7
AL18
VAXG VDDQ
U4
79.33719.20L
2nd = 77.C3371.13L
VAXG VDDQ
AL17 VAXG VDDQ U1 VDDQ Output Decoupling Recommendation:
AK24 VAXG VDDQ P7 1 x 330 uF
AK23 P4
AK21
VAXG VDDQ
P1 0D85V_S0 6 x 10 uF
Removed DIS_ONLY Disable Resistor. AK20
VAXG
VAXG
VDDQ
AK18 PROCESSOR VCCSA: 6A 0617 Modify:
R904,R905,R901,R903 AK17
VAXG
VAXG Joseph Removed TC902,TC903 330uF cap.
AJ24
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VAXG 0719 Modify:
C916
C915
C917
AJ23 VAXG
1
AJ21 VAXG
Reserved EC902 0.1uF near
AJ20
DY
SCD1U50V3KX-GP
VAXG C917 for EMC NEO suggestion.
AJ18
2
VAXG
EC902
AJ17 VAXG
AH24
SA RAIL
VAXG
AH23 VAXG
AH21 VAXG VCCSA M27 VCCSA Output Decoupling Recommendation:
AH20 VAXG VCCSA M26 1 x 330 uF
AH18 L26
Disabling Guidelines for External Graphics Designs: AH17
VAXG VCCSA
J26
2 x 10 uF at Bottom Socket Cavity
VAXG VCCSA 1 x 10 uF at Bottom Socket Edge
Can connect to GND if motherboard only supports external VCCSA J25
J24
graphics and if GFX VR is not stuffed. VCCSA
H26 0624 Modify:
Can be left floating (Gfx VR keeps VAXG rail from floating) VCCSA Removed R902 10ohm closed CPU side.
VCCSA H25
if the VR is stuffed 0713 Modify:
1.8V RAIL
B Add R908 100ohm PH to 0D85V_S0. B
0714 Modify:
1D8V_S0 Removed R908 PH.
PROCESSOR VCCPLL: 1.2A VCCUSA_SENSE

B6 VCCPLL VCCSA_SENSE H23 VCCUSA_SENSE 48
MISC
A6
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U6D3V5KX-1GP
VCCPLL
C923
C922
C924
A2 VCCPLL
1
C22 H_FC_C22
FC_C22 VCCSA_SEL H_FC_C22 48 DCBATOUT
C24
2
VCCSA_VID1 VCCSA_SEL 48
4
3
EC901
SCD1U50V3KX-GP
0617 Modify: SANDY
1
RN901
Joseph Removed TC902, 62.10055.421 SRN1KJ-7-GP
TC903 330uF cap. 2nd = 62.10040.771 0714 Modify:
2
RN901 change to 1K PL from 10K
3rd = 62.10055.321
1
2
A00 0103 add 3rd foxcon CPU1 at XBuild batch run base on Intel PDDG updated.
VCCPLL Output Decoupling Recommendation:

1 x 330 uF
2 x 1 uF 1122 X02 Modify:
1 x 10 uF stuff EC901 0.1uF from
EMC Neo suggestion.
A <Core Design> A
Wistron Corporation
Title
CPU (VCC_GFXCORE)
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CPU1H 8 OF 9 CPU1I 9 OF 9
AT35 VSS VSS AJ22

AT32 VSS VSS AJ19
AT29 VSS VSS AJ16 T35 VSS SANDY VSS F22
AT27 VSS VSS AJ13 T34 VSS VSS F19
AT25 VSS VSS AJ10 T33 VSS VSS E30
D AT19 VSS VSS AJ4 T31 VSS VSS E24 D
AT13 VSS SANDY VSS AJ2 T29 VSS VSS E18
AT7 VSS VSS AH35 T27 VSS VSS E13
AT4 VSS VSS AH34 T26 VSS VSS E10
AT3 VSS VSS AH32 P9 VSS VSS E9
AR25 VSS VSS AH30 P8 VSS VSS E8
AR10 VSS VSS AH22 N35 VSS VSS E3
AR2 VSS VSS AH7 N32 VSS VSS D35
AP34 VSS VSS AH4 N31 VSS VSS D32
AP31 VSS VSS AG9 N30 VSS VSS D29
AP22 VSS VSS AF6 N27 VSS VSS D17
AP19 VSS VSS AF5 N26 VSS VSS C34
AP16 VSS VSS AF3 M34 VSS VSS C31
AP13 VSS VSS AF2 L33 VSS VSS C28
AP10 VSS VSS AE35 L30 VSS VSS C27
AN30 VSS VSS AE31 L6 VSS VSS C1
C AN27 AE30 L5 B22 C
VSS VSS VSS VSS
AN25 AE29 L4 B19
AN22
AN19
VSS
VSS
VSS
VSS VSS
VSS
VSS
AE28
AE27
L3
L2
VSS
VSS
VSS
VSS VSS
VSS
VSS
B17
B15
AN16 VSS VSS AE26 L1 VSS VSS B13
AN13 VSS VSS AE9 K35 VSS VSS B11
AN10 VSS VSS AD7 K32 VSS VSS B9
AN7 VSS VSS AC9 K29 VSS VSS B8
AN4 VSS VSS AC8 K26 VSS VSS B7
AM29 VSS VSS AC6 J34 VSS VSS B5
AM25 VSS VSS AC5 J31 VSS VSS B3
AM22 VSS VSS AC3 H33 VSS VSS B2
AM19 VSS VSS AC2 H30 VSS VSS A35
AM16 VSS VSS AB35 H27 VSS VSS A32
AM2 VSS VSS AB29 H10 VSS
AM1 VSS VSS AB28 H9 VSS
AL34 VSS VSS AB27 H8 VSS
AL31 VSS VSS AB26 H7 VSS
AL28 VSS VSS Y9 H6 VSS
B B
AL10 VSS VSS W35 G35 VSS
AK33 VSS VSS W31 G23 VSS
AK22 VSS VSS W27 F34 VSS
AK19 VSS VSS W26 F31 VSS
AK16 VSS VSS U9 F29 VSS
AK13 VSS VSS U8
AK10 VSS VSS U6
AK7 VSS VSS U5
AK4 VSS VSS U3
AJ25 VSS VSS U2
SANDY SANDY
62.10055.421 62.10055.421
2nd = 62.10040.771 2nd = 62.10040.771
3rd = 63.10055.321 A00 0103 add 3rd foxcon CPU1 at XBuild batch run 3rd = 62.10055.321 A00 0103 add 3rd foxcon CPU1 at XBuild batch run
A <Variant Name> A
Wistron Corporation
Title
CPU (VSS)
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
XDP
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
0624 Modify:
DM2 SWAP DM1 and DM2 location.
SSID = MEMORY M_B_A0 98 A0 NP1 NP1 3D3V_S0
M_B_A1 97 NP2
M_B_A2 A1 NP2
0617 Modify: M_B_A[15:0] 6 96 A2
M_B_A3 95 110
Joseph Change M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, A3 RAS# M_B_RAS# 6
1
DDR_VREF_S3 M_B_A4 92 113
M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 A4 WE# M_B_WE# 6
M_B_A5 91 115 R1402
A5 CAS# M_B_CAS# 6
from net to power. M_B_A6 90 10KR2J-3-GP Note:
1
M_B_A7 A6
86 A7 CS0# 114 M_B_DIM0_CS#0 6
R1405 M_B_A8 89 121 M_B_DIM0_CS#1 6
If SA0 DIM0 = 0, SA1_DIM0 = 0
2
A00 0R0402-PAD-2-GP M_B_A9 A8 CS1#
85 A9 SO-DIMMA SPD Address is 0xA0
M_B_A10
M_VREF_CA_DIMM1 M_B_A11
107
84
A10/AP CKE0
73
74
M_B_DIM0_CKE0 6 0825 SO-DIMMA TS Address is 0x30
M_B_DIM0_CKE1 6
2
M_B_A12 A11 CKE1 SA1_DIM1

83
D M_B_A13 A12 D
119 101 M_B_DIM0_CLK_DDR0 6
M_B_A14 A13 CK0 SA0_DIM1 If SA0 DIM0 = 1, SA1_DIM0 = 0
80 103 M_B_DIM0_CLK_DDR#0 6
M_B_A15 A14 CK0#
78 SO-DIMMA SPD Address is 0xA2
A15
1
1
79 102 M_B_DIM0_CLK_DDR1 6
6 M_B_BS2 A16/BA2 CK1
1
C1423
DY C1425 C1424
CK1#
104 M_B_DIM0_CLK_DDR#1 6 SO-DIMMA TS Address is 0x32
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
109 R1401
2
2 6 M_B_BS0 BA0
108 11 10KR2J-3-GP
6 M_B_BS1 BA1 DM0
6 M_B_DQ[63:0] 28
M_B_DQ0 DM1
5 46
2
M_B_DQ1 DQ0 DM2
7 63
M_B_DQ2 DQ1 DM3
15 136
M_B_DQ3 DQ2 DM4
0617 Modify: 17 DQ3 DM5 153
M_B_DQ4 4 170
Joseph Change M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, M_B_DQ5 DQ4 DM6
6 DQ5 DM7 187
M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 M_B_DQ6 16
DDR_VREF_S3 from net to power. M_B_DQ7 DQ6
18 DQ7 SDA 200 PCH_SMBDATA 15,20,79,82
M_B_DQ8 21 202
M_B_DQ9 23
DQ8
DQ9
SCL PCH_SMBCLK 15,20,79,82 Thermal EVENT
1
M_B_DQ10 33 198 3D3V_S0

DQ10 EVENT# TS#_DIMM0_1 15 3D3V_S0
A00 R1404 M_B_DQ11 35
0R0402-PAD-2-GP M_B_DQ12 DQ11
22 DQ12 VDDSPD 199
M_B_DQ13 24 TS#_DIMM0_1 1R1403 2
M_VREF_DQ_DIMM1 M_B_DQ14 DQ13 SA0_DIM1 10KR2J-3-GP
34 197
2
DQ14 SA0
1
M_B_DQ15 36 201 SA1_DIM1 C1401 C1402
M_B_DQ16 DQ15 SA1
39 DQ16 DY
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
M_B_DQ17 41 77
2
M_B_DQ18 DQ17 NC#1
51 DQ18 NC#2 122
1
M_B_DQ19 53 125 1D5V_S3

C1411 C1412 C1413 M_B_DQ20 DQ19 NC#/TEST
40
DY DQ20
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
M_B_DQ21 42 75
2
M_B_DQ22 DQ21 VDD1

50 DQ22 VDD2 76
M_B_DQ23 52 81
C M_B_DQ24 DQ23 VDD3 C
57 DQ24 VDD4 82
M_B_DQ25 1D5V_S3
M_B_DQ26
59 DQ25 VDD5 87 SODIMM A DECOUPLING
67 DQ26 VDD6 88
M_B_DQ27 69 93 0617 Modify:
M_B_DQ28 DQ27 VDD7
56 DQ28 VDD8 94 Joseph dummy TC1401 default un-stuff.
M_B_DQ29 58 99
DQ29 VDD9
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
0707 Modify: M_B_DQ30
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
68 DQ30 VDD10 100
C1403
C1405
C1406
C1407
C1408
C1409
C1410
Change R1404,R1405 to 0ohm 0402 from short pad. M_B_DQ31 70 105
DQ31 VDD11
1
ST330U2VDM-4-GP
M_B_DQ32 129 106 TC1401
DQ32 VDD12
C1404
M_B_DQ33 131 111
M_B_DQ34 141
DQ33 VDD13
112
DY DY DY DY DY DY DY
2
M_B_DQ35 DQ34 VDD14
143 117
M_B_DQ36 DQ35 VDD15
130 118
M_B_DQ37 DQ36 VDD16
132 123
M_B_DQ38 DQ37 VDD17 0818
140 124
M_B_DQ39 DQ38 VDD18 De-cap
142
M_B_DQ40 DQ39
147 2
M_B_DQ41 DQ40 VSS
149 3
DQ41 VSS
SCD1U10V2KX-5GP
M_B_DQ42 157 8
DQ42 VSS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C1414
M_B_DQ43 159 9
DQ43 VSS
1
M_B_DQ44 146 13 Layout Note:
DQ44 VSS
C1415
C1416
C1417
Place these caps M_B_DQ45 148 14
0D75V_S0 M_B_DQ46 DQ45 VSS Place these Caps near
158 19
2
close to VTT1 and M_B_DQ47 DQ46 VSS
M_B_DQ48
160
DQ47 VSS
20 SO-DIMMA.
VTT2. 163 25
M_B_DQ49 DQ48 VSS
165 26
M_B_DQ50 DQ49 VSS
175 31
DQ50 VSS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
M_B_DQ51 177 32 0818

DQ51 VSS
C1419
C1420
C1421
C1422
M_B_DQ52 164 37 De-cap

DQ52 VSS
1
M_B_DQ53 166 38
C1418 M_B_DQ54 DQ53 VSS
174 43
DY DY DY DQ54 VSS
SC10U6D3V5KX-1GP
M_B_DQ55 176 44
2
B M_B_DQ56 DQ55 VSS B

181 48
M_B_DQ57 DQ56 VSS
183 49
M_B_DQ58 DQ57 VSS
191 54
M_B_DQ59 DQ58 VSS
193 55
M_B_DQ60 DQ59 VSS
180 60
M_B_DQ61 DQ60 VSS
182 61
M_B_DQ62 DQ61 VSS
192 65
M_B_DQ63 DQ62 VSS
194 66
DQ63 VSS
71
M_B_DQS#0 VSS
10 72
M_B_DQS#1 DQS0# VSS
27 127
M_B_DQS#2 DQS1# VSS
45 128
M_B_DQS#3 DQS2# VSS
62 133
M_B_DQS#4 DQS3# VSS
135 134
M_B_DQS#5 152
DQS4# VSS
138
PART NUMBER Height TYPE
M_B_DQS#6 DQS5# VSS
169 139
M_B_DQS#7 DQS6# VSS
186 144
DQS7# VSS
145
62.10017.P61 5.2mm REVERSED
M_B_DQS0 VSS
12 150
M_B_DQS1 DQS0 VSS
M_B_DQS#[7:0] 6 29 151
M_B_DQS2 DQS1 VSS
47 155
M_B_DQS[7:0] 6
M_B_DQS3 64
DQS2 VSS
156
62.10017.N41(2nd) 5.2mm REVERSED
M_B_DQS4 DQS3 VSS
137 161
M_B_DQS5 DQS4 VSS
154 162
M_B_DQS6 DQS5 VSS
171 167
M_B_DQS7 188
DQS6 VSS
168
62.10017.P41(3rd) 5.2mm REVERSED
DQS7 VSS
172
VSS
116 173
6 M_B_DIM0_ODT0 ODT0 VSS
120 178
6 M_B_DIM0_ODT1 ODT1 VSS
179
62.10024.E21(4th) 5.2mm REVERSED
VSS
M_VREF_CA_DIMM1 126 184
VREF_CA VSS
M_VREF_DQ_DIMM1 1 VREF_DQ VSS 185
A A
VSS 189
30 RESET# VSS 190 <Variant Name>
15,37 DDR3_DRAMRST# 1110 X02 Modify:
VSS 195
196 DM2 1st change to 62.10017.P61; 2nd change
VSS to 62.10017.N41 on ST stage from ME updated
0617 Modify:
0D75V_S0 203
204
VTT1
VTT2
VSS
VSS
205
206 connector list. Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Joseph Change M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, Taipei Hsien 221, Taiwan, R.O.C.
M_VREF_CA_DIMM0,M_VREF_CA_DIMM1
H =5.2mm Title
from net to power. DDR3-204P-48-GP
62.10017.P61 DDR3-SODIMM2
2nd = 62.10017.N41 Size Document Number Rev
Custom
3rd = 62.10017.P41
4th = 62.10024.E21 QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
0624 Modify:
SWAP DM1 and DM2 location.
SSID = MEMORY DM1 SA1_DIM0
SA0_DIM0 20101220 R1501 R1502 for change to parallel resistor
M_A_A0 98 NP1
M_A_A1 A0 NP1
97 A1 NP2 NP2
M_A_A[15:0] 6 M_A_A2 96 A2
3
4
M_A_A3 95 110
A3 RAS# M_A_RAS# 6
M_A_A4 92 113 RN1501
A4 WE# M_A_WE# 6
M_A_A5 91 115 M_A_CAS# 6 SRN10KJ-5-GP
M_A_A6 A5 CAS#
90 A6
M_A_A7 86 114 M_A_DIM0_CS#0 6
A00
M_A_A8 A7 CS0#
89 121 M_A_DIM0_CS#1 6
2
1
M_A_A9 A8 CS1#
85
M_A_A10 A9
M_A_A11
107
A10/AP CKE0
73 M_A_DIM0_CKE0 6 Note:
84 74 M_A_DIM0_CKE1 6
D M_A_A12 A11 CKE1 SO-DIMMB SPD Address is 0xA4 D
83
M_A_A13 A12
119 101 M_A_DIM0_CLK_DDR0 6 SO-DIMMB TS Address is 0x34
M_A_A14 A13 CK0
80 103 M_A_DIM0_CLK_DDR#0 6
M_A_A15 A14 CK0#
78
A15
79 102 M_A_DIM0_CLK_DDR1 6
0707 Modify: 6 M_A_BS2 A16/BA2 CK1
Change R1503,R1504 to 0ohm 0402 from short pad. CK1#
104 M_A_DIM0_CLK_DDR#1 6 SO-DIMMB is placed farther from
109
6 M_A_BS0 BA0 the Processor than SO-DIMMA
108 11
6 M_A_BS1 BA1 DM0
6 M_A_DQ[63:0] 28
M_A_DQ0 DM1
5 46
DDR_VREF_S3 M_A_DQ1 DQ0 DM2
7 63
M_A_DQ2 DQ1 DM3
0617 Modify: 15 DQ2 DM4 136
M_A_DQ3 17 153
Joseph Change M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, M_A_DQ4 DQ3 DM5
4 DQ4 DM6 170
1
M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 M_A_DQ5 6 187

A00 R1504 from net to power. M_A_DQ6 DQ5 DM7
16 DQ6
0R0402-PAD-2-GP M_A_DQ7 18 200
M_A_DQ8 DQ7 SDA PCH_SMBDATA 14,20,79,82
21 DQ8 SCL 202 PCH_SMBCLK 14,20,79,82
M_VREF_CA_DIMM0 M_A_DQ9 23
2
M_A_DQ10 DQ9 3D3V_S0

33 DQ10 EVENT# 198 TS#_DIMM0_1 14
M_A_DQ11 35
M_A_DQ12 DQ11
22 DQ12 VDDSPD 199
M_A_DQ13 24 DQ13
1
1
M_A_DQ14 34 197 SA0_DIM0
C1523 C1524 C1522 M_A_DQ15 36
DQ14 SA0
201 SA1_DIM0 DY C1501 C1502
DY DQ15 SA1
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
M_A_DQ16 39
2
2
M_A_DQ17 DQ16
41 DQ17 NC#1 77
M_A_DQ18 51 122
M_A_DQ19 DQ18 NC#2 1D5V_S3
53 DQ19 NC#/TEST 125
M_A_DQ20 40
M_A_DQ21 DQ20
42 DQ21 VDD1 75
M_A_DQ22 50 76
C M_A_DQ23 DQ22 VDD2 C
52 DQ23 VDD3 81
M_A_DQ24 57 82
M_A_DQ25 DQ24 VDD4
59 DQ25 VDD5 87
M_A_DQ26 67 88
DDR_VREF_S3 M_A_DQ27 DQ26 VDD6
69 DQ27 VDD7 93
0617 Modify: M_A_DQ28 56 94
M_A_DQ29 DQ28 VDD8
Joseph Change M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, 58 DQ29 VDD9 99
M_A_DQ30 68 100
M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 DQ30 VDD10
1
M_A_DQ31 70 105 1D5V_S3

R1503 from net to power. M_A_DQ32 DQ31 VDD11
A00 0R0402-PAD-2-GP M_A_DQ33
129
DQ32 VDD12
106 SODIMM B DECOUPLING
131 111
M_A_DQ34 DQ33 VDD13
141 112
M_VREF_DQ_DIMM0 M_A_DQ35 DQ34 VDD14
143 117
2
DQ35 VDD15
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
M_A_DQ36
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
130 118
DQ36 VDD16
SC22U6D3V5MX-2GP
C1503
C1504
C1506
C1507
C1508
C1509
C1510
M_A_DQ37 132 123
DQ37 VDD17
1
M_A_DQ38 140 124
DQ38 VDD18
C1505
M_A_DQ39 142 DY DY
DQ39 DY DY DY DY
1
M_A_DQ40 147 2
2
C1515 C1516 C1517 M_A_DQ41 DQ40 VSS
149 3
DY DQ41 VSS
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
M_A_DQ42 157 8
2
M_A_DQ43 DQ42 VSS

159 9
M_A_DQ44 DQ43 VSS 0818
146 13
M_A_DQ45 DQ44 VSS De-cap
148 14
M_A_DQ46 DQ45 VSS
158 19
M_A_DQ47 DQ46 VSS
160 20
DQ47 VSS
SCD1U10V2KX-5GP
M_A_DQ48 163 25
DQ48 VSS
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SC1U6D3V2KX-GP
C1512
M_A_DQ49 165 26
DQ49 VSS
1
M_A_DQ50 175 31 Layout Note:
DQ50 VSS
C1511
C1513
C1514
M_A_DQ51 177 32 DY
M_A_DQ52 DQ51 VSS Place these Caps near
164 37
2
M_A_DQ53 DQ52 VSS
166 38 SO-DIMMB.
M_A_DQ54 DQ53 VSS
174 43
B M_A_DQ55 DQ54 VSS 0818 B
Place these caps M_A_DQ56
176
DQ55 VSS
44
De-cap
181 48
0D75V_S0 close to VTT1 and M_A_DQ57 DQ56 VSS
183 49
M_A_DQ58 DQ57 VSS
VTT2. 191 54
M_A_DQ59 DQ58 VSS
193 55
M_A_DQ60 DQ59 VSS
180 60
M_A_DQ61 DQ60 VSS
182 61
DQ61 VSS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C1518
C1519
C1520
C1521
M_A_DQ62 192 65
DQ62 VSS
1
M_A_DQ63 194 66
DQ63 VSS
71
DY DY M_A_DQS#0 10
VSS
72
2
M_A_DQS#1 DQS0# VSS

27 127
M_A_DQS#2 DQS1# VSS
45 128
M_A_DQS#3 DQS2# VSS
62 133
M_A_DQS#4 DQS3# VSS
135 134
M_A_DQS#5 DQS4# VSS
152 138
M_A_DQS#6 DQS5# VSS
M_A_DQS#[7:0] 6 169 139
M_A_DQS#7 DQS6# VSS
186 144
M_A_DQS[7:0] 6
DQS7# VSS
145
PART NUMBER Height TYPE
M_A_DQS0 VSS
12 150
M_A_DQS1 DQS0 VSS
29 151
M_A_DQS2 47
DQS1 VSS
155
62.10017.Q41 9.2mm REVERSED
M_A_DQS3 DQS2 VSS
64 156
M_A_DQS4 DQS3 VSS
137 161
M_A_DQS5 DQS4 VSS
154 162
M_A_DQS6 171
DQS5 VSS
167
62.10017.N11(2nd) 9.2mm REVERSED
M_A_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
VSS
116 173
6 M_A_DIM0_ODT0
120
ODT0 VSS
178
62.10017.N61(3rd) 9.2mm REVERSED
6 M_A_DIM0_ODT1 ODT1 VSS
179
VSS
M_VREF_CA_DIMM0 126 VREF_CA VSS 184
A A
1 185
M_VREF_DQ_DIMM0 VREF_DQ VSS
189
62.10024.D91(4th) 9.2mm REVERSED
VSS <Variant Name>
30 RESET# VSS 190
14,37 DDR3_DRAMRST#
VSS 195
1110 X02 Modify:
0617 Modify: 0D75V_S0 203 VTT1
VSS
VSS
196
205 DM1 1st change to 62.10017.Q41; 2nd change Wistron Corporation
204 206 to 62.10017.N11 on ST stage from ME updated 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Joseph Change M_VREF_DQ_DIMM0,M_VREF_DQ_DIMM1, VTT2 VSS connector list. Taipei Hsien 221, Taiwan, R.O.C.
M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 H =9.2mm
from net to power. Title
DDR3-204P-42-GP
62.10017.Q41 DDR3-SODIMM1
2nd = 62.10017.N11 Size Document Number Rev
Custom
3rd = 62.10017.N61
4th = 62.10024.D91 QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
3D3V_S0
RN1701 4 OF 10
PCH1D
1 4 L_CTRL_DATA 27 L_BKLT_EN J47 AP43
L_CTRL_CLK L_BKLTEN Cougar SDVO_TVCLKINN
2 3 49 LVDS_VDD_EN M45 L_VDD_EN SDVO_TVCLKINP AP45
SRN2K2J-1-GP 49 L_BKLT_CTRL P45 L_BKLTCTL

Point SDVO_STALLN AM42
L_DDC_DATA(PAGE17): LVDS_DDC_CLK_R SDVO_STALLP AM40
49 LVDS_DDC_CLK_R T40 L_DDC_CLK
This signal is on the LVDS interface. 49 LVDS_DDC_DATA_R LVDS_DDC_DATA_R K47 AP39
L_DDC_DATA SDVO_INTN
This signal needs to be left NC if eDP is SDVO_INTP AP40
RN1702 L_CTRL_CLK T45
L_BKLT_EN used for the local flat panel display L_CTRL_DATA L_CTRL_CLK
2 3 P39 L_CTRL_DATA
1 4 LVDS_VDD_EN
LVDS_IBG AF37 P38
LVD_IBG SDVO_CTRLCLK
RN
SRN100KJ-6-GP TPAD14-GP TP1701 1 LVDS_VBG AF36 M39
0923 SWAP LVD_VBG SDVO_CTRLDATA
1
4 1 LVDS_VREFH AE48
R1701 LVDS_VREFL LVD_VREFH
3 2 AE47 LVD_VREFL DDPB_AUXN AT49
2K37R2F-GP RN1704 0712 Modify: AT47
A00 0R4P2R-PAD SWAP RN1704 DDPB_AUXP
Place near PCH 49 LVDSA_CLK# AK39
DDPB_HPD AT40
0804 Remove HDMI from PCH.
LVDS
2
LVDSA_CLK#
49 LVDSA_CLK AK40 LVDSA_CLK DDPB_0N AV42
DDPB_0P AV40
49 LVDSA_DATA0# AN48 LVDSA_DATA#0 DDPB_1N AV45
C AM47 AV46 C
49 LVDSA_DATA1#
Digital Display Interface

LVDSA_DATA#1 DDPB_1P
49 LVDSA_DATA2# AK47 LVDSA_DATA#2 DDPB_2N AU48
AJ48 LVDSA_DATA#3 DDPB_2P AU47
DDPB_3N AV47
49 LVDSA_DATA0 AN47 LVDSA_DATA0 DDPB_3P AV49
49 LVDSA_DATA1 AM49 LVDSA_DATA1
49 LVDSA_DATA2 AK49 LVDSA_DATA2
Impedance:90 ohm AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
DDPC_CTRLDATA P42
AF40 LVDSB_CLK#
AF39 LVDSB_CLK DDPC_AUXN AP47
0617 Modify: DDPC_AUXP AP49
Joseph Removed LVDSB related net for AH45 LVDSB_DATA#0 DDPC_HPD AT38
AH47 LVDSB_DATA#1
single LVDS channel base on Dell updated spec. AF49 AY47
LVDSB_DATA#2 DDPC_0N
AF45 LVDSB_DATA#3 DDPC_0P AY49
DDPC_1N AY43
AH43 LVDSB_DATA0 DDPC_1P AY45
AH49 LVDSB_DATA1 DDPC_2N BA47
0917 X01 Modify: AF47 BA48
Add R1703~R1705 on RGB signal and reserved LVDSB_DATA2 DDPC_2P
Close to PCH side EC1701~EC1703 0.1u from EMC Neo suggestion.
AF43 LVDSB_DATA3 DDPC_3N BB47
DDPC_3P BB49
CRT_RED A00
CRT_BLUE 82 CRT_BLUE 1 2 CRT_BLUE_N48 N48 M43
CRT_GREEN R1703 0R0402-PAD-2-GP
CRT_GREEN_P49 CRT_BLUE DDPD_CTRLCLK
82 CRT_GREEN 1 2 P49 CRT_GREEN DDPD_CTRLDATA M36
82 CRT_RED R1704
1 0R0402-PAD-2-GP
2 CRT_RED_T49 T49
R1705 0R0402-PAD-2-GP CRT_RED
B B
AT45
CRT
0923 SWAP DDPD_AUXN
82 CRT_DDC_CLK T39 CRT_DDC_CLK DDPD_AUXP AT43
82 CRT_DDC_DATA M40 CRT_DDC_DATA DDPD_HPD BH41
5
6
7
8
RN1705 BB43
SRN150F-1-GP DDPD_0N
82 CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
82 CRT_VSYNC M49 CRT_VSYNC DDPD_1N BF44
DDPD_1P BE44
BF42
4
3
2
1
DAC_IREF_R DDPD_2N
T43 DAC_IREF DDPD_2P BE42
T42 CRT_IRTN DDPD_3N BJ42
1
DDPD_3P BG42
R1702
1KR2D-1-GP COUGAR-GP-U2-NF
Notes:
2
CRT_BLUE
1K 0.5% 0402.
CRT_GREEN CHIP RES 1K D 1/16W 0402
CRT_RED
EC1701
SCD1U50V3KX-GP
EC1702
SCD1U50V3KX-GP
EC1703
SCD1U50V3KX-GP
1
DY DY DY
2
A <Variant Name> A
Wistron Corporation
Title
PCH (LVDS/CRT/DDI)
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
0719 Modify:
DF_TVS (NV_CLE) connect PROC_SELECT# (H_SNB_IVB#)
with R1808 2.2K5% pull up resistor to PCH VCCPNAND rail 1D8V_S0
SSID = PCH and a R1809 1K5% series resistor base on Intel
feedback.
1
PCH1E 5 OF 10
AY7 R1808
RSVD
Cougar RSVD AV7 2K2R2J-2-GP
BG26 TP1 RSVD AU3
BJ26 Point BG4 R1809
2
TP2 RSVD
BH25 TP3
0709 Modify: BJ16 AT10 NV_CLE 1 2
Removed INT_PIRQH# on RN1801 pin1. TP4 RSVD H_SNB_IVB# 5
BG16 BC8 1KR2J-1-GP
TP5 RSVD
D RN1801 AH38 D
TP6
1 10 3D3V_S0 AH37 TP7 RSVD AU2
INT_PIRQB# 2 9 INT_PIRQD# AK43 AT4 DMI & FDI Termination Voltage
INT_PIRQF# INT_PIRQE# TP8 RSVD
3 8 AK45 TP9 RSVD AT3
INT_PIRQA# 4 7 INT_PIRQC# C18 TP10 RSVD AT1 Set to Vss when LOW
3D3V_S0 5 6 INT_PIRQG# N30 AY3 NV_CLE
TP11 RSVD Set to Vcc when HIGH
H3 TP12 RSVD AT5
SRN8K2J-2-GP-U AH12 AV3
NVRAM
TP13 RSVD
AM4 TP14 RSVD AV1
AM5 TP15 RSVD BB1
Y13 TP16 RSVD BA3
K24 TP17 RSVD BB5
L24 TP18 RSVD BB3
AB46 TP19 RSVD BB7
AB45 BE8
RSVD
R1801 TP20 RSVD
2 1 4K7R2J-2-GP PCI_GNT3# BD4
DY RSVD
BF6
RSVD
B21 AV5 NV_ALE 1D8V_S0
TP21 RSVD NV_CLE
M20 TP22 DF_TVS AY1
AY16 TP23
1
A16 swap override Strap/Top-Block BG46 TP24 RSVD AV10 NV_RCOMP 1 TP1803 TPAD14-GP Danbury Technology:
Swap Override jumper Disabled when Low. R1810
AT8 1KR2J-1-GP
RSVD Enable when High. DY
PCI_GNT#3 Low = A16 swap BE28 AY5
2
TP25 RSVD
override/Top-Block RN1803 BC30 BA2
DGPU_HOLD_RST# TP26 RSVD NV_ALE
Swap Override enabled 1 4 BE32 TP27
DGPU_PW R_EN# 2 3 BJ32 AT12
C High = Default
BC28
TP28 RSVD
BF3
USB Ext. port 1 (HS) C
TP29 RSVD
SRN10KJ-5-GP BE30 TP30 External debug port use on Huron river platform
BF32
BG32
AV26
TP31
TP32
TP33
USBP0N
USBP0P
C24
A24
USB_PN0
USB_PP0
49
49
USB Table
BB26 TP34 USBP1N C25 USB_PN1 82
AU28 TP35 USBP1P B25 USB_PP1 82 Pair Device
AY30 TP36 USBP2N C26 USB_PN2 64
AU26 TP37 USBP2P A26 USB_PP2 64 0 Touch Panel / 3G SIM
1 2R1802 BBS_BIT1 AY26 K28
DY 1KR2J-1-GP AV28
TP38 USBP3N
H28
USB_PN3
USB_PP3
63
63 1 USB Ext. port 1 (HS)
TP39 USBP3P
1 2R1803 BBS_BIT0 AW30 E28
DY 1KR2J-1-GP BBS_BIT0 21 TP40 USBP4N
D28
USB_PN4
USB_PP4
82
82 2 Fingerprint
3D3V_S0 USBP4P
USBP5N C28 USB_PN5 32
USBP5P A28 USB_PP5 32 3 BLUETOOTH
USBP6N C29
2 USBP6P B29 4 Mini Card2 (WWAN)
BOOT BIOS Strap INT_PIRQA# K40 N28
R1814 INT_PIRQB# PIRQA# USBP7N
K38 M28 5 CARD READER
PCI
GNT1#/GPIO51 SATA1GP/GPIO19 BOOT BIOS Location INT_PIRQC# PIRQB# USBP7P
8K2R2J-3-GP H38 PIRQC# USBP8N L30 USB_PN8 57
INT_PIRQD# G38 K30 USB_PP8 57 6 X
PIRQD# USBP8P
0 0 LPC G30
1
USBP9N
C46 E30 7 X
USB
83 DGPU_HOLD_RST# REQ1#/GPIO50 USBP9P
0 1 Reserved TPAD14-GP TP1807 1 DGPU_SELECT# C44 C30
DGPU_PW R_EN# REQ2#/GPIO52 USBP10N
93 DGPU_PW R_EN# E40 REQ3#/GPIO54 USBP10P A30 8 USB Ext. port 4 / E-SATA /USB CHARGE
1 0 Reserved USBP11N L32 USB_PN11 82
BBS_BIT1 D47 K32 USB_PP11 82 9 USB Ext. port 2
GNT1#/GPIO51 USBP11P
1 1 SPI(Default) TPAD14-GP TP1806 1DGPU_PW M_SELECT# E42 GNT2#/GPIO53 USBP12N G32 USB_PN12 49
TPAD14-GP TP1801 1 PCI_GNT3# F46 E32 USB_PP12 49 10 USB Ext. port 3
B GNT3#/GPIO55 USBP12P B
USBP13N C32 USB_PN13 75
USBP13P A32 USB_PP13 75 11 Mini Card1 (WLAN)
79 HDD_FALL_INT1 1 R1812 0R0402-PAD
2 INT_PIRQE# G42
R1813 0R0402-PADINT_PIRQF# G40 PIRQE#/GPIO2
56 SATA_ODD_DA# 1 2 PIRQF#/GPIO3 12 CAMERA
82 USB30_SMI# 1 R1815 0R0402-PAD
2 INT_PIRQG# C42 C33 USB_RBIAS 1 2
R1817 0R0402-PADINT_PIRQH# D44 PIRQG#/GPIO4 USBRBIAS# R1811
69 KB_LED_BL_DET 1 2 PIRQH#/GPIO5 13 Express Card
22D6R2F-L1-GP
USBRBIAS B33
TPAD14-GP TP1802 1 PCI_PME# K10 PME# 1120 X02 Modify:
0709 Modify: PCI_PLTRST# C6 A14 USB_OC#0_1 Reserved USB_OC#0_1 connect from PCH GPIO59.
Add R1817 0ohm and connect to KB_LED_BL_DET. PLTRST# OC0#/GPIO59 USB_OC#0_1 61
K20 USB_OC#2_3
(5V Tolerance High Active) OC1#/GPIO40 USB_OC#4_5
OC2#/GPIO41 B17
71 CLK_PCI_LPC R1804 1 2 22R2J-2-GP CLK_PCI_LPC_R H49 C16 USB_OC#6_7
R1805 1 CLKOUT_PCI0 OC3#/GPIO42
20 CLK_PCI_FB 2 22R2J-2-GP CLK_PCI_FB_R H43 CLKOUT_PCI1 OC4#/GPIO43 L16 USB_OC#8_9 USB_OC#8_9 61
27 CLK_PCI_KBC R1806 1 2 22R2J-2-GP CLK_PCI_KBC_R J48 A16 USB_OC#10_11
CLKOUT_PCI2 OC5#/GPIO9 USB_OC#12_13
K42 CLKOUT_PCI3 OC6#/GPIO10 D14
H40 CLKOUT_PCI4 OC7#/GPIO14 C14 FFS_INT2_R 79
2
0617 Modify:
EC1802 EC1801 EC1803 0908
Joseph Remove PLT_RST AND COUGAR-GP-U2-NF
DY DY DY
SC10P50V2JN-4GP
1
1
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
gate logic IC U1801/C1802. 0628 Modify:

Add EC1803 4.7pF 0402 on CLK_PCI_LPC OC[3:0]# for Device 29 (Ports 0-7)
base on EMC NEO suggestion.
A00 0707 Modify: OC[7:4]# for Device 26 (Ports 8-13)
R1807 Change R1815,R1812,R1813 to 0ohm 0402
from short pad.
5,27,71,75,82,83 PLT_RST# 1 2 PCI_PLTRST#
0719 Modify:
Reserved TP on CLKOUT_PCI3,4 from vender feedback.
A 0R0402-PAD-2-GP <Variant Name> A
0908 X01 Modify: KBC CLK EMI RN1802

Wistron Corporation
1
USB_OC#2_3 1 10
R1816 Add R1818 10K PL on FFS_INT2_R(GPIO14) 2 9 USB_OC#12_13
3D3V_S5 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
0629 Modify: USB_OC#6_7 3 8 USB_OC#8_9 Taipei Hsien 221, Taiwan, R.O.C.
DY
100KR2J-1-GP
1
Reseved R1816 100K 0402 on PLT_RST#. R1818 10KR2J-3-GP USB_OC#0_1 4 7 USB_OC#10_11

C1801 1 2 FFS_INT2_R 5 6 USB_OC#4_5 Title
DY 3D3V_S5
2
SC220P50V2KX-3GP
PCH (PCI/USB/NVRAM)
2
SRN8K2J-2-GP-U
20100625 V1.2 Size Document Number Rev
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
SSID = PCH 4 DMI_RXN[3:0]

4 DMI_RXP[3:0] FDI_TXN[7:0] 4
FDI_TXP[7:0] 4
4 DMI_TXN[3:0]
4 DMI_TXP[3:0]
PCH1C 3 OF 10
BC24 BJ14
4
4
DMI_RXN0
DMI_RXN1 BE20
DMI0RXN Cougar FDI_RXN0
AY14
FDI_TXN0
FDI_TXN1
4
4
DMI1RXN FDI_RXN1
4 DMI_RXN2 BG18
BG20
DMI2RXN Point FDI_RXN2 BE14
BH13
FDI_TXN2 4
4 DMI_RXN3 DMI3RXN FDI_RXN3 FDI_TXN3 4
D Signal Routing Guideline: FDI_RXN4 BC12 FDI_TXN4 4 D
DMI_ZCOMP keep W=4 mils and 4 DMI_RXP0 BE24 DMI0RXP FDI_RXN5 BJ12 FDI_TXN5 4
4 DMI_RXP1 BC20 BG10 FDI_TXN6 4
routing length less than 500 BJ18
DMI1RXP FDI_RXN6
BG9
4 DMI_RXP2 DMI2RXP FDI_RXN7 FDI_TXN7 4
mils. 4 DMI_RXP3 BJ20 DMI3RXP
DMI_IRCOMP keep W=4 mils and FDI_RXP0 BG14 FDI_TXP0 4
routing length less than 500 4 DMI_TXN0 AW24 DMI0TXN FDI_RXP1 BB14 FDI_TXP1 4
4 DMI_TXN1 AW20 BF14 FDI_TXP2 4
mils. BB18
DMI1TXN FDI_RXP2
BG13
4 DMI_TXN2 DMI2TXN FDI_RXP3 FDI_TXP3 4
AV18 BE12
DMI
FDI
4 DMI_TXN3 DMI3TXN FDI_RXP4 FDI_TXP4 4
FDI_RXP5 BG12 FDI_TXP5 4
4 DMI_TXP0 AY24 DMI0TXP FDI_RXP6 BJ10 FDI_TXP6 4
4 DMI_TXP1 AY20 DMI1TXP FDI_RXP7 BH9 FDI_TXP7 4
4 DMI_TXP2 AY18 DMI2TXP
4 DMI_TXP3 AU18 DMI3TXP
FDI_INT AW16 FDI_INT 4
1D05V_VTT BJ24 AV12
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 4 For platforms not supporting Deep S4/S5
R1901 2 49D9R2F-GP DMI_COMP_R
1 BG25 DMI_IRCOMP FDI_FSYNC1 BC10 FDI_FSYNC1 4 1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)
R1902 1 2 750R2F-GP RBIAS_CPY BH21 DMI2RBIAS FDI_LSYNC0 AV14 FDI_LSYNC0 4 2.DPWROK and RSMRST# will rise at the same time (connected on board)
20100628 V1.3 0628 Modify:
Change R1904 to 100K 0402 from 10K and default stuff. FDI_LSYNC1 BB10 FDI_LSYNC1 4 3.SLP_SUS# and SUSACK# are left as no connect
0629 Modify:
R1926 connect to SYS_PWROK.
4.SUSWARN# used as SUSPWRDNACK/GPIO30
1 DY 2 R1926 SYS_PW ROK
10KR2J-3-GP 0707 Modify: A18 DSW ODVREN
Change R1903 change to 0ohm 0402 from short pad. DSWVRMEN
1 2 R1904 PW ROK
System Power Management

C 100KR2J-1-GP 1 R1910 2 0R0402-PAD PM_RSMRST# C
SUS_PW R_ACK 1 2 SUSACK# C12 E22 PCH_DPW ROK R1911 2 10KR2J-3-GP
0707 Modify: R1903 0R0402-PAD SUSACK# DPWROK DY1 RTC_AUX_S5
stuff R1925 and un-stuff R1905.
5 XDP_DBRESET# 1 2 SYS_RESET# K3 B9 PCH_W AKE# 27
R1925 0R0402-PAD SYS_RESET# WAKE#
1 2 R1905
36
3D3V_S0
SYS_PW ROK
DY 10KR2J-3-GP P12 N3
SYS_PWROK CLKRUN#/GPIO32 PM_CLKRUN# 27
1R1923 2
0R2J-2-GP
PW ROK
DY PM_SUS_STAT# TP1901 TPAD14-GP
27,36 S0_PW R_GOOD 1 2 L22 PWROK SUS_STAT#/GPIO61 G8 1
R1924 0R0402-PAD
1 R1906 2 0R0402-PAD
45,46,47,93 RUNPW ROK 1 R1907 2 MEPW ROK L10 APWROK SUSCLK/GPIO62 N14 SUS_CLK 1 R1913 2 0R0402-PAD PCH_SUSCLK_KBC 27
0R2J-2-GP DSWODVREN - On Die DSW VR Enable
DY
5,37 PM_DRAM_PW RGD B13 D10 PM_SLP_S5# 1 HIGH Enabled (DEFAULT)
DRAMPWROK SLP_S5#/GPIO63 TP1902 TPAD14-GP
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms
PM_RSMRST# C21 H4
LOW Disabled
RSMRST# SLP_S4# PM_SLP_S4# 27,46,75
27 SUS_PW R_ACK K16 SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# F4 PM_SLP_S3# 27,36,37,47,75 RTC_AUX_S5
27 PM_PW RBTN# E20 G10 PM_SLP_A# 1

PWRBTN# SLP_A# TP1903TPAD14-GP R1917 1 2 330KR2J-L1-GP
27,86 AC_PRESENT H20 G16 PM_SLP_SUS# 1

B ACPRESENT/GPIO31 SLP_SUS# TP1904TPAD14-GP DSW ODVREN R1918 B
1 2 330KR2J-L1-GP
DY
BATLOW # E10 AP14 H_PM_SYNC
BATLOW#/GPIO72 PMSYNCH H_PM_SYNC 5
PM_RI# A10 K14 PM_SLP_LAN# 1

RI# SLP_LAN#/GPIO29 TP1905TPAD14-GP
COUGAR-GP-U2-NF
3D3V_S0
3D3V_S5 PM_RSMRST# 1 R1912 2 RSMRST#_KBC 27
0907 X01 SWAP RN1901 0R0402-PAD
RN1901 PM_CLKRUN# R1919 1 2 8K2R2J-3-GP
8 1 BATLOW #
7 2 PM_RI#
6 3 PCH_W AKE#
5 4 SUS_PW R_ACK
PCIE_WAKE#
SRN10KJ-6-GP
CRB : 1K PCH_SUSCLK_KBC
CEKLT: 10K 0625 Modify:
2
Reserved EC1901 on PCH_SUSCLK_KBC for
1 2 AC_PRESENT 0920 X01 Modify: EC1901 EMC NEO suggestion.
R1909 100KR2J-1-GP move PCH_WAKE# to RN1901 pin4 0621 Modify: DY
SC4D7P50V2CN-1GP
Add R1909 PH on AC_PRESENT.
Joseph removed Q1901/R1909/R1916 3V_5V_POK
2 R1922 110KR2J-3-GP PM_PW RBTN#
2 R1920 110KR2J-3-GP PM_SLP_LAN# and PM_RSMRST# related control circuit.
DY
A
DY <Variant Name> A
Wistron Corporation
0719 Modify: 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Change R1908 to 10K ohm based on Intel review: Taipei Hsien 221, Taiwan, R.O.C.
8.2K to 10K pull-down is recommended.
2 R1908 1 PM_RSMRST# Title
10KR2J-3-GP
PCH (DM I/FDI/PM)
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
3D3V_S5
SSID = PCH 3D3V_S50705 Modify:

Add R2004 from RN2001. SMB_CLK 4 1 RN2003
1
SMB_DATA 3 2 SRN2K2J-1-GP
R2004
DY 10KR2J-3-GP SML0_CLK 3 2 RN2004
PCH1B 2 OF 10 SML0_DATA 4 1 SRN2K2J-1-GP
1112 X02 Modify:
2
Dell required us to disable PCIE port of WWAN slot PEG_CLKREQ#_R SML1_CLK 3 RN2005
,If PCIE port 1 is disabled, it will cause all PCIE port
BG34
BJ34
PERN1 Cougar E12 EC_SW I#
0915 SWAP
SML1_DATA
2
1 4 SRN2K2J-1-GP
PERP1 SMBALERT#/GPIO11 EC_SW I# 27
1
disabled,so change WWAN to PCIE port 3 from port1
at ST stage. AV32 PETN1 Point SMB_CLK R2005 PCIE_CLK_REQ6#
AU32 Card Reader
PETP1 SMBCLK H14 SMB_CLK 75 1 4 RN2006
D 10KR2J-3-GP PCH_GPIO74 2 3 SRN10KJ-5-GP D
BE34 C9 SMB_DATA
82 PCIE_RXN2 PERN2 SMBDATA SMB_DATA 75
82 PCIE_RXP2 BF34
2
C2001 PERP2
82 PCIE_TXN2 1 2 SCD1U10V2KX-5GP PCIE_TXN2_C BB32 PETN2 LAN
C2002 1 2 SCD1U10V2KX-5GP PCIE_TXP2_C AY32 DRAMRST_CNTRL_PCH 1 R2009 2
SMBUS
82 PCIE_TXP2 PETP2 DRAMRST_CNTRL_PCH 1KR2J-1-GP
SML0ALERT#/GPIO60 A12 DRAMRST_CNTRL_PCH 37
BG36 3D3V_S0 0719 Modify:
82 PCIE_RXN3 X02 1115 BJ36
PERN3
C8 SML0_CLK RN2007 R2009 change to 1K from 10K
82 PCIE_RXP3 PERP3 SML0CLK base on Intel James feedback list.
C2011 1 2 SCD1U10V2KX-5GP PCIE_TXN3_C AV34 2 3
82 PCIE_TXN3 C2012 1 2 SCD1U10V2KX-5GP PCIE_TXP3_C AU34
PETN3 W-WAN G12 SML0_DATA 1 4
82 PCIE_TXP3 PETP3 SML0DATA
SRN2K2J-1-GP
CRB : 1K
82 PCIE_RXN4 BF36 PERN4
82 PCIE_RXP4
C2005 1 2 SCD1U10V2KX-5GP PCIE_TXN4_C
BE36
AY34
PERP4 WLAN C13 PCH_GPIO74 2nd = 84.DM601.03F CEKLT: 10K
82 PCIE_TXN4 C2006 PETN4 SML1ALERT#/PCHHOT#/GPIO74 84.2N702.A3F
82 PCIE_TXP4 1 2 SCD1U10V2KX-5GP PCIE_TXP4_C BB34 PETP4
E14 SML1_CLK 2N7002KDW -GP
PCI-E*
SML1CLK/GPIO58 SML1_CLK 27,86
82 PCIE_RXN5 BG37 PERN5
BH37 M16 SML1_DATA SMB_DATA 6 1
82 PCIE_RXP5 PERP5 SML1DATA/GPIO75 SML1_DATA 27,86 PCH_SMBDATA 14,15,79,82
C2009 1 2 SCD1U10V2KX-5GP PCIE_TXN5_C AY36
82 PCIE_TXN5 C2010 1 2 SCD1U10V2KX-5GP PCIE_TXP5_C BB36
PETN5 USB3.0 5 2
82 PCIE_TXP5 PETP5
BJ38 PERN6 4 3
CLK_PCH_48M BG38
Controller
PERP6 CL_CLK
AU36 PETN6 Intel GBE LAN CL_CLK1 M7 1 Q2001
AV36 TP2001 TPAD14-GP
PETP6
2
Link
PCH_SMBCLK 14,15,79,82
EC2003 BG40 T11 CL_DATA 1
PERN7 CL_DATA1 TP2002 TPAD14-GP SMB_CLK
BJ40
DY
1
SC4D7P50V2CN-1GP PERP7
AY40 PETN7 Dock
C BB40 P10 CL_RST# 1 1118 X02 Modify: C
PETP7 CL_RST1# TP2003 TPAD14-GP
X02 1118 Change X2001 to 82.30020.D41 from 82.30020.851
BE38 from Sourcer Dick updated. C2008
75 PCIE_RXN8 PERN8
BC38 XTAL25_IN 2 1
75 PCIE_RXP8
C2004 1 2 SCD1U10V2KX-5GP PCIE_TXN8_C AW38
PERP8 NEW CARD X2001
75 PCIE_TXN8 C2003 PETN8
75 PCIE_TXP8 1 2 SCD1U10V2KX-5GP PCIE_TXP8_C AY38 PETP8 For DIS_PX mode or MXM mode.
1 4 SC12P50V2JN-3GP
A00 M10 PEG_CLKREQ#_R
DY
1 2R2003 PEG_CLKREQ# 83
PEG_A_CLKRQ#/GPIO47
2
RN
3 2 CLK_PCH_SRC0_N Y40 0R2J-2-GP
82 CLK_PCIE_W W AN# CLKOUT_PCIE0N
::$1&/. 4 RN2011 1
82 CLK_PCIE_W W AN CLK_PCH_SRC0_P Y39 R2006
0R4P2R-PAD CLKOUT_PCIE0P CLKOUT_PEG_A_N A00 1M1R2J-GP2
CLKOUT_PEG_A_N AB37 4 1 CLK_PCIE_VGA# 83 3
CLOCKS
82 CLK_PCIE_W W AN_REQ# J2 PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P AB38 CLKOUT_PEG_A_P 3 RN2016 2 CLK_PCIE_VGA 83
RN
RN
20100614 V1.1 0R4P2R-PAD C2007
RN
1
A00 0630 SWAP RN2012 A00 XTAL25_OUT XTAL-25MHZ-155-GP2 1
:/$1&/. 82 CLK_PCIE_W LAN# 4 1 CLK_PCH_SRC1_N AB49 AV22 CLKOUT_DMI_N 4 1 CLK_EXP_N 5
CLKOUT_PCIE1N CLKOUT_DMI_N
3 RN2012 2 CLK_PCH_SRC1_P AB47 AU22 CLKOUT_DMI_P 3 RN2010 2
82 CLK_PCIE_W LAN
0R4P2R-PAD CLKOUT_PCIE1P CLKOUT_DMI_P 0R4P2R-PAD
CLK_EXP_P 5 82.30020.D41SC12P50V2JN-3GP
M1
82 CLK_PCIE_W LAN_REQ# PCIECLKRQ1#/GPIO18
AM12 0630 SWAP RN2010,RN2016 2nd = 82.30020.G71
0623 Modify: CLKOUT_DP_N
CLKOUT_DP_P AM13 20100621 V1.2 3rd = 82.30020.G61
SWAP WLAN CLK and LAN CLK routing each other. AA48 3D3V_S0 3D3V_S0
0716 Modify: CLKOUT_PCIE2N
AA47 CLKOUT_PCIE2P
UMA_DISCRETE#
Rename PCIE_CLK_LAN_RQ1# to PCIE_CLK_LAN_REQ#. CLK_BUF_EXP_N
CLKIN_DMI_N BF18 UMA: 1 1
1
PCIE_CLK_RQ2# V10 BE18 CLK_BUF_EXP_P 0712 Modify:
PCIECLKRQ2#/GPIO20 CLKIN_DMI_P SWAP RN2008 R2012 R2013 DIS :0 1
20100614 V1.1
A00 RN2008 UMA SG(PX) : 0 0
10KR2J-3-GP
10KR2J-3-GP
/$1&/. 82 CLK_PCIE_LAN# 3 2 CLK_PCH_SRC3_N Y37 BJ30 CLK_BUF_CPYCLK_N 2 3 Optimus(Muxless) : 1 0
CLKOUT_PCIE3N CLKIN_GND1_N
82 CLK_PCIE_LAN 4 RN2014 1 CLK_PCH_SRC3_P Y36 BG30 CLK_BUF_CPYCLK_P 1 4
2
0R4P2R-PAD CLKOUT_PCIE3P CLKIN_GND1_P UMA_DIS#
B UMA_DIS# 22 B
82 PCIE_CLK_LAN_REQ# A8 SRN10KJ-5-GP DGPU_PRSNT#
PCIECLKRQ3#/GPIO25 CLK_BUF_DOT96_N
RN
CLKIN_DOT_96N G24
1
A00 E24 CLK_BUF_DOT96_P PL 10K FOR Integrated CLOCK GEN mode.
CLK_PCH_SRC4_N CLKIN_DOT_96P 0712 Modify: R2010 R2011
82 CLK_PCIE_USB3# 3 2 Y43 CLKOUT_PCIE4N
86%&/. 4 RN2013 1 CLK_PCH_SRC4_P Y45 SWAP RN2020 SRN10KJ-5-GP DY MUXLESS
10KR2J-3-GP
10KR2J-3-GP
82 CLK_PCIE_USB3 0R4P2R-PAD CLKOUT_PCIE4P CLK_BUF_CKSSCD_N RN2020
CLKIN_SATA_N AK7
82 USB3_PEGB_CLKREQ# L12 AK5 CLK_BUF_CKSSCD_P CLK_BUF_DOT96_N 2 3
2
PCIECLKRQ4#/GPIO26 CLKIN_SATA_P CLK_BUF_DOT96_P 1
RN
4
0623 Modify:
Change PCIE_CLK_RQ2#&CLK_PCIE_WLAN_REQ# V45 K45 CLK_BUF_REF14
pull high power to 3D3V_S0 from 3D3V_S5.(add RN2018) CLKOUT_PCIE5N REFCLK14IN RN2021 SRN10KJ-5-GP
V46 CLKOUT_PCIE5P CLK_BUF_CKSSCD_N 1 4 0712 Modify:
3D3V_S0 20100614 V1.1 PCIE_CLK_REQ5# L14 H45 CLK_PCI_FB CLK_BUF_CKSSCD_P 2 3 3D3V_S5 RN2001 SWAP RN2001 PIN6,7,8
PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK CLK_PCI_FB 18
RN2018 1 8
1 4 PCIE_CLK_RQ2# 0712 Modify: 2 7 PCIE_CLK_LAN_REQ#
2 3 CLK_PCIE_W LAN_REQ# AB42 V47 XTAL25_IN SWAP RN2019 RN2019 3 6 CLK_PCIE_W W AN_REQ#
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT CLK_BUF_EXP_N USB3_PEGB_CLKREQ#
AB40 CLKOUT_PEG_B_P XTAL25_OUT V49 2 3 4 5
SRN10KJ-5-GP CLK_BUF_EXP_P 1 4
PEG_B_CLKRQ# E6 0705 Modify: SRN10KJ-6-GP
PCIECLKRQ1# and PCIECLKRQ2# PEG_B_CLKRQ#/GPIO56 SRN10KJ-5-GP Separate RN2009 10K to RN2019, RN2002
RN2021,R2008 for layout routing.
Support S0 power only XCLK_RCOMP Y47 XCLK_RCOMP
1
R2007
2 +VCCDIFFCLKN
CLK_BUF_REF14
R2008 1 8 EC_SW I#
V40 CLKOUT_PCIE6N 1 2 2 7 PCIE_CLK_REQ5#
V42 90D9R2F-1-GP 3 6 CLK_PCIE_NEW _REQ#
CLKOUT_PCIE6P 10KR2J-3-GP 4 5 PEG_B_CLKRQ#
1(:&$5'&/.
PCIE_CLK_REQ6# T13
A00 PCIECLKRQ6#/GPIO45 SRN10KJ-6-GP
3 2 CLK_PCH_SRC7_N V38 K43 JTAG_TCK 1 22R2J-2-GP
2 0625 Modify:
75 CLK_PCIE_NEW #
4 RN2015 1 CLK_PCH_SRC7_P V37
CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64 R2001 DY JTAG_TCK_VGA 86 For VGA_ 27M Move R2014 to RN2002.
FLEX CLOCKS
75 CLK_PCIE_NEW CLKOUT_PCIE7P
A 0R4P2R-PAD F47 CLK_48_USB30 1 R2016 222R2J-2-GP CLK_PCH_48M 32 <Variant Name> A
CLK_PCIE_NEW _REQ# K12 CLKOUTFLEX1/GPIO65
75 CLK_PCIE_NEW _REQ# PCIECLKRQ7#/GPIO46 CLK_27M_VGA_R 1 R2002
RN
CLKOUTFLEX2/GPIO66 H47 2 CLK_27M_VGA 83

ITPXDP_N DY
CLK_PCIE_NEW # TPAD14-GP TP2005
1
1 ITPXDP_P
AK14
AK13
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67 K49 DGPU_PRSNT# 0908 0R2J-2-GP Wistron Corporation
CLK_PCIE_NEW TPAD14-GP TP2006 0630 Modify: 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Removed LAN_XI for LAN 25MHZ and reserved TP2004. Taipei Hsien 221, Taiwan, R.O.C.
0630 Modify: COUGAR-GP-U2-NF 0707 Modify:
2
Removed XDP CLOCK and reserved TP2005,TP2006. Removed R2002 for USB3.0 48MHZ. Title
EC2004 EC2005 0913 X01 Modify: 0709 Modify:
Reserved EC2004,EC2005 on CLK_PCIE_NEW
V Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3 Add R2002 22ohm for CLK_27M_VGA. PCH (PCI-E/SMBUS/CLOCK/CL)
DY DY V Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and
1
&CLK_PCIE_NEW# for EMC suggestion. 0717 Modify:

SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP Size Document Number Rev
default stuff R2002 22ohm for CLK_27M_VGA.
FLEX2 A3
QUEEN 15 A00
if more than 2 PCI clocks + PCI loopback are routed. Date: Tuesday, January 04, 2011 Sheet 20 of 108
5 4 3 2 1
5 4 3 2 1
0630 modify:
SSID = PCH RTC_AUX_S5
Change RN2104 PH 20K to
R2115,R2216 20K 0402.
R2115
20KR2J-L2-GP
1 2 INTVRMEN- Integrated SUS
1 2
RTC_X1 R2116 1.05V VRM Enable
1
20KR2J-L2-GP C2103 High - Enable internal VRs
1 2 RTC_X2 SC1U6D3V2KX-GP
R2101 10MR2J-L-GP
Low - Enable external VRs
2
D D
PCH1A 1 OF 10 LPC_AD[0..3]
X2101 LPC_AD[0..3] 27,71
1 4 RTC_X1 A20 C38 LPC_AD0

RTCX1 Cougar FWH0/LAD0
A38 LPC_AD1
FWH1/LAD1
LPC
RTC_X2 C20 Point B37 LPC_AD2
SC15P50V2JN-2-GP
RTCX2 FWH2/LAD2
1
1
C2101
2 3 C37 LPC_AD3
C2102 RTC_RST# FWH3/LAD3
D20 RTCRST#
SC15P50V2JN-2-GP D36 LPC_FRAME# 27,71
2
2
FWH4/LFRAME#
2
0805 G2101 1M1R2J-GP SRTC_RST# G22 SRTCRST#
1
C2104 R2104 E36
LDRQ0#
RTC
SC1U6D3V2KX-GP 2 1 SM_INTRUDER# K22 K36 0709 Modify:
INTRUDER# LDRQ1#/GPIO23 KB_DET# 69 KB_DET# connect to GPIO23.(inter PH 20K)
X-32D768KHZ-67-GP GAP-OPEN
2
82.30001.A81 RTC_AUX_S5 1 2 PCH_INTVRMEN C17 V5 INT_SERIRQ 27
1
0720 Modify: INTVRMEN SERIRQ
2nd = 82.30001.691 20100625 V1.2
un-stuff R2122 33ohm. R2105
3rd = 82.30001.861 330KR2F-L-GP
SATA0RXN AM3 SATA_RXN0 56
33R2J-2-GP2 1R2122 HDA_SYNC HDA_BITCLK N34 AM1
29 HDA_CODEC_SYNC DY HDA_BCLK SATA0RXP SATA_RXP0 56
HDD1
SATA 6G
SATA0TXN AP7 SATA_TXN0 56
HDA_SYNC L34 AP5 SATA_TXP0 56
0707 Modify: HDA_SYNC SATA0TXP
Change RN2101 to R2122,R2123 33ohm 0402. T10 AM10
RN2102
HDA_RST#
29 HDA_SPKR
HDA_RST#
SPKR SATA1RXN
SATA1RXP AM8 0629 Modify:
Move All of 0.01uF cap closed to all
HDD2
29 HDA_CODEC_RST# 1 4 K34 HDA_RST# SATA1TXN AP11
2 3 HDA_BITCLK AP10 connector base on Layout guideline.
29 HDA_CODEC_BITCLK SATA1TXP
SRN33J-5-GP-U 29 HDA_SDIN0 E34 AD7
A00 HDA_SDIN0 SATA2RXN
SATA2RXP AD5
2 3 HDA_SDOUT G34 AH5
C 29 HDA_CODEC_SDOUT HDA_SYNC 1 4 HDA_SYNC_R Notes: HDA_SDIN1 SATA2TXN
AH4 C
SATA2TXP
RN2105 SRN33J-5-GP-U ME_UNLOCK (HDA_SDO) connect to EC. C34 HDA_SDIN2
IHDA
SATA3RXN AB8
20101220 R2123 R2124 for change to parallel resistor
Make sure EC drive this pin "low" all the time. A34 HDA_SDIN3 SATA3RXP AB10
AF3
SATA3TXN
SATA3TXP AF1
Flash Descriptor Security Overide HDA_SDOUT A36 HDA_SDO
1 R2107 2 1KR2J-1-GP
SATA
27 ME_UNLOCK SATA4RXN Y7 SATA_RXN4 56
Low = Default Y5
+3VS_+1.5VS_HDA_IO
HDA_SDOUT High = Enable TPAD14-GP TP2105 1PCH_GPIO33 C36 HDA_DOCK_EN#/GPIO33
SATA4RXP
SATA4TXN AD3
SATA_RXP4
SATA_TXN4
56
56 ODD
SATA4TXP AD1 SATA_TXP4 56
N32 HDA_DOCK_RST#/GPIO13
Y3
DY 1 R2102 21KR2J-1-GP HDA_SDOUT SATA5RXN
Y1
SATA_RXN5 57
TPAD14-GP TP2101 PCH_JTAG_TCK_BUF

SATA5RXP
SATA5TXN AB3
SATA_RXP5
SATA_TXN5
57
57 ESATA
1 J3 JTAG_TCK SATA5TXP AB1 SATA_TXP5 57
NO REBOOT STRAP TPAD14-GP TP2102 1 PCH_JTAG_TMS H7 Y11 1D05V_VTT

3D3V_S0 JTAG_TMS SATAICOMPO
JTAG
No Reboot Strap TPAD14-GP TP2103 1 PCH_JTAG_TDI K5 Y10 SATA_COMP R2112 1 2 37D4R2F-GP
JTAG_TDI SATAICOMPI
DY1 R2106 21KR2J-1-GP HDA_SPKR Low = Default TPAD14-GP TP2104 1 PCH_JTAG_TDO H1 1D05V_VTT
JTAG_TDO
HDA_SPKR High = No Reboot SATA3RCOMPO AB12
AB13 SATA3_COMP R2113 1 2 49D9R2F-GP

SATA3COMPI
+3VS_+1.5VS_HDA_IO 1 2 PCH_SPI_CLK T3 AH1 RBIAS_SATA3 R2114 1 2 750R2F-GP

27,60 SPI_CLK_R SPI_CLK SATA3RBIAS
R2108 33R2J-2-GP
B B
1 R2103 2 1KR2J-1-GP HDA_SYNC 27,60 SPI_CS0#_R 1 2 PCH_SPI_CS0# Y14 SPI_CS0#
R2109 33R2J-2-GP
This signal has a weak internal pull down. T1 SPI_CS1#
SPI
On Die PLL VR is supplied by 1.5V when SATALED# P3 SATA_LED# 68
sampled high, 1.8 V when sampled low.
27,60 SPI_SI_R 1 2 PCH_SPI_SI V4 SPI_MOSI SATA0GP/GPIO21 V14 SATA_DET#0
Needs to be pulled High for Huron River platform. R2110 33R2J-2-GP
co-operate with R2310 27,60 SPI_SO_R U3 P1 BBS_BIT0 BBS_BIT0 18
SPI_MISO SATA1GP/GPIO19
COUGAR-GP-U2-NF
PLL ODVR VOLTAGE
HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to
Low = 1.8V (Default)
HDA_SYNC High = 1.5V sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this
signal on the board. Signal may have leakage paths via powered off devices (Audio
Codec) and hence contend with the external pull-up. A blocking FET is
recommended in such a case to isolate HDA_SYNC from the Audio Codec device
until after the Strap sampling is complete.
RUN_ENABLE 2N7002K-2-GP
0625 Modify: 3D3V_S0
G Reserved EC2102,EC2103 on HDA_CODEC_BITCLK&HDA_CODEC_SDOUT for RN2103
EMC NEO suggestion. INT_SERIRQ 1 8 0916 X01 Modify:
D HDA_SYNC_R SATA_DET#0 2 7 Add RN2104 instead of R2111 10K.
22 S_GPIO 3 6
A HDA_CODEC_SYNC S HDA_CODEC_BITCLK HDA_CODEC_SDOUT SPI_CS0#_R 4 5 <Variant Name> A
2
Q2101 SRN10KJ-6-GP
2
R2117 84.2N702.J31
100KR2J-1-GP 2ND = 84.2N702.031 EC2102 EC2103 EC2101 RN2104 Wistron Corporation
4 1 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
DY DY DY 22 FP_DET#
1
1
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
3 2 Taipei Hsien 221, Taiwan, R.O.C.

22 PSW _CLR#
1
SRN10KJ-5-GP Title
0707 Modify:
Reserved Q2101 for isolate CODE and PCH
base on design guide update 1.01.
0720 Modify: PCH (SPI/RTC/LPC/SATA/IHDA)
Add R2117 100K and stuff Q2101,R2124. 0625 Modify: Size Document Number Rev
0712 Modify: Reserved EC2101 on SPI_CSO#_R for A3
Add R2124 between HDA_SYNC_R and HDA_SYNC. EMC NEO suggestion. QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
3D3V_S0
0719 Modify: SSID = PCH
Change R2202 to 100K from 200K. GSENSOR_ST GSENSOR_ADI
R2202 Note:
1 2 SATA_ODD_PRSNT# For PCH debug with XDP, need to NO STUFF R2218 R2205 DY 10K
PCH1F 6 OF 10
100KR2J-1-GP
0629 Modify: 20100625 V1.2 S_GPIO 1 R2218 2 GPIO0 T7 C40
R2206 100K DY
3D3V_S0 0712 Modify: Stuff R2202 200K 0402 1%(ANNIE updated) 21 S_GPIO 100R2J-2-GP BMBUSY#/GPIO0 Cougar TACH4/GPIO68 SATA_ODD_PW RGT 56
SWAP RN2203 EC_SMI# B41 UMA_DIS#
RN2203
27 EC_SMI# A42 TACH1/GPIO1 Point TACH5/GPIO69 UMA_DIS# 20
2 3 H_A20GATE DGPU_HPD_INTR# H36 C41 VRAM_SIZE1 1 TP2204 TPAD14-GP 3D3V_S0
H_RCIN# TACH2/GPIO6 TACH6/GPIO70
D 1 4 D
EC_SCI# E38 A40 VRAM_SIZE2 1 TP2205 TPAD14-GP
27 EC_SCI# TACH3/GPIO7 TACH7/GPIO71
1
SRN10KJ-5-GP 1120 X02 Modify:
Rename PCH_GPIO12 to RTC_DET# ICC_EN# C10 R2205
on GPIO12. GPIO8 10KR2J-3-GP
GPIO27 has a weak[20K] internal pull up.
To enable on-die PLL Voltage regurator, 60 RTC_DET# RTC_DET# C4
DY
LAN_PHY_PWR_CTRL/GPIO12
2
should not place external pull down.0908 X01 Modify: PCH_GPIO15 GSENSOR_DET
G2 GPIO15 A20GATE P4 H_A20GATE 27
change FFS_INT2_R from PCH GPIO48 to GPIO14
1
Keep PCH_GPIO5 PH R2201,PCH_GPIO48 PH R2220 AU16 H_PECI_R 1 R2203 2
DY H_PECI 5,27
CPU/MISC
PECI 0R2J-2-GP
56 SATA_ODD_PRSNT# 1 2 PCH_GPIO16 U2 SATA4GP/GPIO16
R2206
3D3V_S0 R2213 0R0402-PAD P5 100KR2J-1-GP
R2220 10KR2J-3-GP RCIN# H_RCIN# 27 DY
GPIO
1 2 PCH_GPIO48 83,92,93 DGPU_PW ROK DGPU_PW ROK D40 AY11 H_CPUPW RGD 5,36
2
0720 Modify: TACH0/GPIO17 PROCPWRGD
Removed DBC_EN on GPIO22. TPAD14-GP TP2210 1 DBC_EN T5 AY10 PCH_THERMTRIP_R R2204 1 2 390R2J-1-GP
SCLOCK/GPIO22 THRMTRIP# H_THERMTRIP# 5,36
E8 T14 INIT3_3V# 1 TP2201 TPAD14-GP 0625 Modify:
82 3G_EN GPIO24/MEM_LED INIT3_3V# Change PL 100K 0402 from PH on GFX_CRB_DET.
0701 Modify: 0709 Modify:
Separate PCH_TEMP_ALERT# from RN2201 3D3V_S0 Rename PCH_GPIO22 to DBC_EN. TPAD14-GP TP2203 1 PCH_GPIO27 E16
to R2222 10K base on layout limitation. Rename PCH_GPIO24 to 3G_EN. GPIO27
PLL_ODVR_EN P8
R2222 10KR2J-3-GP GPIO28
TS_VSS1 AH8
PCH_TEMP_ALERT#1 2 0701 Modify: PSW _CLR# K1
21RN2202 PSW _CLR#
Separate MFG_MODE from STP_PCI#/GPIO34
R2223 10KR2J-3-GP to R2223 10K base on layout limitation. TS_VSS2 AK11 TS Signal Disable Guideline:
21 FP_DET# K4 GPIO35
MFG_MODE 1 2 AH10 TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4
TS_VSS3
2
GAP-OPEN
DMI_OVRVLTG V8 should not float on the motherboard. They should
SATA2GP/GPIO36
TS_VSS4 AK10 TS_VSS 1 2
C RN2201 G2201 FDI_OVRVLTG M5 SATA3GP/GPIO37
R2219 0R0402-PAD be tied to GND directly. C
EC_SMI# 1 8 0916 X01 Modify: P37
EC_SCI# Move EC_SCI#,DBC_EN to RN2201. MFG_MODE NC_1
2 7 N2
1
DGPU_HPD_INTR# Move S_GPIO to RN2103. SLOAD/GPIO38
3 6
DBC_EN Move PSW_CLR# to RN2104. GSENSOR_DET 0707 Modify:
4 5 M3 SDATAOUT0/GPIO39
0923 SWAP 1118 X02 Modify: Change R2219 change to 0ohm 0402 from short pad.
SRN10KJ-6-GP Rename GFX_CRB_DET to GSENSOR_DET PCH_GPIO48 V13 BG2
on GPIO39. SDATAOUT1/GPIO48 NCTF_VSS#BG2
1118 X02 Modify: PCH_TEMP_ALERT# V3 BG48 3D3V_S0
Rename USB3_PWR_ON to PCH_GPIO57. SATA5GP/GPIO49 NCTF_VSS#BG48
1120 X02 Modify: 1120 X02 Modify: USB2_CRT_ON# D6 BH3
61 USB2_CRT_ON# GPIO57 NCTF_VSS#BH3
1
Rename PCH_GPIO12 to RTC_DET# Reserved USB2_CRT_ON# to control FDI TERMINATION VOLTAGE OVERRIDE
on GPIO12. U6102 USB power switch from PCH GPIO57. R2207
NCTF_VSS#BH47 BH47
10KR2J-3-GP
3D3V_S5 TPAD14-GP TP2206 PCH_NCTF_1
1 A4 NCTF_VSS#A4 NCTF_VSS#BJ4 BJ4 DY
GPIO37 LOW - Tx, Rx terminated to same voltage
2
0714 Modify: A44 BJ44 FDI_OVRVLTG (FDI_OVRVLTG) (DC Coupling Model DEFAULT)
A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49
RN2204 Add TP2206~TP2209 on PCH NCTF pin. NCTF_VSS#A44 NCTF_VSS#BJ44
1
RTC_DET# 4 1 A45 BJ45
NCTF_VSS#A45 NCTF_VSS#BJ45
BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48
USB2_CRT_ON# 3 2 R2208
NCTF
A46 BJ46 10KR2J-3-GP
NCTF TEST PIN:

SRN10KJ-5-GP NCTF_VSS#A46 NCTF_VSS#BJ46
A5 BJ5
2
PCH_GPIO15 NCTF_VSS#A5 NCTF_VSS#BJ5
1 R2201 2
1KR2J-1-GP A6 BJ6 DMI TERMINATION VOLTAGE OVERRIDE
NCTF_VSS#A6 NCTF_VSS#BJ6
R2221 B3 C2
3G_EN NCTF_VSS#B3 NCTF_VSS#C2
1 2
10KR2J-3-GP B47 C48 3D3V_S0 GPIO36 LOW - Tx, Rx terminated to same voltage
B NCTF_VSS#B47 NCTF_VSS#C48 B
20100625 V1.2 (DMI_OVRVLTG) (DC Coupling Model DEFAULT)
BD1 NCTF_VSS#BD1 NCTF_VSS#D1 D1
1
0629 Modify:
D1,D49,E1,E49,F1,F49
Add R2221 10K 0402 on PCH_GPIO24(ANNIE updated) BD49 D49 R2209
0709 Modify: NCTF_VSS#BD49 NCTF_VSS#D49 10KR2J-3-GP
Rename PCH_GPIO24 to 3G_EN on R2221. TPAD14-GP TP2207 PCH_NCTF_2
1 BE1 NCTF_VSS#BE1 NCTF_VSS#E1 E1 DY Integrated Clock Enable functionality is achieved
via soft-strap. The default is integrated clock
2
TPAD14-GP TP2208 1 PCH_NCTF_3 BE49 E49 DMI_OVRVLTG
NCTF_VSS#BE49 NCTF_VSS#E49
enable.
1
BF1 NCTF_VSS#BF1 NCTF_VSS#F1 F1
R2210
TPAD14-GP TP2209 1 PCH_NCTF_4 BF49 F49 10KR2J-3-GP
NCTF_VSS#BF49 NCTF_VSS#F49 Integrated Clock Chip Enable
2
COUGAR-GP-U2-NF
ICC_EN# HIGH (R2211 DY)- DISABLED [DEFAULT]
LOW (R2211)- ENABLED

ICC_EN#1 R2211 2
1KR2J-1-GP GPIO8 has a weak[20K] internal pull up.
Integrated Clock Enable functionality is achieved
via soft-strap. The default is integrated clock
enable.
[VRAM_SIZE1:VRAM_SIZE2]
LL=512M / HL=1G / LH=2G
A <Variant Name> A
PLL ON DIE VR ENABLE
0705 Modify:
Removed R2214~R2217 10K 0402 on VRAM_SIZE1&2.

NOTE:This
20K
signal has a weak internal pull-up Wistron Corporation
ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT Taipei Hsien 221, Taiwan, R.O.C.
DISABLED -- LOW (R2212 STUFFED)
Title
PLL_ODVR_EN DY 1 R2212 2 PCH (GPIO/CPU)

1KR2J-1-GP Size Document Number Rev
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
3D3V_DAC_S0
A00 1228
SSID = PCH 6A R2301
1 2
0R0402-PAD-2-GP 3D3V_S0
1111 X02 Modify:
1D05V_VTT
PCH1G POWER 7 OF 10 (0.1uF/0.01uF x1) Change VCCADAC power source to
3D3V_DAC_S0 from 3D3V_S0.
1.3A(Total current of VCCCORE) 0.001A (10uF x1_0603)
Cougar L2301
AA23 U48 +VCCA_DAC_1_2 1 DY 2
SCD01U16V2KX-3GP
AC23
VCCCORE Point VCCADAC HCB1608KF-181-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
D D
VCCCORE
1
CRT
C2301
C2302
C2303
C2304
(1uFx3) AD21 C2313 C2314 C2315
VCCCORE 68.00214.051
1
(10uFx1_0603) AD23 U47 2nd = 68.00206.041
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
VCCCORE VSSADAC
VCC CORE
AF21 3rd = 68.00335.081
2
VCCCORE
AF23
2
VCCCORE 3D3V_S0
AG21 VCCCORE 0.001A
AG23 VCCCORE
AG24 AK36 +3VS_VCCA_LVDS 1 R2304 2
VCCCORE VCCALVDS 0R0603-PAD
AG26 VCCCORE
AG27 AK37 0917 X01 Modify:
VCCCORE VSSALVDS Change R2304 to 0R0603
AG29 VCCCORE
AJ23 short pad from 0ohm.
LVDS
VCCCORE 1D8V_S0
AJ26 VCCCORE VCCTX_LVDS AM37 0.06A
AJ27 VCCCORE
AJ29 AM38 +1.8VS_VCCTX_LVDS 1 R2305 2
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
VCCCORE VCCTX_LVDS 0R0805-PAD
AJ31 VCCCORE
C2316
C2317
VCCTX_LVDS AP36
1
1D05V_VTT C2318 (0.01uF x2)
AP37 (22uF x1)
SC10U6D3V5KX-1GP
VCCTX_LVDS
AN19
2
VCCIO
TPAD14-GP TP2301 1 VCCAPLLEXP BJ22

1D05V_VTT VCCAPLLEXP
(10uF x1)
2.925A(Total current of VCCIO) V33
HVCMOS
VCC3_3
AN16 VCCIO 3D3V_S0
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
C2305
C2306
C2307
C2308
C2309
(1uF x4) AN17 VCCIO 0.266A (0.1uFx1)
1
1
VCC3_3 V34
C C
1
AN21 C2319
2
2
VCCIO SCD1U10V2KX-5GP
A00
AN26 0.16A
2
VCCIO R2308 1D5V_S0 1119 X02 Modify:
AN27 AT16 VCCVRM 1 2 Reserved R2308 on VCCVRM power rail.
0818 VCCIO VCCVRM
De-cap 1D05V_VTT
AP21 VCCIO 0.042A A00 0R0402-PAD-2-GP
AP23 AT20 +1.05VS_VCC_DMI 1 2
VCCIO VCCDMI R2306 (1uF x1)
DMI
1
AP24 0R0402-PAD-2-GP
VCCIO
VCCIO C2320
AP26 AB36 SC1U6D3V2KX-GP
2
VCCIO VCCCLKDMI
Refer to NPCE795 shared SPI flash architecture
A00 1D05V_VTT
AT24 VCCIO 0.02A
+1.05VS_VCC_DMI_CCI 1 2
0.266A (Totally VCC3_3 current) AN33 R2307
VCCIO
1
0R0402-PAD-2-GP (1uFx1)
3D3V_S0 AN34 AG16 C2321 (10uFx1)
VCCIO VccDFTERM SC1U6D3V2KX-GP
2
NAND / SPI
(0.1uF x1) BH29 VCC3_3 VccDFTERM AG17
1
C2310
0.159A(Totally current of VCCVRM) SCD1U10V2KX-5GP AJ16
2
VccDFTERM 1D8V_S0
B 1D5V_S0 AP16 VCCVRM 0.19A B

VccDFTERM AJ17
VCCVRM(Internal PLL and VRMs):
1
TPAD14-GP TP2302 1 VCCFDIPLL BG6 C2322
A.1.5V for Mobile VCCAFDIPLL SCD1U10V2KX-5GP (0.1uFx1)
B.1.8 V for Desktop
2
1D05V_VTT AP17 VCCIO
FDI
VCCSPI V1
3D3V_S5
+1.05VS_VCC_DMI AU20 0.02A
VCCDMI
0.042A (Totally current of VCCDMI)
1
COUGAR-GP-U2-NF (1uFx1)
C2323
SC1U6D3V2KX-GP
2
3.3V CRT LDO
Current Limit=360mA
5V_S5 3D3V_S0 3D3V_DAC_S0
U2301
1 VIN VOUT 5
1122 X02 Modify: 2
Removed U2302 LDO for VCCVRM. GND
3 EN NC#4 4
1
1
A <Variant Name> A
C2311 G9091-330T11U-GP C2312
74.09091.J3F
SC1U10V2KX-1GP
SC1U6D3V2KX-GP
2
2
2nd = 74.09198.G7F Wistron Corporation
3rd = 74.07716.A7F 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
20100621 V1.2 Taipei Hsien 221, Taiwan, R.O.C.
1117 X02 Modify:
Add G9091 LDO circuit for CRT DAC power Title
to avoid monitor noise issue.
1122 X02 Modify:
base on layout condition change 3D3V_DAC_S0
PCH (POWER1)
circuit. A3
A00 1229 add 3rd Richtek(74.09198.G7F) on U2301 at XBuild batch run config QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
SSID = PCH
PCH1J POWER 10 OF 10 1D05V_VTT
TPAD14-GP TP2401 1 VCCACLK AD49 N26

VCCACLK Cougar VCCIO
(1uFx1)
1
0.002A Point VCCIO P26 C2423
3D3V_S5 1 R2403 2 +VCCPDSW T16 VCCDSW3_3
SCD1U10V2KX-5GP
3D3V_S0 0R0603-PAD P28
2
VCCIO 0818
(0.1uFx1)
TPAD14-GP TP2405 1 DCPSUSBYP V12 T27 De-cap
DCPSUSBYP VCCIO 3D3V_S5 5V_S5
(10uFx1)
D (1uFx1) VCCIO T29 D
+V3.3S_VCC_CLKF33 T38 3D3V_S5
VCC3_3
2
L2401 0.097A (Totally current of VCCSUS3_3)
1 2 +V3.3S_VCC_CLKF33 T23 D2401
IND-10UH-218-GP C2401 TPAD14-GP TP2404 +VCCAPLL_CPY_PCH VCCSUS3_3
1 BH23 VCCAPLLDMI2
(0.1uFx1) CH751H-40PT-GP
1
T24 C2424 2nd = 83.R2004.B8F 83.R0304.A8F
C2402 VCCSUS3_3 SCD1U10V2KX-5GP R2408
68.10050.10Y 1D05V_VTT (10uFx1) AL29
SC10U6D3V5KX-1GP
1
SC1U10V2KX-1GP VCCIO
2nd = 68.1001E.10N V23 1 2
USB
2
2
VCCSUS3_3
TPAD14-GP TP2402 1 +VCCSUS1 AL24 V24 3D3V_S5 10R2J-2-GP (0.1uFx1)
DCPSUS VCCSUS3_3
1
P24 C2426
VCCSUS3_3 SCD1U10V2KX-5GP
(0.1uFx1)
2
1
AA19 VCCASW
T26 1D05V_VTT C2425
VCCIO SCD1U10V2KX-5GP
AA21
2
VCCASW
+5VA_PCH_VCC5REFSUS
0.001A
AA24 VCCASW V5REF_SUS M26
3D3V_S0 5V_S0
Clock and Miscellaneous

AA26 VCCASW
AN23 +VCCA_USBSUS 1 TP2403 TPAD14-GP
1D05V_VTT DCPSUS
AA27 VCCASW
2
1.01A (Total current of VCCASW) VCCSUS3_3 AN24 3D3V_S5
AA29 VCCASW DYC2437
SC1U10V2KX-1GP
D2402
CH751H-40PT-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
2
C2406
C2407
C2408
(22uFx2_0603) C2403 C2404 AA31 2nd = 83.R2004.B8F 83.R0304.A8F
VCCASW
1
1
(1uFx3) 0.001A R2407
1
AC26 P34 +5VS_PCH_VCC5REF 1 2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCCASW V5REF
(1uFx1)
2
2
C AC27 10R2J-2-GP C
VCCASW
1
N20 3D3V_S5
VCCSUS3_3
PCI/GPIO/LPC
AC29 C2427
VCCASW SC1U10V2KX-1GP
N22
2
1D05V_VTT 0818 VCCSUS3_3
0.08A (1uFx1) AC31 VCCASW
(1uFx1)
1
(220uFx1) De-cap P20
L2402 VCCSUS3_3 C2428
AD29 VCCASW
1 2 +1.05VS_VCCA_A_DPL P22 SC1U6D3V2KX-GP
2
IND-10UH-218-GP VCCSUS3_3
AD31
SC10U6D3V3MX-GP SC10U6D3V3MX-GP
VCCASW
1
68.10050.10Y C2443
C2409 3D3V_S0
2nd = 68.1001E.10N W21 VCCASW VCC3_3 AA16
DY SC1U6D3V2KX-GP
2
0714 Modify: W23 W16

Reserved C2443,C2444 on +1.05VS_VCCA_A_DPL, VCCASW VCC3_3
(0.1uFx2)
1
(1uFx1) +1.05VS_VCCA_B_DPL same as DG15.
L2403
0.08A W24 VCCASW VCC3_3 T34
C2430 C2431
(220uFx1)
1 2 +1.05VS_VCCA_B_DPL W26 SCD1U10V2KX-5GP SCD1U10V2KX-5GP
2
IND-10UH-218-GP VCCASW
1
C2444 3D3V_S0
68.10050.10Y C2410
W29 VCCASW
2nd = 68.1001E.10N
DY SC1U6D3V2KX-GP W31 AJ2
2
VCCASW VCC3_3
(0.1uFx1)
1
0617 Modify: W33 VCCASW
AF13 C2429
Joseph Rename 1D5V_S0_1D8V_S0 to 1D5V_S0 for VCCVRM. VCCIO SCD1U10V2KX-5GP
2
+VCCRTCEXT N16 DCPRTC 1D05V_VTT
0.16A (Totally current of VCCVRM VCCIO AH13
1
C2411 (0.1uFx1) 1D5V_S0 Y49 AH14

B SCD1U10V2KX-5GP VCCVRM VCCIO B
(1uFx1)
2
1
AF14 C2432
+1.05VS_VCCA_A_DPL VCCIO SC1U6D3V2KX-GP
BD47
SATA
2
VCCADPLLA 1D05V_VTT
VCCAPLLSATA AK1
+1.05VS_VCCA_B_DPL BF47 R2411
VCCADPLLB +V1.05S_VCCAPLL_SATA3 1 2
AF11 1D5V_S0 C2434 DY (10uFx1)
VCCVRM
1
1D05V_VTT A00 1D05V_VTT +VCCDIFFCLKN +VCCDIFFCLK AF17 0R3J-0-U-GP
R2404 VCCIO
0.055A (1uFx1) AF33
DY
SC10U6D3V5KX-1GP
+VCCDIFFCLK VCCDIFFCLKN
1 2 1 R2406 2 AF34 AC16
2
0R0603-PAD VCCDIFFCLKN VCCIO
(1uFx1) AG34 VCCDIFFCLKN
1
1D05V_VTT
0R0402-PAD-2-GP C2412 C2414
0.095A VCCIO AC17
SC1U6D3V2KX-GP SC1U6D3V2KX-GP +V1.05S_SSCVCC AG33 AD17

2
SCD1U10V2KX-5GP(1uFx1) VCCSSC VCCIO

(1uFx1)
1
C2415 C2435
1D05V_VTT A00 (0.1uFx1) 2 1 +VCCSST V16 SCD1U10V2KX-5GP
R2405 DCPSST 1D05V_VTT
2
1 2 +V1.05S_SSCVCC 0818
T17 T21 De-cap
DCPSUS VCCASW
1
(1uFx1) TPAD14-GP TP2406 1 DCPSUS V19

0R0402-PAD-2-GP DCPSUS
MISC
C2413 0714 Modify: +3VS_+1.5VS_HDA_IO

SC1U6D3V2KX-GP 1D05V_VTT Removed C2419 1uF base on V21
2
Annie updated schematic. VCCASW

0.001A 1 R2409 2
CPU
3D3V_S5
BJ8 0R0603-PAD
SCD1U10V2KX-5GP
V_PROC_IO +3VS_+1.5VS_HDA_IO
C2418
(0.1uFx2) VCCASW T19

1
(4.7uFx1_0603)
A C2417 <Variant Name> A
SC4D7U6D3V3KX-GP 0.01A
2
RTC
A22 P32
HDA
RTC_AUX_S5 VCCRTC VCCSUSHDA

(0.1uFx1)
Wistron Corporation
1
6uA COUGAR-GP-U2-NF C2433 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
SCD1U10V2KX-5GP Taipei Hsien 221, Taiwan, R.O.C.
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
C2421
C2422
(0.1uFx2)
1
(1uFx1) Title
PCH (POWER2)
2

A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
SSID = PCH PCH1I 9 OF 10
AY4 VSS Cougar VSS H46

AY42 VSS VSS K18
AY46 VSS Point VSS K26
AY8 VSS VSS K39
B11 VSS VSS K46
B15 VSS VSS K7
B19 VSS VSS L18
B23 VSS VSS L2
B27 VSS VSS L20
D B31 VSS VSS L26 D
PCH1H 8 OF 10 B35 L28
VSS VSS
H5 VSS B39 VSS VSS L36
Cougar B7 VSS VSS L48
AA17 VSS VSS AK38 F45 VSS VSS M12
AA2 VSS Point VSS AK4 BB12 VSS VSS P16
AA3 VSS VSS AK42 BB16 VSS VSS M18
AB11 VSS VSS AL16 BB24 VSS VSS M30
AB7 VSS VSS AL26 BC14 VSS VSS M46
AC19 VSS VSS AL27 BC18 VSS VSS M8
AC2 VSS VSS AL31 BC2 VSS VSS N18
AC21 VSS VSS AL33 BC22 VSS VSS P30
AC24 VSS VSS AL34 BC26 VSS VSS N47
AC33 VSS VSS AL48 BC32 VSS VSS P11
AC34 VSS VSS AM11 BC34 VSS VSS P18
AC48 VSS VSS AM14 BC36 VSS VSS T33
AD10 VSS VSS AM36 BC40 VSS VSS P40
AD13 VSS VSS AM45 BD46 VSS VSS P7
AD19 VSS VSS AM46 BD5 VSS VSS R2
AD24 VSS VSS AM7 BE22 VSS VSS R48
C AD26 AN2 BE26 T12 C
VSS VSS VSS VSS
AD27 VSS VSS AN29 BE40 VSS VSS T31
AD33 VSS VSS AN3 BF10 VSS VSS T37
AD34 VSS VSS AN31 BF12 VSS VSS T4
AD36 VSS VSS AP12 BF16 VSS VSS W34
AD37 VSS VSS AP19 BF20 VSS VSS T46
AD4 VSS VSS AP32 BF26 VSS VSS V11
AD42 VSS VSS AP4 BD3 VSS VSS V26
AD8 VSS VSS AR2 BF8 VSS VSS V36
AE2 VSS VSS AR48 BG17 VSS VSS V39
AE3 VSS VSS AT11 BG21 VSS VSS V43
AF10 VSS VSS AT13 BG33 VSS VSS V7
AF12 VSS VSS AT18 BG44 VSS VSS W17
AD14 VSS VSS AT22 BG8 VSS VSS W19
AD16 VSS VSS AT26 BH11 VSS VSS W2
AF16 VSS VSS AT28 BH15 VSS VSS W27
AF19 VSS VSS AT30 BH17 VSS VSS W48
AF24 VSS VSS AT32 BH19 VSS VSS Y12
AF26 VSS VSS AT34 H10 VSS VSS Y38
B B
AF4 VSS VSS AU24 BH39 VSS VSS BG29
AF42 VSS VSS AU30 BH43 VSS VSS N24
AF46 VSS VSS AV16 BH7 VSS VSS AJ3
AF5 VSS VSS AV20 D3 VSS VSS AD47
AF7 VSS VSS AV24 D12 VSS VSS B43
AF8 VSS VSS AV30 D16 VSS VSS BE10
AG19 VSS VSS AV38 D18 VSS VSS BG41
AG2 VSS VSS AV4 D22 VSS VSS G14
AG31 VSS VSS AV43 D24 VSS VSS H16
AG48 VSS VSS AV8 D26 VSS VSS T36
AH11 VSS VSS AW14 D30 VSS VSS BG22
AH3 VSS VSS AW18 D32 VSS VSS BG24
AH36 VSS VSS AW2 D34 VSS VSS C22
AH39 VSS VSS AW22 D38 VSS VSS AP13
AH40 VSS VSS AW26 D42 VSS VSS M14
AH42 VSS VSS AW28 D8 VSS VSS AP3
AH46 VSS VSS AW32 E18 VSS VSS AP1
AH7 VSS VSS AW34 E26 VSS VSS BE16
AJ19 VSS VSS AW36 G18 VSS VSS BC16
AJ21 VSS VSS AW40 G20 VSS VSS BG28
AJ24 VSS VSS AW48 G26 VSS VSS BJ28
AJ33 VSS VSS AV11 G28 VSS
AJ34 VSS VSS AY12 G36 VSS
AK12 VSS VSS AY22 G48 VSS
AK3 VSS VSS AY28 H12 VSS
H18 VSS
COUGAR-GP-U2-NF H22 VSS
H24 VSS
A H26 VSS <Variant Name> A
H30 VSS
H32 VSS
H34
F3
VSS
VSS
Wistron Corporation
COUGAR-GP-U2-NF Title
PCH (VSS)
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3D3V_AUX_KBC 3 2 3D3V_AUX_KBC
MODEL_ID_DET(GPIO07) PULL-LOW RESISTOR
1 PULL-HIGH RESISTOR VOLTAGE
SSID = KBC A00 1222
PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
DQ15_UMA 100.0K 10.0K 3.0V
1
X00 100.0K 10.0K 3.0V
1
0719 Modify: R2710 DQ15_ATI 100.0K 20.0K 2.75V
3D3V_AUX_KBC 0714 Modify: Reserved 0.1uF on all of ADC input pins base on
64.33025.6DL 33KR2F-GP
R2724 X01 100.0K 20.0K 2.75V
Change C2709,C2710 to EC_AGND from GND. 3D3V_S0 NUVOTON feedback list.(C2717~C2721) 47KR2F-GP DQ15_NVIDIA 100.0K 33.0K 2.48V
1 R2702 2 VBAT X02 100.0K 33.0K 2.48V 0728
2
0R0603-PAD DN15_UMA 100.0K 47.0K 2.24V
2
2
0628 Modify: A00 100.0K 47.0K 2.24V Ventura need to change to 215K(64.21535.6DL)
R2771 Move R2771 to closed 3D3V_AUX_KBC power PCB_VER_AD MODEL_ID_DET DN15_ATI 100.0K 64.9K 2.0V
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
1
2D2R3-1-U-GP rail base on layout placement. Reserved 100.0K 64.9K 2.0V
1
C2702 C2703 DQ13_UMA 100.0K 76.8K 1.87V
3D3V_AUX_KBC_VCC SCD1U10V2KX-5GP DY SC2D2U10V3KX-1GP R2726 Reserved 100.0K 76.8 1.87V
1
2
100KR2F-L1-GP DQ13_ATI 100.0K 100.0K 1.65V
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2704
C2705
C2706
C2707
C2708
C2717 Reserved 100.0K 100.0K 1.65V C2718
1
1
C2709
C2710
SCD1U10V2KX-5GP SCD1U10V2KX-5GP DN13_UMA 100.0K 143.0K 1.358V
1
C2701 Reserved 100.0K 143.0K 1.358V
DY DN13_ATI 100.0K 174.0K 1.204V
SC2D2U10V3KX-1GP
2
115
102
D C2711 Reserved 100.0K 174.0K 1.204V
D
19
46
76
88
DY
4
U2701A 1 OF 2 1 2 EC_AGND EC_AGND DQ15_Ventura 100.0K 215.0K 1.048V
SC220P50V2KX-3GP Reserved 100.0K 215.0K 1.048V
VCC
VCC
VCC
VCC
VCC
AVCC
VDD
EC_AGND R2735 A00 0707 Modify:
40 AD_IA
104
VREF LRESET#
7 PLT_RST#_EC
1 2 PLT_RST# 5,18,71,75,82,83
Rename DISCRETE# to MODEL_ID_DET.
Change R2739 to 100K 0402 from 10K.
215K=64.21535.6DL
C2714 1 2 SCD1U10V2KX-5GP 2 0R0402-PAD-2-GPCLK_PCI_KBC
EC_AGND
97
LCLK
3 LPC_FRAME#
18
21,71
NOTES: Notes:
PCB_VER_AD GPIO90/AD0 LFRAME# LPC_AD3
98
GPIO91/AD1 LAD3
1 The NPCE795P GPIO/PWM outputs that are connected
0720 Modify:
Stuff C2714 0.1uF on AD_IA.
82
28
PSID_EC
CPU_THRM
99
100
GPIO92/AD2 LAD2
128
127
LPC_AD2
LPC_AD1
LPC_AD[0..3] 21,71
to LEDs have high drive buffers (20mA) and can be
The total SPI interface signal between EC and PCH
GPIO93/AD3 LAD1 LPC_AD0
126
28 FAN1_DAC
101
GPIO94/DA0
LAD0
SERIRQ
125 INT_SERIRQ 21 connected directly to the LEDs. cant not exceed 6500mil. The mismatch between
49 LCD_TST 105 8 PM_CLKRUN# 19
GPIO95/DA1 GPIO11/CLKRUN#
0708 Modify:
Rename EG_EN to MEDIA_BTN2# on GPIO96.
MEDIA_BTN2# 106
GPIO96/DA2 GPIO65/SMI#
9
29
PANEL_BLEN
ECSCI#_KBC 0707 Modify:
SPI signal must be within 500mil
0702 Modify: ECSCI#/GPIO54 0707 Modify: KBC_GPIO14 change to PCIE_WAKE#.
GPIO10/LPCPD#
124 HDMI_IN# 51 20100609 V1.0
Rename CHARGE_LED# to CHG_AMBER_LED# 79 123 ECSWI#_KBC Rename PCH_TEMP_ALERT# for HDMI_IN#
19 SUS_PWR_ACK GPIO2 GPIO67/PWUREQ#
Rename DC_BATFULL# to BATT_WHITE_LED#. 95 121
57 USBCHARGER_CB0 GPIO3/AD6 GPIO85/GA20 H_A20GATE 22
USB3_PWR_ON
96 122 0702 Modify: U2701B 2 OF 2
82 USB3_PWR_ON GPIO4/AD5 KBRST#/GPIO86 H_RCIN# 22 KCOL[0..16] 69
108 Rename CHARGE_LED# to CHG_AMBER_LED#
28 SYS_THRM GPIO5/AD4 3D3V_AUX_KBC
0702 Modify: PSL_IN2 93 Rename DC_BATFULL# to BATT_WHITE_LED#. 31 53 KCOL0
PSL_IN2#_GPIO6 28 FAN_TACH1 GPIO56/TA1 KBSOUT0/JENK#
Rename EC_GPIO6 to PSL_IN2 MODEL_ID_DET 94 27 117 52 KCOL1
GPIO7/AD7 GPIO52/PSDAT3/RDY# BLON_OUT 49 19 PM_PWRBTN# GPIO20/TA2 KBSOUT1/TCK
0707 Modify:
68 BATT_WHITE_LED# 114 25 AD_IA_HW2 AD_IA_HW2 40
0709 Modify:
75,82 PCIE_WAKE# 63 51 KCOL2 A00
Rename DISCRETE# to MODEL_ID_DET. ECSMI#_KBC GPIO16 GPIO50/PSCLK3/TDO EC_GPIO27 change to PCH_WAKE# to PCH. GPIO14/TB1 KBSOUT2/TMS KCOL3 RN2707
6 11 PCH_WAKE# 19 19,36,37,47,75 PM_SLP_S3# 64 50
Rename EC_GPIO36 for MEDIA_BTN3#. GPIO24 GPIO27/PSDAT2 MEDIA_BTN1# 0709 Modify: GPIO01/TB2 KBSOUT3/TDI KCOL4 MEDIA_BTN2#
69 CAP_LED 109 10 49 4 1
GPIO30 GPIO26/PSCLK2 KB_DET# rename to MEDIA_BTN1# on KBC GPIO26. KBSOUT4/JEN0# KCOL5 MODEL_ID_DET
36 S5_ENABLE 14 71 TPDATA 69 68 CHG_AMBER_LED# 32 48 3 2
GPIO34/CIRRXL GPIO35/PSDAT1 GPIO15/A_PWM KBSOUT5/TDO KCOL6
82 MEDIA_BTN3# 15
80
GPIO36 GPIO37/PSCLK1
72 TPCLK 69 <------ TP 29 KBC_BEEP 118
62
GPIO21/B_PWM KBSOUT6/RDY#
47
43 KCOL7
39 BAT_IN# GPIO41 82 MEDIA_LED1# GPIO13/C_PWM KBSOUT7
17 65 42 KCOL8 SRN100KJ-6-GP
70 LID_CLOSE# GPIO42/TCK 69 KB_BL_CTRL GPIO32/D_PWM KBSOUT8 KCOL9
19 RSMRST#_KBC 20
21
GPIO43/TMS GPIO17/SCL1
70
69
BAT_SCL 39,40 <------ BATTERY / CHARGER 40 AD_IA_HW 81
66
GPIO66/G_PWM KBSOUT9/SDP_VIS#
41
40 KCOL10 A00 R2739 R2774 for change to parallel resistor
19,46,75 PM_SLP_S4# GPIO44/TDI GPIO22/SDA1 BAT_SDA 39,40 82 MEDIA_LED3# GPIO33/H_PWM KBSOUT10/P80_CLK KCOL11 EC_AGND
21 ME_UNLOCK 23
26
GPIO46/CIRRXM/TRST# GPIO73/SCL2
67
68
SML1_CLK 20,86 <------PCH / eDP 82 MEDIA_LED2# 22
16
GPIO45/E_PWM KBSOUT11/P80_DAT
39
38 KCOL12
82 RCID GPIO51 GPIO74/SDA2 SML1_DATA 20,86 68 PWRLED# GPIO40/F_PWM KBSOUT12/GPIO64
0629 Modify: PSL_IN1 73 119 0629 Modify: 37 KCOL13
PSL_IN1_GPIO70 GPIO23/SCL3 PM_LAN_ENABLE 82 KBSOUT13/GPIO63
Rename TP_LOCK_LED#&BATT_WHITE_LED# PSL_OUT 74 120 EC_ENABLE#_1 Rename PWRLED#&PWR_BTN_LED#&CHARGE_LED#. 36 KCOL14 0709 Modify:
0702 Modify: EC_GPIO72 PSL_OUT_GPIO71 GPIO31/SDA3 PROCHOT_EC 0715 Modify: ECRST# KBSOUT14/GPIO62 KCOL15 Removed R2772 10K PH on EC_GPIO27.
75 24 85 35
Rename EC_GPIO70 to PSL_IN1 VBKUP GPIO47/SCL4 Removed PWR_BTN_LED# on KBC GPIO45. VCC_POR# KBSOUT15/GPIO61/XOR_OUT KCOL16 0714 Modify:
82 WIFI_RF_EN 82 28 34
Rename EC_GPIO71 to PSL_OUT GPIO75 GPIO53/SDA4 LCD_TST_EN 49 0720 Modify: GPIO60/KBSOUT16 USB_DET# Un-stuff D2705 and Add R2760 between EC_SMI# and
63,82 BLUETOOTH_EN 83 33
GPO76/SHBM Change MEDIA_LED2# to KBC GPIO45. GPIO57/KBSOUT17 ECSMI#_KBC already confirm with NUVOTON and SW.
19,36 S0_PWR_GOOD 84 82 E51_RxD 113 KROW[0..7] 69
GPIO77 Add AD_IA_HW on KBC GPIO66. GPIO87/CIRRXM/SIN_CR KROW0
68 TP_LOCK_LED# 91 82 E51_TxD 111 54
GPIO81 GPIO83/SOUT_CR/TRIST# KBSIN0 KROW1
110 55
C 61 USB_PWR_EN#
19,86 AC_PRESENT
36,42 IMVP_PWRGD
112
1 R2762 2EC_GPIO97 107
GPO82/IOX_LDSH/TEST#
GPIO84/IOX_SCLK/XORTR#
GPIO97
F_CS0#
F_SCK
90
92
EC_SPI_CS#_C
EC_SPI_CLK_C
2 R2736
2 R2719
1 33R2J-2-GP
1 33R2J-2-GP
SPI_CS0#_R 21,60
SPI_CLK_R 21,60
29 AMP_MUTE#
19 PCH_SUSCLK_KBC
30
77
GPIO55/CLKOUT/IOX_DIN_DIO
GPIO00/EXTCLK
KBSIN1
KBSIN2
KBSIN3
56
57
KROW2
KROW3 D2705
C
86 EC_SPI_DI_C A00 1 R2737 20R0402-PAD-2-GP 58 KROW4 1
F_SDI/F_SDIO1 SPI_SO_R 21,60 KBSIN4 22 EC_SMI#
0604 Modify: A00 0R0402-PAD-2-GP 87 EC_SPI_DO_C 2 R2722 1 33R2J-2-GP 59 KROW5
RN2704 pull-Low 10K Resistor to DY KBC_VCORF 44
F_SDIO/F_SDIO0 SPI_SI_R 21,60
R2721 1 2 43R2J-GP PECI 13
KBSIN5
60 KROW6 DY 3 ECSMI#_KBC
VCORF 5,22 H_PECI PECI KBSIN6
1 2 EC_VTT12 61 KROW7 BAS16-6-GP
on BLUETOOTH_EN. 1D05V_VTT
1
R2720 0R0402-PAD VTT KBSIN7 0714 Modify:

NOTE: 2
1
C2712 AGND Add USB_DET# on KBC GPIO57/KBSOUT17.
GND
GND
GND
GND
GND
GND
0706 Modify: SC1U10V3ZY-6GP

Locate resistors R2736,R2719 and R2722 close
C2716 NPCE795PA0DX-GP-U 83.00016.K11
2
KBC GPIO7 change to DISCRETE# to the NPCE795P. Need very close to EC 2ND = 83.00016.F11
SCD1U16V2KX-3GP
2
KBC GPIO97 change to IMVP_PWRGD. NPCE795PA0DX-GP-U
18
45
78
89
116
5
103
EC_SPI_DI_C
C2712 Need very close to EC
1
NOTE: A00
EC_AGND
ROSA Multi GPIO setting Connect GND and AGND planes via either
0R resistor or one point layout connection.
R2773
100KR2J-1-GP 22 EC_SMI# 1
R2760
2ECSMI#_KBC
2
0R0402-PAD-2-GP
0719 Modify: 1 2 0604 Modify: 3D3V_AUX_S5

Reserved 0.1uF on all of ADC input pins base on R2711 0R0402-PAD Add Pull down 100k ohm at F_SDI for Power consumption concern.
NUVOTON feedback list.(C2717~C2721)
1
ECRST#
C2719 SCD1U10V2KX-5GP 20100712 V1.5 EC_AGND R2705
CPU_THRM 2 1 MEDIA BUTTON CONTROL
C2720 DY SCD1U10V2KX-5GP
10KR2J-3-GP
USB3_PWR_ON 2 1 D2701 0709 Modify:
DY
1
C2721 SCD1U10V2KX-5GP 1 Add R2774,R2775 PH 100K to 3D3V_AUX_KBC
20 EC_SWI# EC_GPIO47 High Active
E
SYS_THRM 2 C2715 for MEDIA_BTN2#,MEDIA_BTN3#.
DY 1
DY 3 ECSWI#_KBC 2N7002K-2-GP 28,36,86 PURE_HW_SHUTDOWN# B MMBT3906-4-GP Add R2776 100K to 3D3V_AUX_KBC for PCIE_WAKE#
2
BAS16-6-GP from DEVICE to KBC.
DY
SC1U6D3V2KX-GP
EC_AGND 2 PROCHOT_EC G 0621 Modify: Q2701 KB_DET# rename to MEDIA_BTN1# on KBC GPIO26. 3D3V_AUX_KBC
C
Removed R2723
83.00016.K11 D H_PROCHOT#_EC
1 2 84.T3906.A11
H_PROCHOT# 5,40,42
1
2ND = 83.00016.F11 R2733 0R0402-PAD USB_DET#

2nd = 84.03906.F11 1 2
17 L_BKLT_EN 1 2 PANEL_BLEN R2732 S R2772 100KR2J-1-GP
R2761 0R0402-PAD D2704 MEDIA_BTN1# 1 2
100KR2J-1-GP
0630 Modify: 1 Q2702 R2770 100KR2J-1-GP

22 EC_SCI#
Removed R2762 100K 0402. 84.2N702.J31
DY
2
ECSCI#_KBC
3
BAS16-6-GP
2ND = 84.2N702.031 MEDIA_BTN3# 1 2
B 2
PCIE_WAKE#
R2775
1 2
100KR2J-1-GP
B
83.00016.K11 R2776 100KR2J-1-GP
2ND = 83.00016.F11
0714 Modify: R2757
Un-stuff D2701,D2704 and Add R2758,R2759 DQ15
1 2
ohm confirm with NUVOTON and SW.
R2758
PSL SOLUTION 10mW SOLUTION EC GPIO standard PH/PL 0722 Modify:
0R2J-2-GP
BAT54CPT-GP
20 EC_SWI# 1 2ECSWI#_KBC Add R2757 0ohm only for DQ15 stuff,
0R0402-PAD-2-GP 0712 Modify: change D2706 only for DN15 stuff. 1MEDIA_BTN1#
PSL_IN2 A00 default stuff R2756, un-stuff R2734. 3D3V_AUX_KBC
22 EC_SCI# 1 R2759 2ECSCI#_KBC RTC_AUX_S5 A00 1228 3D3V_AUX_KBC
R2734
VBACKUP 82 INSTANT_ON#
INSTANT_ON# 3
DN15 2ND =83.R2003.E81
83.00054.Q81
RN2701
0R0402-PAD-2-GP 1 R2756 2 EC_GPIO72 1 2 EC_GPIO72 0712 Modify: 2 KBC_ON#_R
10mW 0R2J-2-GP BAT_SCL Add D2706 connect to MEDIA
BAT54CPT-GP
R2704 0R0402-PAD-2-GP A00 1228 DY BAT_SDA
3
4
2
1 BUTTON Instant_on#. D2706
1 1 2 EC_GPIO72 0713 Modify:
330KR2J-L1-GP 3D3V_AUX_S5 Add R2772,D2707 for USBCHARGER BAT54CPT-GP
SRN4K7J-8-GP DETECT Function.
68 KBC_PWRBTN# 3 83.R2003.E81 R2763
2ND = 83.00054.Q81 3D3V_AUX_S5 A00 1228 RN2703 1 USB_DET#
2 C2722 AC_OK 1 R2768 2 PSL_IN1 AC_IN#_KBC 2 10mW 1 PSL_IN1 BAT_IN# 4 1
40 AC_OK
1
1 2 AC_IN#_KBC 3 2 USBDET_CON# 3 83.R2003.E81

PSL 57 USBDET_CON#
2ND = 83.00054.Q81
D2702
KBC_ON#
RN2706
SCD1U10V2KX-5GP 0R2J-2-GP
PSL R2769
100KR2J-1-GP
0R0402-PAD-2-GP
0702 Modify:
PSL_IN1 0630 Modify:
Removed LID_CLOSE#
SRN100KJ-6-GP
0723 Modify:
2 KBC_ON#_R
S
4 1 Rename EC_GPIO70 to PSL_IN1 PH 10K on RN2705. Add R2764,D2708 Base on Dell Peter request, both D2707
2
KBC_ON#_R 3 2KBC_ON#_GATE G Q2703 RN2705 13/15 Media BTN 2(Recovery Button) need
G
DMP2130L-7-GP S5_ENABLE 8 1 support bootable capability.
SRN10KJ-5-GP ECRST# 7 2
D2703 D 2ND = 84.03413.A31 6 3
2N7002K-2-GP
PSL_OUT
1
2 EC_ENABLE#_1 5 4
D
C2713 G
10mW 3 AC_IN# 40 SCD1U10V2KX-5GP DY 84.02130.031 3D3V_AUX_KBC 10mW SRN10KJ-6-GP
BAT54CPT-GP
2
D KBC_ON# 0623 Modify: 0628 Modify: 1MEDIA_BTN2#

2ND = 83.00054.Q81 1 DY Change RN2702 to R2712 10K 0402 Stuff R2712 and Removed R2805.
83.R2003.E81 3D3V_AUX_KBC 1 R2767 2 KBC_ON#_R EC_ENABLE#_1 S Resistor on FAN_TACH1. DATA_RECOVERY#
3 83.R2003.E81
3D3V_S0 82 DATA_RECOVERY#
0R2J-2-GP 2ND = 83.00054.Q81
BAT54CPT-GP KBC_ON#_R
Q2704 2
0902 X01 Modify: PSL_OUT G 84.2N702.J31 FAN_TACH1 1 2
AC_IN#_KBC Add C2722 0.1uF between Q2703 G&S pin for
2N7002K-2-GP PSL 2ND = 84.2N702.031
28 FAN_TACH1
R2712 10KR2J-3-GP D2708
fixed leakage voltage to 3D3V_AUX_KBC under G D R2766
A DC mode.
0916 X01 Modify:
Add Q2706 2N7002 to avoid leakage loop from
D S5_ENABLE S 0702 Modify:
Rename EC_GPIO71 to PSL_OUT
KBC_ON# 2 10mW 1 KBC_ON#_R
E51_RxD 1
DY 2
A
3D3V_S5 to 3D3V_AUX_KBC issue when 10mW 0R0402-PAD-2-GP R2708 10KR2J-3-GP
S Q2705
latched fail timing. 2N7002K-2-GP A00 1228
Q2706 84.2N702.J31 <Core Design>
84.2N702.J31 2ND = 84.2N702.031
2ND = 84.2N702.031
BLUETOOTH_EN 1
DY 2 Wistron Corporation
R2709 10KR2J-3-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
NOTES: Taipei Hsien 221, Taiwan, R.O.C.
0623 Modify:
Please make sure there's no pull-down resistor on USB_PWR_EN#,AC_PRESENT,E51_TXD. Change RN2704 to R2708 10K 0402 Title
Resistor on BLUETOOTH_EN.
0604 Modify: KBC Nuvoton NPCE795
RN2704 pull-Low 10K Resistor to DY Size Document Number Rev
A2
on BLUETOOTH_EN. QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
0705 Modify:
SSID = Thermal Thermal sensor P2800

R2802 change to 0ohm 0402 from
short pad and default un-stuff. Fan controller P2793
R2802 0R2J-2-GP U2802
1 DY 2 FON# 1 8
3D3V_DAC_S0 FON# GND 5V_S0
5V_S0 2 VIN GND 7
FAN_VCC 3 6
1119 X02 Modify: VO GND
27 FAN1_DAC 4 VSET GND 5
Change U2801,U2804,U2805 VCC power to *Layout* 10 mil
1
3D3V_DAC_S0 from 3D3V_S0.
P2800A1 R2803 G991P11U-GP
D 3D3V_DAC_S0 107KR2F-GP For linear FAN 74.00991.031 D
1
2nd = 74.02793.A31 C2803 C2804
2
1
C2802 3rd = 74.05606.A71
87.1 Degree
SC4D7U6D3V3KX-GP
ADJ A00 1224
SCD1U10V2KX-5GP
2
2
2
SCD1U10V2KX-5GP
1
P2800A1 A00 1227
1
R2804 C2805 0614 Modify:
SCD1U10V2KX-5GP
226KR2F-GP 1111 X02 Modify: Change FAN1 connector part number to
P2800A1 ADJ&ADJ_VGA power source change to 3D3V_DAC_S0 20.D0210.103 base on ME EMN and DXF.
2
from 3D3V_S0 to solve T8 shut down issue. 0712 Modify:
2
Change FAN1 part number to 20.F1639.004
1227 A00 Modify: from 20.D0210.103 base on latest EMN and DXF.
Layout notice : If stuff P2800EA1 then must stuff R2803,R2804,C2805 but if stuff P28003B0 should be unstuff.
Both DXN and DXP routing 10 mil
trace width and 10 mil spacing. 0628 Modify:
Stuff R2712 and Removed R2805.
P2800_DXP
P2800EA1-GP 5
1
2ND = 84.03904.P11 1 2 FAN_TACH1_C 3

27 FAN_TACH1
3
1
84.03904.L06 C2806 5 4 R2807 0R0402-PAD 2
Q2801 VCC TDR SYS_THRM 27
SC470P50V3JN-2GP C2807
DY 1 6 3 CPU_THRM 27
2
PMBS3904-1-GP SC2200P50V2KX-2GP DXP TDL FAN_VCC

7 2 *Layout* 15 mil 1
2
THERM_SYS_SHDN#_OTZ DXN GND ADJ
8 1 4
2
P2800_DXN OTZ ADJ
2
R2808 FAN1
NTC-100K-8-GP 2.System Sensor, Put on palm rest U2801 D2802 ACES-CON3-11-GP
1
C 1117 X02 Modify: 1.H/W T8 Shutdown C2809 C2810 C
Rename U2801&U2804 pin 8 to 0831 20.F0772.003
2nd = 20.F1841.003
SC2200P50V2KX-2GP
SC4D7U6D3V3KX-GP
THERM_SYS_SHDN#_OTZ from THERM_SYS_SHDN#. 74.02800.A71 CH551H-30PT-GP DY
2
83.R5003.C8F
AFTP2801 1FAN_TACH1_C 0724 Modify: 1110 X02 Modify:
Removed C2808 0.1uF. 2ND = 83.R5003.H8H Add 2nd 20.F1841.003 on FAN1 from
AFTP2802 1FAN_VCC ME updated connector list.
3rd = 83.5R003.08F
X02 1118
R2805 A00 1228 3D3V_S0
THERM_SYS_SHDN#_OTZ
1 2
0R2J-2-GP
1
1117 X02 Modify: R2809
Add R2805 0hm between THERM_SYS_SHDN#_OTZ 100KR2J-1-GP
and THERM_SYS_SHDN#.
Q2802
2
S THERM_SYS_SHDN#
27,36,86 PURE_HW _SHUTDOW N# D
G 3D3V_S0
EMI/ESD
1
C2811
2N7002K-2-GP
DY
SCD1U10V2KX-5GP
84.2N702.J31 0709 Modify:
2
FAN_VCC Removed R2811 and connect
B 2ND = 84.2N702.031 3D3V_S0 to Q2802.G directly. B
1
EC2801
X02 1111
DY
SCD1U16V2KX-3GP
2
A00 1228 un-stuff U2805 G709T1UF related circuit and R2812 then stuff R2805 3D3V_DAC_S0
1111 X02 Modify:
Reserved G709T1UF for T8 solution
24K3R2F-1-GP U2805 sync with DN13. R2801
R2806
1 DY 2 U2805_1 1 SET VCC 5 U2805_5 2 DY 1
1
2 GND DY C2817 150R2F-1-GP
THERM_SYS_SHDN#
1 DY 2 3 OUT# 4 DY SCD1U10V2KX-5GP
R2812 0R2J-2-GP HYST
2
G709T1UF-GP R2810 3D3V_DAC_S0
U2805_4 2 DY 1
74.00709.A7F R2811 0R2J-2-GP
20101019 X01: 2 DY 1 A00 1224
Reserve U2804 for PURE_HW_SHUTDOWN# test. 0R2J-2-GP Hysterisis:
20101020 X01: 10C for HYST= VCC
Reserve R2810 to 3D3V_S0 and R2811 to GND for HYST. 2C for HYST=GND
A00 1228 Cancel VGA Thermal sensor P2800 circuit
A <Core Design> A
1111 X02 Modify:

ADJ&ADJ_VGA power source change to 3D3V_DAC_S0
from 3D3V_S0 to solve T8 shut down issue.
Wistron Corporation
Title
Thermal P2800/Fan Controllor P2793

A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
AUD_SPK_R+ 5V_S0 +PVDD 5V_S0

SSID = AUDIO For EMI AUD_SPK_R-
AUD_SPK_L-
AUD_SPK_R+
AUD_SPK_R-
AUD_SPK_L-
58
58
58
+AVDD
AUD_SPK_L+ 1 R2903 2
AMP_MUTE# +PVDD AUD_SPK_L+ 58
27 AMP_MUTE# 1 R2902 2 0R0603-PAD
AUD_DMIC_CLK +AVDD 0R0603-PAD
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U6D3V5MX-3GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2905
C2906
C2908
C2909
C2910
AUD_DMIC_IN0
1
AUD_VREG
1 R2904 2
1
0R0603-PAD
2
EC2901 EC2902 Close to codec
2
SC22P50V2JN-4GP AUD_DVDDCORE
41
40
39
38
37
36
35
34
33
32
31
D D
SC22P50V2JN-4GP U2901
PORTD_-L
PORTD_+L
AVDD2
THERMAL_PAD
EAPD
PVDD
PORTD_+R
PORTD_-R
PVDD
PVSS
VREG/+2_5V
C2901
SC10U6D3V5MX-3GP
2
1122 X02 Modify: PUMP_CAPP
change R2920,R2921 to 22ohm from 0ohm and
2
stuff EC2901,EC2902 22p from EMC Neo updated.
CLOSE TO CODEC
C2914
1 30 SC2D2U10V3KX-1GP
1
AUD_DMIC_CLK_R DVDD_LV CAP+ PUMP_CAPN
2 DMIC_CLK/GPIO_1 CAP- 29
3D3V_S0 AUD_DMIC_IN0_R 3 28 AUD_V_B
HDA_CODEC_SDOUT DMIC_0/GPIO_2 V-
21 HDA_CODEC_SDOUT 4 SDATA_OUT AVSS2 27
HDA_CODEC_BITCLK 5 26 AUD_HP1_JACK_R R2906 1 2 60D4R2F-GP
21 HDA_CODEC_BITCLK BITCLK PORTB_R AUD_HP1_JACK_R2 82
Close to codec 21 HDA_SDIN0 1R2901 2HDA_CODEC_SDIN0 6 SDATA_IN PORTB_L 25 AUD_HP1_JACK_L R2905 1 2 60D4R2F-GP AUD_HP1_JACK_L2 82
33R2J-2-GP 7 24
HDA_CODEC_SYNC DVDD AVSS2 AUD_EXT_MIC_R C2922
21 HDA_CODEC_SYNC 8 SYNC 71.92H87.A03 PORTA_R 23 2 1 SC1U10V3KX-3GP MIC_IN_R 82
HDA_CODEC_RST# 9 22 AUD_EXT_MIC_L C2921 2 1 SC1U10V3KX-3GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
21 HDA_CODEC_RST# RESET# PORTA_L MIC_IN_L 82

1
2
C2903
C2904
C2902
AUD_PC_BEEP 10 21 +AVDD
PCBEEP AVDD1
VREFOUT_C
VREFOUT_A
Put C2921 and C2922 close to codec
2
PORTC_R
VREFFILT
PORTF_R
SENSE_A
SENSE_B
PORTC_L
PORTF_L
0707 Modify:
updated U2901 part number from data base.
CAP2
AUD_CAP2
92HD87B1A5NDGXTBX8-GP AUD_VREFFLT
11
12
13
14
15
16
17
18
19
20
A00
2010/06/30 Change to 92HD87 (71.92H87.A03)
AUD_V_B
C C
RN2902 AUD_VREG
AUD_VREFOUT_B
1 4 AUD_DMIC_IN0_R
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC4D7U6D3V3KX-GP
AUD_SENSE_A
AUD_SENSE_B
AUD_PC_BEEP
AUD_VREFFLT
49 AUD_DMIC_IN0 AUD_DMIC_CLK_R
2 3
SC1U6D3V2KX-GP
49 AUD_DMIC_CLK
C2917
C2918
C2915
C2916
AUD_CAP2
1
SRN22J-7-GP 0707 Modify:
3D3V_S0 Change R2911,R2914,R2917 change
20101220 R2920 R2921 for change to parallel resistor to 0ohm 0603 from short pad.
2
0726 Modify:
Removed all of AUD_AGND and R2911,R2914,R2917.
1
AUD_VREFOUT_B
R2908
10KR2J-3-GP
Close to codec
2
AMP_MUTE#
AUD_VREFOUT_B
120KR2J-L-GP From SB
HDA_CODEC_BITCLK R2909
AUD_PC_BEEP C2912 2 1 SCD1U10V2KX-5GP SB_SPKR_R 1 2 HDA_SPKR 21
C2913 2 1 SCD1U10V2KX-5GP KBC_BEEP_R 1 2 0719 Modify:
AUD_PC_BEEP KBC_BEEP 27
1
0,&,1
R2910 470KR2J-2-GP Move RN2901 to closed AUDIO CODEC from speaker connector.
2
C2923
SC1U10V2KX-1GP DY C2907
SC4D7P50V2CN-1GP
Trace width>15 mils G2901
From EC
2
DUMMY-C2
B AUD_VREFOUT_B B
1
2
1
RN2901
SRN4K7J-8-GP
3
4
$]DOLD,)(0,
HDA_CODEC_SDOUT
82 MIC_IN_L
1
R2912
47R2J-2-GP
DY +AVDD +AVDD 82 MIC_IN_R
R2913
2
1 2 AUD_HP1_JD# 82
1
1
PCH_AZ_CODEC_SDOUT1
R2915 20KR2F-L-GP R2916

2K49R2F-GP 2K49R2F-GP
2
A AUD_SENSE_A AUD_SENSE_B <Core Design> A

1
1
R2918
C2919 20KR2F-L-GP Wistron Corporation
SC1000P50V3JN-GP-U R2919 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2
2 1 Taipei Hsien 221, Taiwan, R.O.C.

2
EXT_MIC_JD# 82
1
C2920 39K2R2F-L-GP Title

DY SCD1U10V2KX-5GP Audio Codec 92HD87B1
2
Close to Pin13 Size Document Number Rev

Close to Pin14 A3 A00
QUEEN 15
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
SSID = SDIO
48MHz clock input trace of characteristic impedance (Zo) must be 50 3D3V_CARD_S0
15%. 3D3V_CARD_S0
20 CLK_PCH_48M
1
PCH GPIO67(48M) confirm with SW C3206 C3207
SCD1U10V2KX-4GP SC4D7U6D3V3KX-GP
2
XD_D7 XD_D7 74
SP14 SP14 74
SP13 SP13 74
SP12 SP12 74
C SP11 SP11 74 Close to chip C
C3201
1 RREF U3201
DY2
24
23
22
21
20
19
RTS5138-GR-GP
3D3V_S0 SC100P50V2JN-3GP
XD_D7
SP14
SP13
SP12
SP11
CLK_IN
1 R3201 2
6K2R2F-GP 1 18 SP10 SP10 74
USB_PN5_R RREF SP10
2 17
MAX 0.4A USB_PP5_R 3
DM GPIO0
16 SP9 SP9 74
DP SP9 SP8
4 3V3_IN SP8 15 SP8 74
3D3V_CARD_S0 5 14 SP7 SP7 74
V18 CARD_3V3 SP7 SP6
6 13
DY V18 SP6 SP6 74
2
XD_CD#
1
C3203 C3204 C3202
SP1
SP2
SP3
SP4
SP5
SCD1U10V2KX-4GP SC4D7U6D3V3KX-GP SC1U10V2KX-1GP 25
1
GND
2
71.05138.003
7
8
9
10
11
12
SP5 SP5 74
SP4 SP4 74
SP3 SP3 74
SP2
The maximum range of the PMOS output current SP1
SP2
SP1
74
74
XD_CD#
1. xD-Picture Card: 250mA XD_CD# 74
2. SD/MMC Card: 250mA

B B
3. MS/MSPRO/Duo-HG: 250mA
The pin2 / pin3 (DM/DP) of RTS5138 chip trace layout
with differential characteristic impedance (Zdiff) is 90[
POWER TRACE 10%
R3211
1.RTS5138: pin 4 (3V3_IN) trace fixed width is 30 mils (minimum). 1 2 USB_PP5_R
18 USB_PP5
2.RTS5138: pin 5 (CARD_3V3) trace fixed width is 30 mils (minimum). 0R0402-PAD-2-GP
3.RTS5138: pin 6 (V18) trace fixed width is 12 mils (minimum).
Keep the trace routing lengths as short as possible. A00 1229
4.RTS5138: pin 1(RREF) trace fixed width is 12 mils (minimum). 0917 X01 Modify:
stuff TR3201 and un-stuff R3211,R3210
5.RTS5138: pin 1(RREF) trace must far away 48MHz clock trace. at X01 stage from EMC Neo suggestion.
6.De-coupling and Bulk capacitor should place near to RT5138 chip and Combo Socket.
7.It is recommended that use of ferrites bead on power trace.
R3210
8.Via size: Pad>=32 mils, Finished hole>=16 mils. 18 USB_PN5 1 2 USB_PN5_R
0R0402-PAD-2-GP
<Core Design>
A A
Wistron Corporation
Title
Size
Card Reader-RTS5138
Document Number Rev
A3
QUEEN 15 A00
5 4 3 2 1
A B C D E
4 4
3 3
(Blanking)
2 2
1 <Core Design> 1
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
A B C D E
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
0723 Modify:
0628 Modify: Default stuff R3622 PH Resistor to fix Annie
Removed R3609,R3610,R3613,C3613 and Stuff R3614. demo board abnormal issue from Annie team
A00 updated.
27,42 IMVP_PW RGD 1 R3614 2 SYS_PW ROK
R3622
SSID = Reset.Suspend
1
Q3603 0R0402-PAD-2-GP 1D05V_VTT 2 1 H_THERMTRIP# 5,22
PS_S3CNTRL G C3612 DY
SCD01U50V2KX-1GP 56R2J-4-GP
2
D
E
S 5,22 H_CPUPW RGD 1 R3601 2 H_PW RGD_R B DY Q3601
1KR2J-1-GP
84.2N702.J31 DY
1
2N7002K-2-GP CHT2222APT-GP
C
A00 1228 stuff Q3603 2nd = 84.2N702.031 C3602 DY
SCD1U10V2KX-5GP
D D
2
Power Sequence
2
19,27 S0_PW R_GOOD 3
1 SYS_PW ROK 19 2ND = 83.00016.F11

D3602 83.00016.K11
BAS16-6-GP BAS16-6-GP
83.00016.K11 2
2ND = 83.00016.F11
3 PURE_HW _SHUTDOW N# 27,28,86
0628 Modify:
Utilize D3602 Diode instead of U3603 AND GATE 1
for SYS_PWROK sequnece control. 41 3V_5V_EN
D3601
200KR2J-L1-GP
1
1 2 S5_ENABLE 27
R3602
R3603 1KR2J-1-GP
DY
0621 Modify:
2
ROSA Run Power Change R3603 to 1K from 2K 0402.
15V_S5
AO4468 MAX 9A
Rds(on) = 18.5mOhm
2nd = 84.08882.037
5V_S0
5V_S5 84.04468.037 5V_S0
2
C AO4468-GP C
+5V_RUN Comsumption
R3604 5 4
100KR2J-1-GP 6
D G
3
Peak current 7.73A
D S
7 D S 2
8 1
1
D S
1
U3601
1 R3605 2 5V_RUN_ENABLE C3603
3D3V_AUX_S5 10KR2J-3-GP SC10U10V5ZY-1GP
2
1
C3608
SCD01U50V2KX-1GP
PS_S3CNTRL 37
2
1 R3606 2 PS_S3CNTRL
100KR2J-1-GP
D G S
6
Rds(on) = 18.5mOhm
Q3602 AO4468 MAX 11.6A
2N7002KDW -GP
2nd = 84.08882.037
3D3V_S0 3D3V_S0
84.2N702.A3F
1
3D3V_S5 84.04468.037 3D3V_S0
1
2nd = 84.DM601.03F AO4468-GP

+3.3V_RUN Comsumption DY
SCD1U50V3KX-GP
S G D 5 4
Peak current 8.14A 0719 Modify:
2
D G
EC3601
6 3
7
D
D
S
S 2 Reserved EC3601 0.1uF near
8 1 C3604 for EMC NEO suggestion.
1
D S
B 19,27,37,47,75 PM_SLP_S3# U3602 B
C3604
RUN_ENABLE 1 R3607 2 3.3V_RUN_ENABLE SC10U6D3V5KX-1GP
2
10KR2J-3-GP
1
C3605
SCD01U50V2KX-1GP
2
0615 Modify:
Removed R3626,R3628 0ohm 0805 Resistor,
they are unnecessary for this power rail.
Removed R3627,R3629 0ohm 0805 Resistor for 1D5V_DDR_S0.
1D5V_S3 1D5V_S0
1.5V_RUN for VGA Comsumption 1D5V_S0
Peak current 7.39A TPCA8062-H-GP MAX 28A
Rds(on) = 4.1~5.4m OHM MAX Current ? mA
+1.5V_RUN_CPU Comsumption Design Current ? mA
Peak current 3A U3606
8 D S 1 Total= 11.39A
+1.5V_RUN for Mini-Card Comsumption 7 D S 2
6 D S 3
Peak current 1A
1
5 D G 4
C3609
<Core Design>
A TPCA8062-H-GP SC10U6D3V5KX-1GP A
2
1 R3630 2 1.5V_RUN_ENABLE
10KR2J-3-GP
84.08062.037 Wistron Corporation
1

C3610 2nd = 84.00460.037 Taipei Hsien 221, Taiwan, R.O.C.
SCD01U50V2KX-1GP 3rd = 84.00312.037
2
Title
0713 Modify:
Change U3606 part number to 84.08062.037
from 84.04468.037.
Power Plane Enable
0827 Add 2nd and 3rd. A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
Close to DIMM
S3 Power Reduction Circuit SM_DRAMPWROK
0D75V_S0 1D5V_S0
1
Close to CPU
D S3 Power Reduction Circuit Processor VREF_DQ Implementation
R3707
R3703
22R2J-2-GP 2 DY
R3704
220R2J-L2-GP D
0R2J-2-GP
Q3702_D2
1 DY 2
Q3701_D
0629 Modify 0629 Modify
Q3708
S +V_SM_VREF_CNT 9
D
D
2
M_VREF_DQ_DIMM0 1 2 +V_SM_VREF D Q3702
R3708 0R0402-PAD R3705 Q3701 2N7002K-2-GP
G 100KR2J-1-GP 2N7002K-2-GP
DY 84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
1
2N7002K-2-GP
2ND = 84.2N702.031
0706 Modify: 84.2N702.J31
S
Removed Q3707,R3717 and connect
2ND = 84.2N702.031
S
RUN_ENABLE to Q3708.G directly
same as EV board.
RUN_ENABLE PS_S3CNTRL
36 PS_S3CNTRL
C C
Close to CPU
5 S3 Power Reduction X01 20091111 S3 Power Reduction Circuit SM_DRAMPWROK
1D5V_S3
1
2N7002K-2-GP R3706
1KR2J-1-GP
0730 36 PS_S3CNTRL G 1.05VTT_PW RGD 45,48
2
D 0D75V_EN R3709 2
DY1 0R2J-2-GP
1
0908 X01 Modify: Q3703
S
R3710 Stuff Q3704,R3710; un-stuff R3716. 2N7002K-2-GP
S3 Power Reduction Circuit
Q3704 0R0402-PAD-2-GP U3701 pin2 change to 1.05VTT_PWRGD from SM_DRAMRST#
A00 RUNPWROK.
84.2N702.J31 5 SM_DRAMRST# S
2ND = 84.2N702.031
2
D SM_DRAMRST#_D
1 R3718 2 DDR3_DRAMRST# 14,15
1KR2J-1-GP
1
19,27,36,47,75 PM_SLP_S3# 1
R3716
DY 22R2J-2-GP
2 0D75V_EN 46 G
C3702
84.2N702.J31 SC100P50V2JN-3GP
2
2ND = 84.2N702.031
1
C3705 DRAMRST_CNTRL_PCH 20
DY SCD1U10V2KX-5GP
2
B C3703 B
2 1DRAMRST_CNTRL_PCH
SCD047U16V2KX-1-GP
0709 Modify:
Change U3701 pin1,5 to 3D3V_S0 from 3D3V_S5. Close to CPU
S3 Power Reduction Circuit SM_DRAMPWROK
3D3V_S0
1D5V_S0
X02 1111 3D3V_S0
1
CEKLT V1.0: PCH to 1K,CUP to 200R

1
R3713
200R2F-L-GP
PUSH PULL R3702
U3701 DY 200R2F-L-GP
2
5,19 PM_DRAM_PW RGD 1

2
5 R3719
0D75V_EN 2
4 VDDPW RGOOD_R 1 2 VDDPW RGOOD 5
0920 3
TC7SZ08FU-2-GP 910R2F-GP
1
1110 X02 Modify:

R3720 Change U3701 1st to 73.7SZ08.EAH;2nd to
73.7SZ08.EAH 750R2F-GP 73.01G08.L04;3rd to 73.7SZ08.DAH from
Sourcer Eason updated.
2nd = 73.01G08.L04
2
A 3rd = 73.7SZ08.DAH DN15ATI A
R3717 0709 Modify:

5,19 PM_DRAM_PW RGD 1 2 VDDPW RGOOD_R
DY 0R2J-2-GP U3701 change to OD type 73.01G09.AAH.
0723 Modify:
Wistron Corporation
Change U3701 to push pull type 73.01G08.L04. Taipei Hsien 221, Taiwan, R.O.C.
0827 R3720 change to 910ohm 0402.
R3719 change to 750ohm 0402. Title
default un-stuff R3702.
SM_DRAMPWROK must have a maximum of 15ns rise or fall time
over VDDQ * 0.55 200mV and the edge must be monotonic ADAPTER
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Support
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Size Document Number

DCIN Rev
A3 QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
Batt Connecter
1SMA18AT3G-GP
BT+
K
D D
1
G3901
PD3902
2 1 C3902 C3901
40 BATT_SENSE SCD1U50V3KX-GP SC2200P50V2KX-2GP DY BATT1
2
GAP-CLOSE-PW R-3-GP 10
A
0714 Modify: 1
Merge R3902~R3904 to PRN3901 33ohm. PN3901 A00 1224
1 8 2
2 7 PBAT_SMBCLK1 3
27,40 BAT_SCL
3 6 PBAT_SMBDAT1 4
27,40 BAT_SDA
4 5 PBAT_PRES1# 5
27 BAT_IN#
6
SRN33J-7-GP AFTP3901 1 BAT_ALERT 7
8
9
EC3901 EC3902 11
SC10P50V2JN-4GP
SC10P50V2JN-4GP
1
1
ALP-CON9-2-GP-U
DY DY 20.81316.009
2
0701 Modify:
2nd = 20.81440.009
Removed D3904 ESD Diode on BAT_IN#.
3rd = 20.81328.009
DCBATOUT
EC3903
SCD1U50V3KX-GP
1
C C
AFTP3902 1 PBAT_PRES1#
AFTP3903 1 PBAT_SMBDAT1
2
AFTP3904 1 PBAT_SMBCLK1
AFTP3905 1 BT+
1122 X02 Modify:

stuff EC3903 0.1uF from
EMC Neo suggestion.
For actual location, need to be swap all pin
Close to Batt Connector
B B
BAT_IN#
BAT_SDA
BAT_SCL
3
3
D3901
D3902 D3903 BAV99-5-GP-U
BAV99-5-GP-U BAV99-5-GP-U
1
2
1
83.00099.T11
83.00099.T11 83.00099.T11 2nd = 83.00099.K11
2nd = 83.00099.K11 2nd = 83.00099.K11
3rd = 83.BAV99.D11
3rd = 83.BAV99.D11 3rd = 83.BAV99.D11 3D3V_AUX_KBC
A <Core Design> A
0930 X01 Modify:
Change D3901~D3903 main source to 83.00099.T11
for 83.BAV99.D11 shortage issue.
Wistron Corporation
Title
BATT CONN
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
0719 Modify:
SSID = Charger Id=-12A
Reserved EC4006 0.1uF near PR4002
for EMC NEO suggestion. 0719 Modify:
Qg=-25nC AD+_TO_SYS Reserved EC4007 0.1uF near PG4006
Rdson=10~38mohm DCBATOUT
D
PU4002
S
PR4002 for EMC NEO suggestion. BT+
AD+ 8 1 PU4003
7 D S 2 1 2 1 S D 8
6 D S 3 2 S D 7
D01R2512F-4-GP
EC4006
SCD1U50V3KX-GP
EC4007
SCD1U50V3KX-GP
5 D G 4 0720 Modify: 3 S D 6
1
Add AD_IA_HW related circuit AD+ G D
PR4003
4 5
100KR2J-1-GP
AO4407A-GP from TOM suggestion. A00 1222 GAP-CLOSE-PW R-3-GP
1
PQ4003_D AO4407A-GP
D
84.04407.F37 PG4002 D
2
1
2nd = 84.04835.H37 PR4035 PG4003
84.04407.F37
2
2
1
10KR2J-3-GP
AD+_G_2 GAP-CLOSE-PW R-3-GP
300KR2F-L-GPPW R_CHG_REF
PG4001
PG4006
PG4004
PG4005
PR4006
PR4004
2nd = 84.04835.H37
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
2
2
470KR2J-2-GP
1
A00 1222 A00 1222
DY
10KR2F-2-GP
1
AD+ PR4047
PR4524_03
PR4005
Id=-12A
1PR4533_02
2 1
1
2
PQ4003 174KR2F-GP 0723 Modify:
DC_IN_D
2N7002K-2-GP PR4007 Removed PR4038 PH. Qg=-25nC

PQ4001
84.2N702.J31 A00 1222 0R2J-2-GP Rdson=10~38mohm
2
AD+_G_1
3 4 2ND = 84.2N702.031 5,27,42 H_PROCHOT#
1
PW R_CHG_ACOK 2 5 PR4031 PR4008 PR4010
316KR3F-2-GP
0917 X01 Modify:

150KR2F-L-GP 0R0402-PAD 0R0402-PAD A00 1222
S
1
1 6 A00 1222 Change PR4008,PR4010 to 0R0402 PU4004
1
short pad from 0ohm.
PR4009
Id=12A
2
2N7002KDW -GP 1 PR4034 2PQ4003_G PR4032
ICREF
27 AD_IA_HW PW R_DCBATOUT_CHG
84.2N702.A3F 1 2 0R0402-PAD-2-GP Qg=3.8nC
2nd = 84.DM601.03F 0R0402-PAD-2-GP PC4002
SCD1U50V3KX-GP
Rdson=24~30mohm
2
CHG_AGND SCD1U50V3KX-GP
SC2200P50V2KX-2GP
2
PR4033 CHG_AGND PW R_DCBATOUT_CHG
SC1U6D3V2KX-GP
1
PC4004
1 2
2
CHG_AGND PC4005
EC4001
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
ICREF
1
20R5F-1GP PW R_CHG_DCIN PW R_CHG_CSSP 1
PC4006
PC4007
PC4008
PC4009
0818 1 2 22 DCIN CSSP 28 2
1
EC4002
PR4013
33R3J-2-GP
DY
5
6
7
8
PC4003 PW R_CHG_ACIN 2 SCD1U50V3KX-GP
DY
SCD1U25V2KX-GP
SIS412DN-T1-GE3-GP
2
ACIN
D
D
D
D
SCD47U50V5KX-1GP PW R_CHG_CSSN CHG_AGND
PU4004
0827 3D3V_AUX_KBC 27
DY
2
0702 Modify: CSSN PW R_CHG_ICOUT
11 VDDSMB ICOUT 26
Change PR4014 from 48.7K to 49.9K 0707 Modify:
PD4001
2
C 0402 base on power team suggest. Change PR4012 change to 0ohm 0402 from short pad. C
Charger Current=1.4~3.6A
49K9R2F-L-GP
CHG_AGND
1
PC4001 25 PW R_CHG_BOOT
1 PR4017 2PW R_CHG_BST1
K A 1 2
BOOT
1
G
S
S
S
SCD1U10V2KX-5GP PW R_CHG_VDDP 0R0603-PAD PC4011
PC4010
21
SCD01U50V2KX-1GP
VDDP 0603 Modify:

1 PR4012 2 PW R_CHG_ACOK SD103AWS-1-GP SCD1U50V3KX-GP
PR4014
13 ACOK
2
4
3
2
1
0R0402-PAD change PL4001 to 68.5R610.10X. BT+
83.1R504.A8F
2
AC_OK CHG_AGND 24 PW R_CHG_UGATE 2nd = 83.1R504.B8F

UGATE 84.00412.037
1
PW R_CHG_SCL PC4013 BT+_R
27,39 BAT_SCL 2 1 10 SCL 1 2 2nd = 84.08061.A37 PL4001
2
PG4007 GAP-CLOSE-PW R-3-GP PC4012 SC3300P50V3KX-1GP PR4019

23 1 PR4018 2 SCD1U50V3KX-GP DY PW R_CHG_LX1 1 2 1 2
2
PHASE 0R0603-PAD IND-5D6UH-48-GP-U1 D01R2512F-4-GP
PW R_CHG_PHASE
2 1 PW R_CHG_SDA 9 1 2
DY 68.5R610.10X
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
27,39 BAT_SDA SDA
PG4008 GAP-CLOSE-PW R-3-GP 20 PW R_CHG_LGATE PC4014 2nd = 68.5R610.10U
SCD1U50V3KX-GP
CHG_AGND LGATE SC220P50V2JN-3GP
PC4015
PC4016
PC4017
PC4018
PC4019
68.5R610.10X
5
6
7
8
1
SIS412DN-T1-GE3-GP
Id=5.5A
D
D
D
D
PG4010
PG4009
PU4005
14 NC#14 PGND 19
PR4001 DCR=39~42mohm
2
SCD1U50V3KX-GP
1 2 0720 Modify: 18 PW R_CHG_CSOP
27 AD_IA 84.00412.037 Size=6.6X7.3X3
1
Change PR4001 to 20K from 0ohm CHG_AGND CSOP
20KR2J-L2-GP base on power team Brian updated. PW R_CHG_CSON
2
CSON 17 2nd = 84.08061.A37
G
S
S
S
PW R_CHG_VICM 8 84.00412.037
4K7R2J-2-GP
PW R_CHG_FBO VICM 0629 Modify
PC4020
SC220P50V2JN-3GP
Id=12A
4
3
2
1
PR4022 PG4009_1
1
PR4021
1
2
200KR2F-L-GP Qg=3.8nC
8K45R2F-2-GP
1 2 PR4024
SCD1U50V3KX-GP
Rdson=24~30mohm
PR4025
6 0R0402-PAD
CHG_AGND
1PWR_CHG_FBO1
PW R_CHG_EAI FBO BT+

1 PR4023 2 PW R_CHG_CSOP_1
PC4024
5 EAI NC#16 16
PC4022 PW R_CHG_EAO 4 0R0402-PAD
PR4026
2
1
EAO
1
2
SC2200P50V2KX-2GP PW R_CHG_REF 3
SC10U25V6KX-1GP
7K5R2F-1-GP VREF
1
1PR4526_01 PW R_CHG_CE 0707 Modify:
PC4023
1 2 2 2 1 7 CE
B Change PR4023 change to 0ohm 0402 from short pad. B
1 PR4027 2
PC4034
12 15
DY
GND
1
GND VFB
1
PC4021 0R0402-PAD
PC4030
SCD1U10V2KX-5GP
PC4025
2
SC150P50V2JN-3GP 1 2 PW R_CHG_VFB1 PR4028 2

BATT_SENSE 39
2
PU4001 0R0402-PAD 0721 Modify:

1
DY
SCD1U50V3KX-GP
PC4026 PC4027 SC56P50V2JN-2GP PC4029
29
2
1
2
BQ24745RHDR-GP Change PU4005 to 84.00412.037
PC4031
DY
SC1U6D3V2KX-GP
DY
SCD1U50V3KX-GP
SCD01U50V2KX-1GP
from power team Brian updated.

DY
2
1
PC4028
2
DY
2
1
1
1 PR4029 2
1K8R6J-GP
SCD01U50V2KX-1GP 0R0402-PAD PC4032
PR4030
This Resistor DY DY 0603 Modify:
SCD1U25V2KX-GP
2
must be 1% PQ4004_D Add PC4034 to 78.10622.52L.
2
1
tolerance. CHG_AGND 1 PR4020 2 CHG_AGND

0917 X01 Modify: PR4036 0R0402-PAD
Change PR4027 to 0R0402 76K8R2F-GP
short pad from 0ohm. A00 1222 CHG_AGND CHG_AGND
D
0625 Modify: PQ4004 0916 X01 Modify: CHG_AGND

Reserved EC4003,EC4004 on DC_IN_D&PWR_CHG_ACOK for 2N7002K-2-GP Reserved PQ4004,PR4036,PR4037 for
EMC NEO suggestion. AD_IA_HW2 function.
0719 Modify: 84.2N702.J31 0701 Modify:
Reserved EC4005 0.1uF near PR4004 for EMC NEO suggestion. ICREF Change PQ4002 to single 2N7002.
Reserved EC4008 0.1uF near PC4017 for EMC NEO suggestion. 2ND = 84.2N702.031
EMI/ESD A00 1222 A00 1222 Q4001

G
27 AD_IA_HW 2 1PR4037 2PQ4004_G AC_IN# to KBC S

DC_IN_D PW R_CHG_ACOK AD+ BT+
0R0402-PAD-2-GP D
CHG_AGND 27 AC_IN#
A <Core Design> A
2
EC4005
SCD1U50V3KX-GP
EC4008
SCD1U50V3KX-GP
G AC_OK
1
EC4004 EC4003 PC4033

PW R_CHG_REF SCD1U10V2KX-5GP DY
DY DY DY Wistron Corporation
1
2N7002K-2-GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
84.2N702.J31 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

2 PR4011 1 AC_OK Taipei Hsien 221, Taiwan, R.O.C.
AC_OK 27 2ND = 84.2N702.031
Title
10KR2F-2-GP
CHARGER BQ24745
A3
QUEEN 15 A00
5 4 3 2 1
A B C D E
SSID = PWR.Plane.Regulator_5v3p3v
PWR_3D3V_LGATE2 1 PR4102 2 PWR_3D3V_LGATE2_1

0R0402-PAD
SCD1U25V3KX-GP
SCD1U25V3KX-GP
SC1KP50V2KX-1GP
1
PC4104
PC4102
PC4103
1
2
2
PD4102
BAT54-7-F-GP
2
4
PWR_5V_ENTRIP1 PWR_3D3V_ENTRIP2 DY 4
ROSA team PD4103_3 PD4101_3
187KR2F-GP
3
1
1
0629 Modify 0629 Modify
3
PR4104
PR4103
PC4105 DY
SC18P50V2JN-1-GP PC4106 DY PD4103 PD4101
147KR2F-GP
2
SC18P50V2JN-1-GP BAT54S-7F-GP BAT54S-7F-GP
2
83.00054.Y81
2
2nd = 83.0R203.081
1
15V_S5 15V_PWR 5V_S5
83.00054.Y81 DCBATOUT
PG4101 2nd = 83.0R203.081 0810 PWR_5V_DCBATOUT
0603 Modify: GAP-CLOSE-PWR-3-GP
Change PR4103 to 187K from 100K.
1 2 PC4108_1
0629 Modify PG4105 GAP-CLOSE-PWR
1 2
1
PC4107
PD4104 SC1U25V3KX-1-GP PC4108 PC4109
BZT52C15S-GP SCD1U25V3KX-GP SCD1U25V3KX-GP PG4106 GAP-CLOSE-PWR
2
83.15R03.C3F 1 2
2nd = 83.15R03.E3F
A
PG4127 GAP-CLOSE-PWR
1 2
DCBATOUT PWR_3D3V_DCBATOUT PG4128 GAP-CLOSE-PWR

84.00412.037 0604 Modify: DCBATOUT 1 2
PG4102 GAP-CLOSE-PWR PWR_3D3V_DCBATOUT Id=12A Change PU4103 to 74.8223.A73. 0721 Modify: PWR_5V_DCBATOUT
1 2 Qg=3.8nC 0714 Modify: Change PU4104 to 84.04800.D37
Change PU4103 to TPS51123 from RT8223MGQW. PC4101 PC4113 from power team Brian updated. 0721 Modify:
Rdson=24~30mohm
SC10U25V6KX-1GP
SCD01U50V2KX-1GP
0720 Modify: Add PG4127,PG4128 from
1
PG4103 GAP-CLOSE-PWR PC4110 PC4111 PC4112 Change PR4105 to 2.2ohm from 0ohm from DY power team Brian updated.
1
1
1 2 power team Brian updated. 0804 Change MOS follow Brian.
SC10U25V6KX-1GP
SC10U25V6KX-1GP
0913 X01 Modify: 0901 PU4104 and PU 4105 horizontally mirror.

SCD1U50V3KX-GP
2
Add 2nd source 84.08061.A37 on PU4102, PC4114 PC4116 PC4117
2
D 8
D 7
D 6
D 5
5
6
7
8
1
PG4104 GAP-CLOSE-PWR PU4104 base on Brian updated 2nd soruce excel file.
D
D
D
D
SC10U25V6KX-1GP
SC10U25V6KX-1GP
1 2 PU4102 PU4104
SCD1U50V3KX-GP
5V_PWR 5V_S5
16
SIS412DN-T1-GE3-GP SIS412DN-T1-GE3-GP
2
PU4103 0721 Modify:
3 Design Current = 9.2A 84.00412.037 Change PR4106 to 0ohm 0603 from 84.00412.037
2nd = 84.08061.A37 Design Current = 8A PG4107 GAP-CLOSE-PWR 3
VIN
0909 X01 Modify: 2.2ohm from power team Brian updated.
14.5A<OCP< 17A 2nd = 84.08061.A37 12.6A<OCP< 14.6A 1 2
G
S
S
S
Change PL4101,PL4102 to 68.2R210.20B SCD1U25V3KX-GP
S
S
S
G
from 68.2R210.20Q base on Brian updated. PC4115 PR4105 PC4118

1
2
3
4
4
3
2
1
Add 2nd source 68.2R21B.10J on PL4101, 2 1PWR_3D3V_BOOT1
1 2PWR_3D3V_BOOT2 9 22 PWR_5V_BOOT1 1 PR4106 2PWR_5V_VBST1_1 1 2 0719 Modify: PG4109 GAP-CLOSE-PWR
3D3V_S5 3D3V_PWR PL4102 base on updated 2nd excel file. VBST2 VBST1 0R0603-PAD 1 2
3D3V_PWR
68.2R210.20B SCD1U25V3KX-GP PWR_3D3V_UGATE2
2D2R3-1-U-GP 10 21 PWR_5V_UGATE1 5V_PWR Reserved EC417 0.1uF for
PG4108 GAP-CLOSE-PWR 2nd
77.53371.04L
= 77.93371.011 PL4101 DRVH2 DRVH1 PL4102 EMC NEO suggestion.
1 2 1 2 PWR_3D3V_PHASE2
11 20 PWR_5V_PHASE1 1 2 PG4111 GAP-CLOSE-PWR
1
IND-2D2UH-46-GP-U LL2 LL1 IND-2D2UH-46-GP-U 1 2

A00 1224 2nd = 68.2R21B.10J PWR_3D3V_LGATE2
12 19 PWR_5V_LGATE1 68.2R210.20B 77.53371.04L
1
1
PG4110 GAP-CLOSE-PWR DRVL2 DRVL1
DY 2nd = 68.2R21B.10J
D 8
D 7
D 6
D 5
5
6
7
8
1 2 PT4102 PG4113 PR4107 2nd = 77.93371.011 PG4115 GAP-CLOSE-PWR
D
D
D
D
SCD1U10V2KX-4GP
2D2R5F-2-GP PU4106 PWR_3D3V_VOUT2 7 PWR_5V_VOUT1 PR4108 PG4114 PC4120 EC4107

24 DY 1 2
SE330U6D3VM-15-GP
2
2
1
1
VO2 VO1
PC4119
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
SI7716ADN-T1-GE3-GP 2D2R5F-2-GP
SCD1U10V2KX-4GP
PG4112 GAP-CLOSE-PWR PWR_3D3V_FB2 PWR_5V_FB1 PT4104
1PWR_3D3V_SNUB
5 2
84.07716.037
SCD1U50V3KX-GP
2
VFB2 VFB1 PG4117 GAP-CLOSE-PWR
1 2
SE330U6D3VM-15-GP
2
2
3D3V_S5
2nd = 84.08065.B37 1 2
2
2
G
S
S
S
PWR_5V3D3V_EN0 13 A00 1224
S
S
S
G
1 2 23
DY820KR2F-GP
1PWR_5V_SNUB
1
PG4116 GAP-CLOSE-PWR PR4109 EN0 PGOOD
1
2
3
4
4
3
2
1
1 2 0804 PWR_3D3V_ENTRIP26 1 PWR_5V_ENTRIP1 PR4110 PU4105 0804 PG4119 GAP-CLOSE-PWR
PWR_5V3D3V_VREF TRIP2 TRIP1 100KR2J-1-GP 1 2
3 15
PG4118 GAP-CLOSE-PWR PC4121 VREF GND
84.07716.037
2
1
SCD22U10V2KX-1GP
PC4122
1 2 SC330P50V3KX-GP DY PWR_5V3D3V_TONSEL
4 25 PG4121 GAP-CLOSE-PWR
Mag. 2.20uH 6.5*6.9*3 Id=16A TONSEL GND SI7716ADN-T1-GE3-GP 1 2
2
Qg=7.3nC 3V_5V_POK PC4123

DY
2
PG4120 GAP-CLOSE-PWR DCR=18~20mohm PWR_5V3D3V_SKIPSEL

14 18 PWR_5V3D3V_ENC SC560P50V-GP
Rdson=13.5~16.5mohm 84.07716.037
2
SKIPSEL ENC
1 2 Idc=8A, Isat=14A PG4123 GAP-CLOSE-PWR
TPS51123RGER-GP 2nd = 84.08065.B37 1 2
VREG3
VREG5
PG4122 GAP-CLOSE-PWR 74.51123.073
2
1 2
1
8 PR4113
17
PR4112 5V_AUX_S5 0R0402-PAD
PG4124 GAP-CLOSE-PWR PR4111 DY 0R2J-2-GP 3D3V_AUX_S5
PG4125
PWR_5V3D3V_VREG3
1 2 6K65R2F-GP
1
1 2 5V_S5
2
1 2
1
PWR_3D3V_FB2_R 3V_5V_EN 36
1
PG4126 GAP-CLOSE-PWR PC4124 GAP-CLOSE-PWR-3-GP PR4114
1
1 2 DYSC18P50V2JN-1-GP 0R2J-2-GP DY DY
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
2 PR4115 2
2
2
33KR2F-GP
EC4101
EC4102
EC4103
1 2
PWR_5V_FB1_R
1
2
PR4116 PC4128 DY
1
10KR2F-2-GP PC4125 PC4126 PC4127 SC18P50V2JN-1-GP
2
PR4117 0701 Modify:
DY
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
2 1 PC4127 Default un-stuff.

DY0R2J-2-GP
SC4D7U25V5KX-GP
3D3V_AUX_S5
2
1
0719 Modify:
PR4119
PWR_5V3D3V_VREF 1 PR4118 2 21K5R2F-GP Reserved EC4101~EC4106 0.1uF near
0R0402-PAD PTC4101,PC4119 for EMC NEO suggestion.
Close to VFB Pin (pin5) Close to VFB Pin (pin2)
2
2 PR4120
1
PWR_5V3D3V_VREF DY 0R2J-2-GP
3D3V_AUX_S5 1 PR4121 2 I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

0R0402-PAD
Inductor: 2.2UH FDVE0630-2R2M=P3 TOKO 21mohm Isat =8.7Arms 68.2R21B.10A
2 PR4123 O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
DY 1
0R2J-2-GP H/S: FDSS8884 SO-8/ 23mohm/30mOhm@4.5Vgs/ 84.08884.037
0914 X01 Modify: L/S: FDS6690AS SO-8/ 12mohm/15mOhm@4.5Vgs/ 84.06690.E37
Un-stuff PU4101,PD4105,PR4124,
DCBATOUT PR4125,PR4101 at X01 stage. DCBATOUT
2
Vz=5.1V DY PD4105
1
PU4101 MMPZ5231BPT-GP
PR4124 4 3 PWR_5V3D3V_EN0 83.5R103.E3F
DY 40K2R2F-GP
2nd = 83.PDZ51.AVF
1
5 DY 2 PU4101_2 TONSEL CH1 CH2

SKIPSEL VREG3 or VREG5 VREF(2V) GND
2
PU4101_5 6 1 0629 Modify GND 200kHz 250kHz

PR4101 Operating OOA Auto Skip Auto Skip
1
2N7002KDW-GP DY100KR2F-L1-GP VREF 300kHz 375kHz PWM only

PR4125
Mode
750KR2F-GP VREG3 or VREG5 400kHz 500kHz
DY
2
84.2N702.A3F
2
1 1
<Variant Name>
Wistron Corporation
Title
5V/3D3V(TPS51123RGER)
A2
QUEEN 15 A00
A B C D E
5 4 3 2 1
PR4216 PC4231 0921 X01 Modify:

SSID = CPU.Regulator 0629 Modify
1 2 PR4216_1 1 2 Add PR4216,PC4231 from vender suggestion.
0719 Modify:
95831_VW G 2KR2F-3-GP SC330P50V2KX-3GP Reserved EC4201~EC4203 0.1uF near
PR4246(TOP) for EMC NEO suggestion.
1
PC4220
0721 Modify:
2
PR4208 PC4202 1 2
8K06R2F-GP SC1000P50V3JN-GP-U DY Removed EC4201~EC4203.
1
SC330P50V2KX-3GP VCC_AXG_SENSE 9
1
0629 Modify PC4212
2
95831_COMPG SCD068U10V2KX-1GP
2
95831_FBG
PC4222
2
D PC4208 PR4211 PC4221 1 2 VSS_AXG_SENSE 9 D
PR4237 1 2 1 PC4221_1 1
2 2
0629 Modify SC1000P50V3JN-GP-U 0719 Modify:
DUMMY-R2
SC39P50V2JN-1GP 422R2F-2-GP SC680P50V2KX-2GP
Stuff PR4246 NTC resistor. PG4202
0629 Modify 2 1
ISPG 44
1
PC4211 PR4210 PR4236 ISNG 44
1 2PC4211_2 1 2 1 2 DUMMY-C2
0920 X01 Modify:
SC150P50V2KX-GP 475KR2F-GP 3K01R2F-3-GP Change PR4236 to 3.01K from 3.32K NTCG PR4246 PR4219
from Brian updated. 1 TP4202 TPAD14-GP 1 2 2 1
95831_IMONG PR4239 NTC-470K-9-GP
PR4220_1
1 2 3K83R2F-GP
69.60013.141
SCD047U25V2KX-GP
1
1D05V_VTT
PC4205
Only for Dual-core, PC4214 2nd = 69.60037.021
1
PR4202 16K5R2F-2-GP PR4220 0629 Modify
Qual-core stuff 22KR 22KR2F-GP 1 2 2 1
BOOTG 44
95831_PROG2
(64.22025.6DL) UGATEG 44
2
SCD1U10V2KX-4GP PHASEG 44 27K4R2F-GP
2
VSS_AXG_SENSE LGATEG 44 NTC place near high side MOSFET of Phase1

Close to CPU
0629 Modify
PW M3 43
1
0707 Modify:
75R2F-2-GP
130R2F-1-GP
54D9R2F-L1-GP
2
Updated IMONG and IMON circuit
PR4232
PR4244
PR4234
from power team Brian. 3D3V_S0 PR4222
49
48
47
46
45
44
43
42
41
40
39
38
37
0707 Modify: PU4201 0R0402-PAD 5V_S0
Removed PR4240 GND to 95831_AGND.
PROG2
COMPG
FBG
VSENG
RTNG
ISPG
ISNG
NTCG
BOOTG
UGG
PHG
LGG
GND
2
1
1 PR4231 2
1
8 H_CPU_SVIDDAT 0R0402-PAD PR4230 PR4223
1 2
0707 Modify: 1K91R2F-1-GP DY 0R2J-2-GP
2
C Removed PR4233. 1 36 BOOT2 C
VWG BOOT2 BOOT2 43
0629 Modify 2 35 UGATE2 PR4243
UGATE2 43
2
8 VR_SVID_ALERT# 95831_PGOODG 3 IMONG UG2 PHASE2 0R0402-PAD
PGOODG PH2 34 PHASE2 43
95831_SDA 4 33
SDA VSSP2 LGATE2 VCC_GFXCORE
5 32 LGATE2 43
1
ALERT# LG2
8 H_CPU_SVIDCLK 1 PR4204 2 95831_SCLK 6 SCLK VDDP 31 95831_VDDP
1 PR4203 2 0R0402-PAD IMVP_VR_ON 7 30 95831_PW M3
SC1U10V2KX-1GP
SC1U10V2KX-1GP
48 D85V_PW RGD VR_ON PWM3
1
0R0402-PAD PR42351 2 1K91R2F-1-GP LGATE1 0629 Modify
PC4228
PC4229
3D3V_S0 8 PGOOD LG1 29 LGATE1 43
1
9 28 0629 Modify
DY
SCD1U50V3KX-GP
H_PROCHOT#_C IMON VSSP1 PHASE1
10 27 PHASE1 43
2
95831_IMON 27,36 IMVP_PW RGD VR_HOT# PH1 UGATE1
EC4209
11 26
SCD01U50V2KX-1GP
UGATE1 43
2
PR4201 95831_VW NTC UG1 BOOT1
12 VW BOOT1 25 BOOT1 43
1
ISEN3/FB2
A00 1227 0629 Modify
PC4203
1 2
1D05V_VTT DY
1
Only for Dual-core, PR4207
PROG1
ISUMN
ISUMP
COMP
ISEN2
ISEN1
VSEN
DC&QC 22KR2F-GP 75R2F-2-GP
VDD
RTN
Qual-core stuff 18K2R
VIN
FB
2
(64.18225.LDL) 0901
2
VSSSENSE PC4204 ISL95831HRTZ-T-GP 0719 Modify:
13
14
15
16
17
18
19
20
21
22
23
24
1 PR4215 2 SC47P50V2JN-3GP
PR4226
2
5,27,40 H_PROCHOT# 0R0402-PAD 0629 Modify Reserved EC4204~EC4207 0.1uF near

PG4203
95831_PROG1 1 2 C1403(TOP),C1507,C1509,C1406,
1 2 95831_NTC
0629 Modify TP_LOCK_LED1 for EMC NEO suggestion.
5K62R2F-GP
ISEN3
ISEN2
ISEN1
DUMMY-C2 PW R_VCCCORE1_DCBATOUT
PR4229 PR4247 0629 Modify
1 2 1 2 0707 Modify: 95831_VIN 1 PR4225 2
NTC-470K-9-GP Stuff PR4247 NTC Resistor. 0R0402-PAD
PR4228_1
0707 Modify: 3K83R2F-GP

B Change all of 9531_AGND to GND for vender suggest. 69.60013.141
2nd = 69.60037.021 5V_S5 B
Place near high side MOSFET of Phase1 PR4228 0629 Modify PR4224
1 2 95831_VDD 1 2
0629 Modify PC4215 0921 ISEN1
SC1U10V2KX-1GP
SCD22U25V3KX-GP
43 ISEN1
27K4R2F-GP 1R2F-GP
95831_ISUMN
PC4226
PC4201
1 2
1
1 Change PU4201 VDD power source to 5V_S5 from ISEN2
5V_S0 to avoid abnormal MVP_PWRGD waveform. 43 ISEN2
SCD22U10V2KX-1GP
1
2 43 ISEN3 ISEN3
2
PR4205 PC4216
2
VSUM- 0629 Modify

8K06R2F-GP
1 2
PC4206
SC1000P50V3JN-GP-U SCD22U10V2KX-1GP
2
0721 Modify:
0629 Modify PC4217 Change PC4227 to 33uF from 47uF from
95831_COMP 1 2 power team Brian updated.
Change PC4225 to 0.033uF from 0.068uF from
95831_FB SCD22U10V2KX-1GP power team Brian updated.
VSUM+ 43
PR4206
1
PC4209 PR4212 PC4213
SCD033U16V2KX-GP
SCD33U6D3V2KX-1-GP
1 2 1 2 1 2PC4213_1 1 2 PR4242
0629 Modify 2K61R2F-1-GP
11KR2F-L-GP
SC39P50V2JN-1GP 499R2F-2-GP SC470P50V-2-GP
PC4225
PR4241
DUMMY-R2
1
1
A00 1230
PC4227
PC4207 A00 1227 PR4213
Only for Dual-core,
2
PC4210 PR4209 0629 Modify Place near choke of Phase1
ISEN3 1 2 1 2 1 2 1 2
Qual-core stuff 3K6R(64.36015.6DL) PR4242_2
2
1
0721 Modify:
PC4210_2
Change PR4213 to 3.16K from 2.32K from

Only for Dual-core,
SC150P50V2KX-GP 316KR2F-GP 2K37R2F-GP PR4245
Qual-core stuff 1K27R
2
DUMMY-C2 0629 Modify power team Brian updated. NTC-10K-27-GP
DC&QC
A PC4230 PR4214 (64.12715.6DL) 69.60013.131 <Variant Name> A
2PR4214_1 1 PR4217 A00 1227
1 2 2nd = 69.60011.201
2
2KR2F-3-GP 1 2 VSUM- 43
SC560P50V-GP 0921 X01 Modify: PC4219
Wistron Corporation
SC330P50V2KX-3GP
1
Add PR4214,PC4230 from vender suggestion. 1 2 845R2F-GP DC&QC
DY PC4218 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
PC4224
8 VCCSENSE
1
SC330P50V2KX-3GP PG4201 PR4218 SCD1U10V2KX-4GP Taipei Hsien 221, Taiwan, R.O.C.
2
8 VSSSENSE 1 2 2 1
PC4223 Title
PR4218_2
2
DUMMY-C2 DUMMY-R2
0920 X01 Modify:
1 2
0629 Modify ISL95831_CPU_CORE(1/3)
Change PR4213 to 3.6K from 3.16K SC1000P50V3JN-GP-U 0721 Modify: Size Document Number Rev
from Brian updated. Change PR4217 to 1K from 698ohm from A3
power team Brian updated. QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
0719 Modify:
84.00462.037 PWR_VCCCORE1_DCBATOUT
Change PU4308 part number to 84.00172.037 from
SIR462DP 84.07686.037 base on power team Brian suggestion.
Id=30A, Qg=8.8nC, 0726 Modify:
5V_S0 Rdson=7.9~10 mohm PWR_VCCCORE3_DCBATOUT
PWR_VCCCORE_BOOT3
Brian updatede PU4308 change to 84.00462.037.
1
PU4308 PC4313 PC4314 PC4315 PC4316 PC4317
5
6
7
8
PR4314
QC
D
D
D
D
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
1 2PWR_VCCCORE_BOOT1_1
2
42 BOOT1
1
PC4301 PC4303 PC4304 PC4305
SC1U10V2KX-1GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
PR4302 PC4306 2D2R3-1-U-GP SIR462DP-T1-GE3-GP
5
6
7
8
SC4D7U25V5KX-GP
1 2PWR_VCCCORE_BOOT3_1 SC4D7U25V5KX-GP
1
D
D
D
D
PU4302 80.3371V.A2L
G
S
S
S
2D2R3-1-U-GP PC4318 0705 Modify
1
D 330uF, 2.5V, B2 SCD22U25V3KX-GP D
4
3
2
1
PC4302 68.R3610.20A VCC_CORE
ESR=9m[, Iripple=3.073A
2
SCD22U25V3KX-GP
84.00462.037
2
0.36uH, Idc=20A,
G
S
S
S
PR4301 PU4301 0705 Modify PL4303
42 UGATE1 2nd = 84.08064.A37
1
0R0402-PAD 1 2
Isat=25A
4
3
2
1
SIR462DP-T1-GE3-GP VCC_CORE 42 PHASE1 L-D36UH-1-GP A00 1224
VCC
BOOT
84.00462.037 DCR=1.4 +/-7% mohm 68.R3610.20A
1
5
6
7
8
5
6
7
8
2nd = 84.08064.A37 PL4301 84.00462.037 2nd = 68.R3610.20C PT4301 PT4302
1
D
D
D
D
D
D
D
D
ST330U2VDM-4-GP
ST330U2VDM-4-GP
2 7 PWR_VCCCORE_PH3 1 2 PU4309 0809
42 PWM3 PWM PHASE SIR462DP
SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
8 PWR_VCCCORE_HG3 L-D36UH-1-GP PU4310
PWR_FCCM UGATE
4 A00 1224 PT4308 PT4309 QC
68.R3610.20A Id=30A, Qg=8.8nC,
2
LGATE
5
6
7
8
5
6
7
8
2
ST330U2VDM-4-GP
ST330U2VDM-4-GP
6 FCCM PU4304 2nd = 68.R3610.20C PG4318
D
D
D
D
D
D
D
D
PU4303 0809 Rdson=7.9~10 mohm PG4317
79.33719.20L
GND
GND
2
SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
S
S
S
S
S
S
G
PWR_VCCCORE_VSUM-_1
QC 84.00460.037
2
PG4301 PG4302
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
79.33719.20L 79.33719.20L 2nd = 84.08059.037 2nd = 77.C3371.13L
4
3
2
1
4
3
2
1
1
ISL6208CRZ-TGP-U 2nd = 77.C3371.13L 2nd = 77.C3371.13L
84.00460.037
9
3
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
2nd = 84.08059.037
PWR_VCCCORE_VSUM-_3
79.33719.20L
1
S
S
S
S
S
S
0705 Modify PR4315
G
PR4303
2nd = 77.C3371.13L
DY
1 2 ISEN2 42
4
3
2
1
4
3
2
1
PWR_VCCCORE_VSUM+_3
DY
1 2 1R2F-GP
ISEN1 42 84.00460.037
PWR_VCCCORE_VSUM+_1
DCBATOUT_IMVP7 PWR_VCCCORE3_DCBATOUT 1R2F-GP 2nd = 84.08059.037 PR4316
PG4319 DY
1 2 ISEN3 42
PR4304 42 LGATE1 1R2F-GP
1 2
PWR_VCCCORE_LG3 DY
1 2 84.00460.037 PR4317
GAP-CLOSE-PWR 2nd = 84.08059.037
84.00460.037 1R2F-GP
ISEN2 42
1 2 VSUM- 42
PG4320 84.00460.037 SIR460DP 1R2F-GP
1 2 PR4305
SIR460DP 1 2
Id=40A,Qg=16.8nC, PR4318
GAP-CLOSE-PWR
Id=40A,Qg=16.8nC, PR4306
VSUM- 42 Vcc_core Rdson=4.7~6.1mohm 2 1 ISEN1 42
PG4321 1R2F-GP
C 1 2 Rdson=4.7~6.1mohm 2 1
ISEN3 42
Iomax=53A 10KR2F-2-GP C
PR4319
GAP-CLOSE-PWR 10KR2F-2-GP OCP>97.5A 2 1 VSUM+ 42
PG4322 PR4307
1 2 2 1 3K65R2F-1-GP
VSUM+ 42 0705 Modify
GAP-CLOSE-PWR
0719 Modify: 3K65R2F-1-GP
PG4323 Change PU4302 part number to 84.00172.037 from DCBATOUT_IMVP7 PWR_VCCCORE1_DCBATOUT
1 2 84.07686.037 base on power team Brian suggestion. PG4305
FOR NVIDIA VENTURA 1 2
GAP-CLOSE-PWR 0726 Modify: 0705 Modify 0705 Modify
PG4324 GAP-CLOSE-PWR
Brian updatede PU4302 change to 84.00462.037. DCBATOUT DCBATOUT_IMVP7 PG4306
1 2 84.00462.037 PWR_VCCCORE2_DCBATOUT 1 2
GAP-CLOSE-PWR SIR462DP
GAP-CLOSE-PWR
Id=30A, Qg=8.8nC, PG4307
Rdson=7.9~10 mohm 1 2
PU4305 0708 Modify: GAP-CLOSE-PWR

1
1
SIR462DP-T1-GE3-GP A00 1223 no co-lay PR4320 change to BIG SIZE footprint for CPU VENTURA.
QCPC4307 PC4308 PC4309 PC4310 PC4311 PG4308
5
6
7
8
PR4308 PR4320 0705 Modify: 1 2

D
D
D
D
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
1 2PWR_VCCCORE_BOOT2_1 1 2 R4346 change to PR4320 4m ohm sense
2
2
42 BOOT2 Resistor from 3m ohm. GAP-CLOSE-PWR
2D2R3-1-U-GP PG4309
D004R3720F-GP 0705 Modify: 1 2
1
Removed R4347 sense Resistor base on VENTURA SPEC.
2
G
S
S
S
PC4312 0705 Modify GAP-CLOSE-PWR

SCD22U25V3KX-GP PR4321 PR4322 PG4310
2
4
3
2
1
VCC_CORE 10R2F-L-GP 10R2F-L-GP 0705 Modify: 1 2

B UGATE2 Add PR4321,PR4322,PC4319. B
42 UGATE2 84.00462.037 PL4302
VENTURA VENTURA GAP-CLOSE-PWR
2nd = 84.08064.A37
1
PHASE2 PC4319
U4306_VIN+
U4306_VIN-
42 PHASE2 1 2
L-D36UH-1-GP 1 2
LGATE2 PT4303 PT4304 VENTURA 3D3V_VGA_S0
42 LGATE2 68.R3610.20A
5
6
7
8
5
6
7
8
1
ST330U2VDM-4-GP
ST330U2VDM-4-GP
PU4307 A00 1224 SCD1U25V2KX-GP
2nd = 68.R3610.20C
D
D
D
D
D
D
D
D
PU4306 0809 0702 Modify: DCBATOUT

SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
0705 Modify Change U4306 power source to

QC
2
3D3V_VGA_S0 from 3D3V_S0.

2
1
DCBATOUT_IMVP7 PWR_VCCCORE2_DCBATOUT 2nd = 84.08059.037 84.00460.037 PG4303 PG4304 C4301 A00 1224
79.33719.20L
1
2
3
4
1
S
S
S
S
S
S
0719 Modify:
G
PG4311 2nd = 77.C3371.13L VENTURA
2
Reserved PTC4307 47uF. PT4306
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1 2 84.00460.037
VIN+
GND
VS
VIN-
4
3
2
1
4
3
2
1
0721 Modify: SE47U25VM-11-GP

79.33719.20L
2
GAP-CLOSE-PWR SIR460DP SCD1U10V2KX-5GP Removed PTC4307.
PG4312 2nd = 77.C3371.13L
79.47612.3FL
Id=40A,Qg=16.8nC,
1
1 2 PR4309 VENTURA 2nd = 79.47612.60L
PWR_VCCCORE_VSUM-_2
Rdson=4.7~6.1mohm DY
1 2 ISEN1 42 R4345
SDA
SCL
GAP-CLOSE-PWR 1R2F-GP 3K3R2J-3-GP 3K3R2J-3-GP
A1
A0
PWR_VCCCORE_VSUM+_2
PG4313 R4344 VENTURA

1 2 U4306
84.00460.037 8
7
6
5
2
PR4310 0712 Modify:
GAP-CLOSE-PWR
2nd = 84.08059.037 VENTURA Change VENTURA solution part number to
DY
1
1R2F-GP
2 ISEN3 42
HPA00900AIDCNR-GP 74.00900.079 from 74.00219.079.
PG4314INS43029 0719 Modify:
1 2 INA_A0
Change PU4305 part number to 84.00172.037 from 74.00900.079 INA_A1
GAP-CLOSE-PWR 84.07686.037 base on power team Brian suggestion. PR4311
1
PG4315 1 2 VSUM- 42
1 2 0726 Modify: R4347 R4346
1R2F-GP 3K3R2J-3-GP 3K3R2J-3-GP
A GAP-CLOSE-PWR
Brian updatede PU4305 change to 84.00462.037. PR4312 A
DY DY DN15ATI
PG4316 2 1
2
2
ISEN2 42
1 2 0728
10KR2F-2-GP
GAP-CLOSE-PWR PR4313 Wistron Corporation
2 1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
VSUM+ 42 Taipei Hsien 221, Taiwan, R.O.C.
3K65R2F-1-GP
SMBC_INA219 85,92 Title
SMBD_INA219 85,92
ISL95831_CPU_CORE ( 2 of Rev
3)
Would be instead of INA219 by HPA00900
Custom
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
0705 Modify
DCBATOUT_IMVP7 PW R_GFXCORE_DCBATOUT
PG4403 GAP-CLOSE-PW R
1 2
0719 Modify: 1 2
84.07686.037 base on power team Brian suggestion. PG4405 GAP-CLOSE-PW R
D 1 2 D
0720 Modify:
84.00172.037 base on power team Brian suggestionl. 1 2
84.00462.037 PG4407 GAP-CLOSE-PW R

SIR462DP-T1-GE3-GP PW R_GFXCORE_DCBATOUT 1 2
Id=30A, Qg=8.8nC,
Rdson=7.9 mohm PG4408 GAP-CLOSE-PW R
1 2
1
PC4402 PC4403 PC4404 PC4405 PC4406
5
6
7
8
PR4401
D
D
D
D
1 2 PW R_GFXCORE_BOOT_1 0624 Modify: PG4409 GAP-CLOSE-PW R
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
2
2
42 BOOTG Removed PU4402 1 2
1R3J-L1-GP MOSFET.
0721 Modify:
1
Removed PC4401
G
S
S
S
PC4407 PU4401
SCD22U25V3KX-GP SIR462DP-T1-GE3-GP
4
3
2
1
VCC_GFXCORE
84.00462.037
2nd = 84.08064.A37 PL4401 79.33719.20L A00 1224 79.33719.20L
42
42
UGATEG
PHASEG 1 2 2nd = 77.C3371.13L 2nd = 77.C3371.13L VCC_GFXCORE
L-D36UH-1-GP
42 LGATEG 68.R3610.20A 68.R3610.20A PT4401 PT4402 PT4403 80.3371V.A2L Iomax=33A
5
6
7
8
5
6
7
8
1
2nd = 68.R3610.20C OCP>50A
D
D
D
D
D
D
D
D
C PU4403 PU4404 0.36uH, Idc=20A, Isat=25A 330uF, 2.5V, B2 C
DCR=1.4 +/-7% mohm ESR=9m[, Iripple=3.073A
ST330U2VDM-4-GP
ST330U2VDM-4-GP
ST330U2VDM-4-GP
2
2
SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
2
PG4401 PG4402 79.33719.20L
84.00460.037
S
S
S
S
S
S
G
G
2nd = 77.C3371.13L
2nd = 84.08059.037
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
4
3
2
1
4
3
2
1
1
PWR_GFXCORE_ISN_R
0809
0629 Modify
PC4408
DY PR4402
PWR_GFXCORE_ISP_R
2 1 PC4408_1 1 DY 2
1
84.00460.037
2nd = 84.08059.037 PC4409 549R2F-GP
84.03503.037 SCD1U10V2KX-4GP SCD068U16V2KX-GP
2
PR4403 0629 Modify PR4404
BSZ035N03MS 1 2 PR4403_2 1 2 ISNG 42
Id=18A,Qg=27~35nC,
1
1R2F-GP 0721 Modify:
768R2F-1-GP
Rdson=3.4~4.3mohm PR4405 PC4410 Change PR4404 to 768ohm from 549ohm from
2
NTC-10K-27-GP PC4411 power team Brian updated.
1
2nd = 69.60011.201
69.60013.131 PR4406 SCD068U16V2KX-GP
SCD01U16V2KX-3GP
1 2
1
0629 Modify PR4405_2
11KR2F-L-GP
PR4407
2
7K5R2F-1-GP
PR4408
2
B B
2 1 ISPG 42
10KR2F-2-GP 0920 X01 Modify:
Change PC4410 to 0.01u from 0.022uF
from Brian updated.
EMI/ESD 0715 Modify:

Add EC4401~EC4410 for EMC NEO suggestion.
VCC_CORE VCC_CORE PW R_VCCCORE1_DCBATOUT PW R_VCCCORE2_DCBATOUT PW R_VCCCORE3_DCBATOUT VCC_GFXCORE PW R_GFXCORE_DCBATOUT

EC4401
SCD1U50V3KX-GP
EC4402
SCD1U50V3KX-GP
EC4403
SCD1U50V3KX-GP
EC4405
SCD1U50V3KX-GP
EC4408
SCD1U50V3KX-GP
EC4407
SCD1U50V3KX-GP
EC4409
SCD1U50V3KX-GP
EC4410
SCD1U50V3KX-GP
1
DY DY DY DY
2
A DN15ATI A
Wistron Corporation
Title
ISL95831_CPU_CORE(3/3)
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
DCBATOUT PW R_1D05V_DCBATOUT
0719 Modify:
PG4501 GAP-CLOSE-PW R 84.07686.037 base on power team Brian suggestion.
1 2
PW R_1D05V_DCBATOUT
1 2 1122 X02 Modify:
stuff EC4501 0.1uF from
EMC Neo suggestion.
D D
PG4503 GAP-CLOSE-PW R 84.00172.037
1 2 1D05V_PW R 1D05V_VTT
1
BSZ115N03MSC PC4504 PC4505 PC4506 PC4507
Id=20A, Qg=9.8nC,
SCD1U50V3KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SCD1U25V3KX-GP
PG4504 GAP-CLOSE-PW R PG4505 GAP-CLOSE-PW R
2
5
6
7
8
Rdson=8.9 mohm
EC4501
1 2 1 2
TPS51218 for 1D05V
D
D
D
D
PU4502 PG4506 GAP-CLOSE-PW R
1 2
SIR172DP-T1-GE3-GP
G
S
S
S
PR4516
4
3
2
1
2 1 0721 Modify: 1 2
1123 X02 Modify:
3D3V_S0 Change PR4504 to 2.2ohm from 0ohm from 84.00172.037
2nd = 84.08065.037 Design Current = 9.9A
Change PR4501 to 75K from 45.3K power team Brian updated.
for 1.05V OCP set to 20A from Brian. 10KR2J-3-GP Mag. 2.20uH 10*11.5*4 15.6A<OCP< 18.3A
PU4501 PG4508 GAP-CLOSE-PW R
37,48 1.05VTT_PW RGD PC4502 DCR=6.7~7mohm 1 2
PR4501 1D05V_PW R
1 PGOOD GND 11 PR4504 SCD1U25V3KX-GP Idc=12A, Isat=27A
PR4502 1 2 PW R_1D05V_TRIP 2 10 PW R_1D05V_VBST 1 2PW R_1D05V_VBST_R
2 1 0909 X01 Modify:
PW R_1D05V_EN TRIP VBST PW R_1D05V_DRVH Change PL4501 to 68.2R210.20C PL4501 PG4509 GAP-CLOSE-PW R
19,46,47,93 RUNPW ROK 1 2 3 EN DRVH 9
PW R_1D05V_VFB 4 8 PW R_1D05V_SW 2D2R3-1-U-GP from IND-D56UH-27-GP base on 1 2 1 2
75KR2F-GP
0R0402-PAD-2-GP PW R_1D05V_CCM 5 VFB SW Brian updated.
CCM V5IN 7 5V_S5
SE390U2D5VM-7GP
A00 1224 6 PW R_1D05V_DRVL COIL-2D2UH-11-GP A00 1224
DRVL DY
1
1
0809 68.2R210.20C PG4510 GAP-CLOSE-PW R
1
PT4502
PR4503 PR4514 2nd = 68.2R21B.10I PR4505 PC4508 PTC4509 1 2
5
6
7
8
470KR2F-GP TPS51218DSCR-GP-U1 PU4503 DY
D
D
D
D
SC1U10V2KX-1GP
SCD1U10V2KX-4GP
SCD1U25V3KX-GP
2D2R5F-2-GP 100R2F-L1-GP-U
2
SIR460DP-T1-GE3-GP
C PC4503 PG4511 GAP-CLOSE-PW R C
2
1PWR_1D05V_SNUB 2
VTT_SENSE_L 1 2
1
1
PC4501
SC1KP50V2KX-1GP
S
S
S
PR4506 PC4511 PG4512 GAP-CLOSE-PW R
G
DY 79.3971V.30L
1
9K76R2F-1-GP 1 2
2
4
3
2
1
SCD1U10V2KX-4GP
A00 1224
DY 2nd = 77.93971.02L
2
Id=26.5A PG4513 GAP-CLOSE-PW R
PW R_1D05V_VFB 1 2
Qg=40.6~61nC,
Rdson=2.6~3.2mohm DY PC4509
1
SC560P50V-GP PR4507 PG4514 GAP-CLOSE-PW R
84.00460.037
2
20KR2F-L-GP 1 2
2nd = 84.08059.037 0921
0920 X01 Modify:
Change PR4507 to 20K from 20.5K PG4515 GAP-CLOSE-PW R
2
VSS_SENSE_L from Brian updated. 1 2
1
0721 Modify:
Brian suggest change PU4503 to 84.00460.037. PR4508 PG4516 GAP-CLOSE-PW R
Change PR4506 to 9.76K from 10K from 100R2F-L1-GP-U 1 2
power team Brian updated.
1
2
DY
SCD1U50V3KX-GP
Vout=0.704V*(R1+R2)/R2
EC4502
VTT_SENSE_L 1 PR4509 2 VCCIO_SENSE 8 0617 Modify:
0R0402-PAD
B Joseph Change PTC4502 to 330uF from 390uF B
1
base on layout placement status.
PC4510 0721 Modify:
DY SC1000P50V3JN-GP-U
Brian Add PC4511 1uF. 0719 Modify:
2
Change PTC4502 to 330u 79.33719.L01. Reserved EC4502,EC4503 0.1uF near
VSS_SENSE_L 1 PR4510 2 VSSIO_SENSE 8 PG4516(TOP) for EMC NEO suggestion.
0R0402-PAD
0901 X01 Modify:
Change PTC4502 to 79.3971V.30L from
79.33719.L01 from power team Brian updated.
0727 Modify: 0913 X01 Modify:
PR4505,PR4508 change to 100ohm from 10ohm. Add 2nd source 77.93971.02L on PTC4502
stuff PR4509,PR4510 0ohm from Brian updated. base on Brian updated 2nd soruce excel file.
A DN15ATI A
Wistron Corporation
Title
TPS51218_+1.05V_VTT
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p5v0p75v 1D5V_PW R 1D5V_S3
DCBATOUT +PW R_SRC_1D5V 1 2

0719 Modify: PG4603 PG4608
2 1 GAP-CLOSE-PW R
5V_S5 Change PU4602 part number to 84.00172.037 from
84.07686.037 base on power team Brian suggestion. GAP-CLOSE-PW R 1 2
PG4604 PG4609
SC1U10V3KX-3GP
+PW R_SRC_1D5V 2 1 GAP-CLOSE-PW R
PC4601
3D3V_S0 84.00172.037 GAP-CLOSE-PW R
D 1 2 D
1
BSZ115N03MSC PG4605 PG4610
2 1 GAP-CLOSE-PW R
Id=20A, Qg=9.8nC,
PC4614
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
SC4D7U25V5KX-GP
2
1
5
6
7
8
Rdson=8.9 mohm GAP-CLOSE-PW R
PC4609
PC4611
PC4612
PC4613
1 2
1
D
D
D
D
PR4604 PG4606 PG4611
20KR2J-L2-GP 0630 modify 2 1 GAP-CLOSE-PW R
PU4602
2
PU4601 SIR172DP-T1-GE3-GP GAP-CLOSE-PW R 1 2
2
PR4605_2
20 12 PC4619 PG4612
19,45,47,93 RUNPW ROK PGOOD V5IN 84.00172.037
G
S
S
S
SCD1U25V3KX-GP 2nd = 84.08065.037 Design Current = 14.45A GAP-CLOSE-PW R
0721 Modify: 17 PR4605
22.71A<OCP< 26.84A
4
3
2
1
Removed PR4615,PR4616 and connect 37 0D75V_EN VTTEN PW R_1D5V_VBST1
VBST 15 2 1 2 1 2
0D75V_EN to VTTEN directly. PW R_1D5V_EN 16 2D2R3J-2-GP PG4613
EN/PSV GAP-CLOSE-PW R
PW R_1D5V_VREF 6 14 PW R_1D5V_DRVH 0913 X01 Modify: 1D5V_PW R
VREF DRVH
1
Add 2nd source 68.R681A.10Q on PL4601 1 2

PR4603 0721 Modify: PL4601 base on Brian updated 2nd soruce excel file. PG4614
10KR2F-2-GP Change PR4602 to 68K from 6.2K from 13 PW R_1D5V_SW 1 2 GAP-CLOSE-PW R
power team Brian updated. SW IND-D68UH-51-GP-U
1 2
68.R6810.20G
SC4D7U6D3V5KX-3GP
2
1
PW R_1D5V_REFIN 8 TPS51216_DRVL A00 1224 PG4615
11 84.00460.037
SCD1U10V2KX-4GP
REFIN DRVL
5
6
7
8
1
PU4603 GAP-CLOSE-PW R
PC4620
PC4621
2nd = 68.R681A.10Q
SCD1U25V3KX-GP
1
D
D
D
D
SiR460DP-T1-GE3
PG4607
10 PR4612 PT4602
47KR2F-GP
DY DY
SCD1U50V3KX-GP
PGND
2
SIR460DP-T1-GE3-GP
PW R_1D5V_MODE 19 2D2R5F-2-GP
68.R6810.20G 1 2
Id=40A, Qg=16.8nC,
SE390U2D5VM-7GP
SCD01U16V2KX-3GP
GAP-CLOSE-PWR-3-GP
2
MODE
2
PG4616
PC4603
PR4601
EC4601
200KR2F-L-GP
Id=22~39A
2
1
Rdson=4.7~6.1 mohm GAP-CLOSE-PW R

2
PW R_1D5V_TRIP 18 PW R_1D5V_VDDQS DCR=2.4~2.7mohm

PC4602
9
1
TRIP VDDQS
S
S
S
TPS51216_PHS_SET
G
PR4608
1 2
110KR2F-GP
Size=10X11.5X4
PWR_1D5V_VDDQS
2
PG4617
PR4601_1
C 2 C
4
3
2
1
VTTIN
1
PW R_1D5V_VTTREF5 +0D75V_DDR_P GAP-CLOSE-PW R
PR4602
VTTREF
1
PC4622
PR4606
3
DY
4K02R2F-GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1
VTT
1
SC330P50V2KX-3GP 1 2
79.3971V.30L
SCD1U10V2KX-4GP
2
1
1
PC4610 PG4618
PC4615
PC4616
PC4617
1 2nd = 77.93971.02L
2
SCD22U6D3V2KX-1GP VTTS GAP-CLOSE-PW R

21 GND DY
2
4 0902 X01 Modify:

2
2
VTTGND Change PTC4602 to 79.3971V.30L from
7 1 2
GND 84.00460.037 79.22719.20L sync with DQ15-NV PG4619
0920 X01 Modify: TPS51216RUKR-GP Add 2nd source 77.93971.02L on PTC4602. GAP-CLOSE-PW R
Change PR4602 to 110K from 68K 2nd = 84.08059.037
from Brian updated. 74.51216.073 0721 Modify:
1D5V_PW R
79.3971V.30L 1 2
un-stuff PC4617 from PG4620
SC1U10V3KX-3GP
0928 power team Brian updated. 0630 Modify: 390uF, 2.5V,6.3X5.7 GAP-CLOSE-PW R
PC4604
1
Change PR4606 to 4.02K from 0630 Modify: ADD PC4604 1uF0603 on PWR_1D5V_VTTIN.
240ohm for fine tune 1.5V output Change 1D5V power soluiton to TPS51216 from ESR=10m[, Iripple=3.87A
1 2
Voltage. TPS51116 follow power team Brian suggest. PG4621
2
+0D75V_DDR_P 0D75V_S0 GAP-CLOSE-PW R
PG4601
0630 Modify: 1 2 1 2
Change PC4610 to 0.22u 0402 PG4622
from 0603 from Brian. GAP-CLOSE-PW R 0721 Modify: GAP-CLOSE-PW R
PG4602 Removed PR4615,PR4616 and connect
1 2 0D75V_EN to VTTEN directly. 1 2
State S3 S5 VDDR VTTREF VTT PG4623
GAP-CLOSE-PW R GAP-CLOSE-PW R
S0 Hi Hi On On On
1 2
S3 Lo Hi On On Off(Hi-Z) PG4624
B DDR_VREF_S3 GAP-CLOSE-PW R B
S4/S5 Lo Lo Off Off Off

PW R_1D5V_VTTREF 1 PR4611 2 PR4607 1 2
0R0603-PAD 1 2 PW R_1D5V_EN PG4625
19,27,75 PM_SLP_S4# GAP-CLOSE-PW R
MODE
0702 Modify: 0R0402-PAD-2-GP
1
PR5003 Frequency Discharge Mode Add PR4611 0ohm 0603 pad PC4606
on PWR_1D5V_VTTREF. A00 1224 SCD1U10V2KX-5GP
DY
200k ohm 400kHz
2
Tracking Discharge
100k ohm 300kHz
68k ohm 300kHz
Non-tracking Discharge
47k ohm 400kHz
<Variant Name>
A A
Wistron Corporation
Title
TPS51116_+1.5V_SUS
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1D8V_S0
D D
3D3V_S5
TPS51311 PWM for 1D8V_S0
1
PC4709
SCD1U25V3KX-GP
2
3D3V_S5
PU4702
+1.8V_RUN
C 12 VDD VIN 13 Design current = 2.7985A C
PC4716
PC4718
14
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
PC4701 SC100P50V2JN-3GP VIN
1
1 2 11 PC4713
AGND SCD1U25V3KX-GP
17 PGND PGND 15
PR4709 PC4710 16
2
PGND
1 2 PR4709_1 2 1 51331_FB_1 10 FB
SC2200P50V2KX-2GP 1D8V_RUN_PW R 1D8V_S0
5K9R2F-GP 0629 Modify 51331_COMP 9 4 51331_VBST
1 PR4710 251331_VBST_1 PG4706
COMP VBST 0R0603-PAD 1 2
1
2 PC4711 GAP-CLOSE-PW R
51331_PS RES SCD1U25V3KX-GP
8 MODE
3D3V_S0 1 DY 2 1D8V_RUN_PW R PG4707
2
100KR2J-1-GP PR4714 PL4701 1 2
1
3 5 51331_SW 1 2
19,45,46,93 RUNPW ROK PGOOD SW#5
1 6 GAP-CLOSE-PW R
DY PR4708 EN SW#6
7 IND-2D2UH-46-GP-U PG4708
SW#7
SC22U6D3V5MX-2GP
57K6R2F-GP
PC4715
68.2R210.20B 1 2
SC10U6D3V5MX-3GP
2nd = 68.2R21B.10J
2
PC4714
TPS51311RGTR-GP GAP-CLOSE-PW R
2
PG4709
74.51311.073
PG4710
1 2
2
GAP-CLOSE-PWR-3-GP
PR4712 GAP-CLOSE-PW R
1
19,27,36,37,75 PM_SLP_S3# 1 2 51331_EN
10KR2J-3-GP 0920 X01 Modify:

0902 X01 Modify: stuff PC4714 22uF
B Change PR4712 to 10K from 0ohm and stuff from Brian updated. B
1
PC4717 for fine tune 1D8V_S0 ramp up sequence. PC4717

SC1U6D3V2KX-GP PG4710_1
2
1
PC4712
SC2200P50V2KX-2GP
1
0629 Modify
1 2
PC4712_1 PR4701
20KR2F-L-GP
PR4713
40D2R2F-GP
2
2
51331_FB_1 1 2 51331_FB
PG4702
1
GAP-CLOSE-PW R
PR4711
10KR2F-2-GP
2
A DN15ATI W histler A
Wistron Corporation
Title
TPS51311 for 1D8V_S0

A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
3D3V_S0
VCCSA_PWM
1
5V_S5
TPS51461 for VCCSA PR4809

4K7R2J-2-GP
1
1112 X02 Modify:
2
1
set TPS51461 PWM solution dummy field for PC4814 1 PR4808 2 D85V_PWRGD 42
SC1U10V2KX-1GP
VCCSA_PWM and APL5916 LDO solution dummy PR4806 0R0402-PAD PR4812
D
VCCSA_PWM D
2
field for VCCSA_LDO. defualt stuff VCCSA_LDO at 1R2F-GP 1 2
ST stage. VCCSA_PWM DY
1KR2F-3-GP
VCCSA_PWM
VCCSA_PWM
2
PWR_VCCSA_VID1 1 PR4804 2
SC2D2U10V3KX-1GP
VCCSA_SEL 9
PWR_VCCSA_PGOOD
0R0402-PAD
PWR_VCCSA_VID0 1 PR4805 2 H_FC_C22 9
PC4816
0R0402-PAD
VCCSA_PWM
PWR_VCCSA_EN 1 PR4801 2
2
0R0402-PAD 1.05VTT_PWRGD 37,45
VCCSA_PWM VCCSA_PWM
1
PWR_VCCSA_V5DRV DY
2
PC4810
SC1U6D3V2KX-GP
PU4801
18
17
16
15
14
13
68.R4710.10M
V5DRV
VID1
VID0
V5FILT
PGOOD
EN
PC4811 Design Current = 4.2A
PCB Footprint = QFN24-G2D25H40 SCD1U25V3KX-GP Id=17.5~26A
19 DCR=4~4.2mohm 6.6A<OCP< 7.8A
5V_S5 PGND PWR_VCCSA_BST
20 12 1 PR4807 2PWR_VCCSA_BST_R
1 2
21
PGND BST
11 0R0603-PAD Size=6.5X6.9X3 0D85V_S0
22
PGND SW#11
10
VCCSA_PWM
VCCSA_PWM 23
VIN
VIN
SW#10
SW#9
9 VCCSA_PWM PL4801
24 8
1
PC4807 PC4815 PC4813 PC4812 VIN SW#8 PWR_VCCSA_SW
25 7 1 2
GND SW#7
PC4803
PC4804
PC4805
PC4806
IND-D47UH-22-GP
COMP
MODE
1
SLEW
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
VOUT
SCD1U25V3KX-GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
VREF
VCCSA_PWM VCCSA_PWM VCCSA_PWM VCCSA_PWM
GND
2
2
PR4803
VCCSA_PWM
1
2D2R5F-2-GP
DY DYPC4808
1
2
3
4
5
6
SCD1U25V3KX-GP
TPS51461RGER-GP
68.R4710.10M
1PWR_VCCSA_SNUB
2
2
PR4811
74.51461.043 PWR_VCCSA_VOUT
PWR_VCCSA_VREF
PWR_VCCSA_COMP
PWR_VCCSA_SLEW
1 2 0D85V_S0 2nd = 68.R4710.10V
100R2F-L1-GP-U
VID0 VID1 VCCSA VCCSA_PWM VCCSA_PWM
VCCUSA_SENSE 9 1 PR4810 2
2
VCCSA_PWM 0R0402-PAD
VCCSA_PWM VCCSA_PWM
C L L 0.9V PC4801 C
1
VCCSA_PWM SCD01U50V2KX-1GP
1
PR4802 PC4809
L H 0.8V 4K99R2F-L-GP VCCSA_PWM DY SC560P50V-GP
2
VCCSA_PWM
2 PWR_VCCSA_COMP_1
H L 0.725V
H H 0.675V
0D85V_S0
1
1
PC4817
DY
SCD1U50V3KX-GP
SC3300P50V3KX-1GP 1D05V_VTT
EC4801
PG4801
VCCSA_PWM
2
PWR_VCCSA_VIN 1
VCCSA_LDO
2
2
GAP-CLOSE-PWR
PC4802 PG4802
1 2
SCD22U10V2KX-1GP
VCCSA_LDO
1
VCCSA_PWM GAP-CLOSE-PWR
PG4809
1 2
VCCSA_LDO
GAP-CLOSE-PWR
PG4810
1 2
VCCSA_LDO
1112 X02 Modify:

APL5916 for VCCSA GAP-CLOSE-PWR
PG4811
1 2
CO-LAY APL5916 related circuit for VCCSA LDO VCCSA_LDO
solution. 20100614 V1.1 GAP-CLOSE-PWR
for CRB board PG4812
5V_S5 1 2
VCCSA_LDO
3D3V_S0 GAP-CLOSE-PWR
1
B B
VCCSA_LDO
1
PC4824 PC4822 PC4820
1
PR4819 SC1U6D3V2KX-GP
Iomax=6A
2
4K7R2J-2-GP
VCCSA_LDO
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
OCP>9A 0D85V_S0
2
2
VCCSA_LDO VCCSA=0.85V PG4803

1 2
VCCSA_LDO
VCNTL
7 5
42 D85V_PWRGD POK VIN
9
VCCSA_LDO VCCSA_PWR GAP-CLOSE-PWR
VIN
PG4804
1 2 APL5916_EN 8 3 1
37,45 1.05VTT_PWRGD PR4817 0R2J-2-GP EN VOUT
4
2
VCCSA_LDO
R1 VCCSA_LDO
1
VOUT GAP-CLOSE-PWR
VCCSA_LDO VCCSA_LDO
1
PR4814 PC4818 PG4805
1
2 10KR2F-2-GP 1 2
VCCSA_LDO VCCSA_LDO
GND
FB
SC100P50V2JN-3GP
DY
2
GAP-CLOSE-PWR
VCCSA_LDO PC4825
2
1
PC4821 PWR_VCCSA_FB PC4819 PTC4801 PG4806
1
SC1U6D3V2KX-GP PU4802
DY 1 2
VCCSA_LDO
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
APL5916KAI-TRL-GP
R2
ST100U6D3VBM-7GP
2
2
1
74.05916.031 GAP-CLOSE-PWR
1
PR4816 PG4807
PR4815 80K6R2F-GP 1 2
80K6R2F-GP DY VCCSA_LDO
GAP-CLOSE-PWR
VCCSA_LDO
2
PG4808
Vout=0.8*(1+R1/R2)
2
1 2
VCCSA_LDO
GAP-CLOSE-PWR
VCCSA_LDO
PQ4801_D
VCCSA_SEL VCCSA_PWR
L 0.9V PR4813
PQ4801_5 1 2
DY VCCSA_SEL 9
H 0.8V 3D3V_S0
1
10KR2J-3-GP
DY PC4826
6
SCD1U10V2KX-4GP
2
1
A PQ4801 A
2N7002KDW-GP
DY PR4818
10KR2F-2-GP
84.2N702.A3F DY
1
2nd = 84.DM601.03F
2
PQ4801_G <Core Design>
1118 X02 Modify:

Change PTC4801 to 100u(77.21071.07L)
Wistron Corporation
from 150u from power team Brian updated.
1122 X02 Modify:
Updated VCCSA_LDO circuit from Power Title
team Brian updated.
TPS51461_VCCSA
A2
QUEEN&NIRVANA 15 A00
5 4 3 2 1
SSID = VIDEO 3D3V_S0
SSID = VIDEO
1
2
0909 X01 Modify:
Change LCD1 to 20.F1816.030 for 30pin
Re-assign LCD1 pin define base on Roy updated SRN2K2J-1-GP
cable pin define list. RN9403
LCD POWER for ROSA
LVDS CONNECTOR
4
3
DCBATOUT_LCD 17 LVDS_DDC_CLK_R
LCD1 17 LVDS_DDC_DATA_R
31
NP1
1
2 0902 X01 Modify:

3 Add 2nd source 74.09724.09F on
4 U4901 sync with Annie.
5 LCD_BRIGHTNESS R4902 2 1 33R2J-2-GP L_BKLT_CTRL 17 LCDVDD 3D3V_S0
6 3D3V_CAMERA_S0 BAT54CPT-GP
7 USB_CAMERA#
8 USB_CAMERA A00 0103 not co-lay 1 U4901
17 LVDS_VDD_EN
9 Layout 40 mil
10 3 LCDVDD_EN 1 5
EN IN#5
11 AUD_DMIC_CLK 29 2 GND
12 AUD_DMIC_IN0 29 27 LCD_TST_EN 2 3 OUT IN#4 4
1
13
49K9R2F-L-GP
LVDSA_CLK 17
1
R4905
14 LVDSA_CLK# 17 D4901 C4907
SC4D7U6D3V3KX-GP
15 BLON_OUT_C C4908 G5285T11U-GP
SC4D7U6D3V3KX-GP
16 LVDSA_DATA2 17 83.R2003.E81
2
SCD1U50V3KX-GP
17 LVDSA_DATA2# 17 2ND = 83.00054.Q81 74.05285.07F
2
EC4907
18
19 LVDSA_DATA1 17 2nd = 74.09724.09F
20 LVDSA_DATA1# 17
21 1122 X02 Modify:
22 stuff EC4907 0.1uF from
LVDSA_DATA0 17 EMC Neo suggestion.
23 LVDSA_DATA0# 17
24 LVDS_DDC_DATA_R 17
25 LVDS_DDC_CLK_R 17
26 LCD_TST_C 1 TP4904TPAD14-GP
27 3D3V_S0 1 R4907 2
28 100KR2J-1-GP
29 LCDVDD RN4901
30 BLON_OUT_C 1 4
SCD1U10V2KX-5GP
BLON_OUT 27
C4901
NP2 LCD_TST_C 2 3 LCD_TST 27

1
32 C4902
PS-CON30-GP DY SC1U6D3V2KX-GP SRN100J-3-GP

2
1122 X02 Modify:

20.F1816.030 Change RN4901 to 100ohm 4p from 8p
for improve layout place.
2nd = 20.F1860.030
USB_CAMERA#
18 USB_PN12 69.10103.041 USB_CAMERA
2nd = 69.10084.071
FILTER-4P-6-GP
3
1
4 TPNL1
CLOSED TO LVDS CONN LCD1
TPNL_5V
TOUCH PANEL 5V_S0
5 R4904
18 USB_PP12 TR4902
1
TPNL 1
TPNL TPNL2
SCD1U10V2KX-4GP
SC10U6D3V5KX-1GP
1122 X02 Modify:
C4911
TPNL DY
1
Change TR4902 CM choke to 69.10103.041
C4910
2 USB_PN0_C 0R0402-PAD-2-GP
and un-stuff R4908,R4909 from EMC Neo Suggestion. 3 USB_PP0_C
SCD1U50V3KX-GP
4 A00 1230
2
EC4908
1122 X02 Modify:
6 stuff C4908 0.1uF from
EMC Neo suggestion.
DCBATOUT_LCD DCBATOUT
ACES-CON4-17-GP-U USB_PN0_C
18 USB_PN0
F4901
2 1
20.F1621.004 USB_PP0_C
1
EC4906
SCD1U50V3KX-GP
2nd = 20.F1561.004 TR4901

1
POLYSW -1D1A24V-GP-U 3rd = 20.F1686.004

SCD1U50V3KX-GP
C4904
C4905
1 2
SC1KP50V2KX-1GP
69.50007.A31 DY
SCD1U50V3KX-GP
2
0916 X01 Modify:

EC4909
TPNL
2
0913 X01 Modify: Change TPNL1 to 20.F1621.004 from 4 3 A00 1229

2nd = 69.50007.A41 Reserved EC4910~EC4915 on LVDS signal Double updated EMN&DXF.
for EMC suggestion. 0917 X01 Modify: FILTER-4P-6-GP
Add 2nd source 20.F1561.004;3rd source
For EMI request
20.F1686.004 on TPNL1 from updated 69.10103.041
connector list.
Close to LVDS connector 2nd = 69.10084.071
LVDSA_DATA0
LVDSA_DATA0#
LCD_BRIGHTNESS LVDSA_DATA1
Camera Power LCD_TST_C LVDSA_DATA1#
18 USB_PP0
3D3V_S0 3D3V_CAMERA_S0 LVDSA_CLK# LVDSA_DATA2
LVDSA_CLK LVDSA_DATA2# 1122 X02 Modify:
1 F4902 2 Swap TR4901 pin4,3 and pin2,1 each other
1
0R0603-PAD EC4904 EC4905 EC4901EC4902EC4910 EC4912 EC4911EC4913EC4914EC4915 base on Connie swap report.
Change TR4901 CM choke to 69.10103.041
DY DY DY DY DY
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
1
EC4903 and un-stuff R4911,R4912 from EMC Neo Suggestion.

DY DY DY DY DN15ATI W histler
2
Change R4911,R4912 to 0603 from 0402.

C4903
DY DY
SCD1U10V2KX-5GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
SC10U6D3V5KX-1GP
2
Wistron Corporation
Title
LCD Connector
A3
QUEEN 15 A00
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
CRT Connector
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
0721 Modify:
Change HDMI1 part number to 22.10296.271 from
SSID = VIDEO HDMI Level Shifter & CONNECTOR 22.10296.211 base on ME latest EMN and DXF.
0831 X01 Modify:
R5101 R5106
A00 1229 HDMI CONN Change HDMI1 part
22.10296.271 base
0910 X01 Modify:
number to 22.10296.311 from
on ME Double updated.
HDMI_CLK_R_C HDMI_CLK_R_C_CON HDMI_DATA1_R_C 1 HDMI_DATA1_R_C_CON HDMI_PLL_GND Change HDMI1 part number to 22.10296.331 from
1 2 2 22.10296.311 base on ME Double updated.
HDMI1
2
0R0402-PAD-2-GP 0913 X01 Modify:
0R0402-PAD-2-GP 22
Add R5101~R5108and reserved TR5101~TR5104 R5123 20
on all of HDMI differential pair for EMC suggestion. HDMI_DATA2_R_C_CON
DY 0R2J-2-GP 1
D
D D
2
1
3 HDMI_DATA2_R_C#_CON TPAD14-GP AFTP5101 1 DDC_DATA_HDMI
Q5103 4 HDMI_DATA1_R_C_CON
2N7002K-2-GP 5
6 HDMI_DATA1_R_C#_CON
84.2N702.J31 HDMI_DATA0_R_C_CON
0806 7
2ND = 84.2N702.031 8
S
R5102 R5105 3D3V_VGA_S0 9 HDMI_DATA0_R_C#_CON
HDMI_CLK_R_C# 1 2 HDMI_CLK_R_C#_CON HDMI_DATA1_R_C# 1 2 HDMI_DATA1_R_C#_CON 10 HDMI_CLK_R_C_CON 0716 Modify:
0R0402-PAD-2-GP 0R0402-PAD-2-GP 11 Add F5101 1A FUSE for DELL suggesiton.
12 HDMI_CLK_R_C#_CON 0720 Modify:
1
HDMI_DATA0_R_C 1R5104 2 HDMI_DATA0_R_C_CON HDMI_DATA2_R_C 1R5108 2 HDMI_DATA2_R_C_CON 13 Stuff F5101 FUSE from DELL suggestion.
R5113 14 5V_CRT_S0_R
0R0402-PAD-2-GP 0R0402-PAD-2-GP DY 100KR2J-1-GP 15 DDC_CLK_HDMI
16 DDC_DATA_HDMI
17 A00 1223 HDMI leakage
2
18
19
21
1
23 C5102
3D3V_S0
X02 10.28
SCD1U10V2KX-5GP
2
SKT-HDMI23-2-GP-U1
1
R5103 R5107 22.10296.331 R5112
HDMI_DATA0_R_C# 1 HDMI_DATA0_R_C#_CON HDMI_DATA2_R_C# 1 HDMI_DATA2_R_C#_CON 10KR2J-3-GP
2 2 2nd = 22.10296.311
0R0402-PAD-2-GP 0R0402-PAD-2-GP
2
C C
27 HDMI_IN#
4
Q5105
2N7002KDW -GP
HDMI_CLK# C5103 1 2 SCD1U10V2KX-5GP HDMI_CLK_R_C#
85 HDMI_CLK#
HPD_HDMI_CON
HDMI_CLK C5104 1 2 SCD1U10V2KX-5GP HDMI_CLK_R_C
3
85 HDMI_CLK
HDMI_DATA0# C5105 1 2 SCD1U10V2KX-5GP HDMI_DATA0_R_C# GPU_HDMI_HPD 85
85 HDMI_DATA0# HDMI_DATA0 C5106 SCD1U10V2KX-5GP HDMI_DATA0_R_C
85 HDMI_DATA0 1 2
3D3V_S0
2 1 PEX_RST# 83,85,86
R5116 1KR2F-L-GP
HDMI_DATA1# C5110 1 2 SCD1U10V2KX-5GP HDMI_DATA1_R_C#
85 HDMI_DATA1# DY
3
HDMI_DATA1 C5107 1 2 SCD1U10V2KX-5GP HDMI_DATA1_R_C
85 HDMI_DATA1
1 2HDMI_HPD_B 1 Q5102
HDMI_DATA2# C5108 1 2 SCD1U10V2KX-5GP HDMI_DATA2_R_C# R5111 1KR2F-L-GP PMBS3904-1-GP
85 HDMI_DATA2# HDMI_DATA2 C5109 SCD1U10V2KX-5GP HDMI_DATA2_R_C 0629 Modify
1 2
2
85 HDMI_DATA2
1
R5110 84.03904.L06 HDMI_HPD_E 1 2 HDMI_HPD_DET 85
3D3V_VGA_S0 5V_S0 1MR2F-GP R5125 0R2F-N1-GP
Close to HDMI Connector 2nd = 84.03904.P11 DY
1
3rd = 84.03904.T11
8
7
6
5
8
7
6
5 R5117
2
1
2
RN5106 RN5107 0927 10KR2J-3-GP
SRN470J-5-GP SRN470J-5-GP R5114 R5115 DY
0630 SWAP RN5106 0R0402-PAD-2-GP DY
2
B 0630 SWAP RN5107 A00 B
0R2J-2-GP
X02 1110
1
2
3
4
1
2
3
4
2
1
3D3V_S0 HDMI_PLL_GND 0726 For NV 0629 Modify:
Utilize Q5104 2N7002 instead of PCA9509 Level
1
shifter base on Intel DG recommand on HDMI DDC.

R5109 5V_CRT_S0_R A00 1228
DY 20KR2J-L2-GP 0714 Modify:
2
1
Stuff R5109 20K PH to 3D3V_S0. 0810
RN5116
2
3
4
SRN2K2J-1-GP 3D3V_VGA_S0
HDMI_OE# 1 2 HDMI_IN# 27 Optimus
R5127 0R0402-PAD RN5101
SRN2K2J-1-GP
3
4
0707 Modify:
D
Add Q5101,R5109,R5127 for HDMI_IN# to KBC. 0923 SWAP

Q5104
2
1
Q5101
DY 2N7002K-2-GP GPU_HDMI_CLK 4 3 DDC_CLK_HDMI
85 GPU_HDMI_CLK
84.2N702.J31
5 2
2ND = 84.2N702.031
6 1
G
HPD_HDMI_CON GPU_HDMI_DATA 2N7002KDW -GP

85 GPU_HDMI_DATA
84.2N702.A3F
DDC_DATA_HDMI
2nd = 84.DM601.03F
A
Routing Guidelines: <Variant Name>
A
CTRLDATA must be routed longer than CTRLCLK within 1000 mils (25.4 mm).
The total delay on CTRLDATA should be longer than CTRLCLK. Wistron Corporation
Title
HDMI Level Shifter/Connector

A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
LVDS_Switch
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
SSID = User.Interface
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Size
ITP/Fan Connector
Document Number Rev
A3
QUEEN 15 A00
5 4 3 2 1
SSID = SATA SATA HDD Connector
HDD1
0629 Modify:
Move All of 0.01uF cap closed to HDD 23
connector base on Layout guideline.
20100625 V1.2 NP1
1
21 SATA_TXP0 SCD01U16V2KX-3GP 2 1 C5614 SATA_TXP0_C 2

21 SATA_TXN0 SCD01U16V2KX-3GP 2 1 C5613 SATA_TXN0_C 3
4
21 SATA_RXN0 C5616 1 2 SCD01U16V2KX-3GP SATA_RXN0_C 5
21 SATA_RXP0 C5615 1 2 SCD01U16V2KX-3GP SATA_RXP0_C 6
7
3D3V_S0 8
9
1
C5604 C5601 10
11
DY DY 12
2
13
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
5V_S0 14
1123 X02 Modify: 15
1
stuff EC5601 180pF from RF C5605 C5606 16
fine tune result. 17
18
SCD1U10V2KX-5GP
79 FFS_INT2
SC10U10V5ZY-1GP
2
2
3D3V_S0 19
TPAD14-GP TP5601 1HDD1_20 20
1
TPAD14-GP TP5602 1HDD1_21 21

EC5601 TPAD14-GP TP5603 1HDD1_22 22
SC180P50V2JN-1GP NP2
2
24
TYCO-CON22-1-GP-U2
20.F1011.022
2nd = 62.10065.081
0810
A00 delete 62.10065.121
0901 Add 2nd.
0906 Add 3rd.
SATA Zero Power ODD

0629 Modify:
ODD Connector 20100625 V1.2

0629 Modify:
Move All of 0.01uF cap closed to ODD
connector base on Layout guideline. 22 SATA_ODD_PW RGT
Move R5601 PH 10K to RN5601 PH.
U5601
SATA_RX- and SATA_RX+ Trace G547F1P81U-GP ODD_PW R_5V
ODD1 5V_S0
8
Length match within 20 mil 4 5
EN/EN# OC# ODD_PW R_5V
NP1 Mars: 3 IN#3 OUT#6 6 100 mil
S1 Exchange ODD and ESATA differential pair each other. 2 IN#2 OUT#7 7
1 GND OUT#8 8
1
S2 SATA_TXP4_C C5612 1 2 SCD01U16V2KX-3GP C5609
SATA_TXP4 21 When the drive is powered on, the FET to the MD/DA pin drive is OFF.
1
S3 SATA_TXN4_C C5611 1 2 SCD01U16V2KX-3GP SATA_TXN4 21 SC10U6D3V5KX-1GP C5610
SC10U6D3V5KX-1GP
S4 When the drive is powered off, the FET to the MD/DA pin is ON
2
S5 SATA_RX4-_C C5607 1 2SCD01U16V2KX-3GP SATA_RXN4 21 74.00547.C79
2
S6 SATA_RX4+_C C5608 1 2SCD01U16V2KX-3GP SATA_RXP4 21 2ND = 74.02191.079
S7
5V_S0
P1 ODD_PW R_5V
SATA_ODD_PRSNT# 22
2
P2
R5605
P3
P4 SATA_ODD_DA#_C 0R2J-2-GP 2 R5602 100KR2J-1-GP ,
DY 1 SATA_ODD_DA# 18
P5

1
P6
1
NP2 R5604
DY 10KR2J-3-GP 0629 Modify: SATA_ODD_DA#_C
ODD_PWRGT#
9
Move R5601 PH 10K to RN5601 PH.
SKT-SATA7P-6P-40-GP-U
2
20100625 V1.2 3D3V_S0

62.10065.E01 RN5601
6
2nd = 62.10065.D01 SATA_ODD_PW RGT 4 1 <Variant Name>

3rd = 62.10065.D61 SATA_ODD_DA# 3 2 Q5601
2N7002KDW -GP
SRN10KJ-5-GP 84.2N702.A3F
0614 Modify: 2nd = 84.DM601.03F Wistron Corporation
1
Change ODD1 connector part number to 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
22.10300.421 base on ME EMN and DXF. Taipei Hsien 221, Taiwan, R.O.C.
0707 Modify: SUPPORT ZERO SATA ODD
Change ODD1 connector part number to Title
62.10065.E01 base on latest EMN and DXF.
SATA_ODD_PW RGT SATA_ODD_DA# HDD/ODD
0707 Modify: Size Document Number Rev
Change Q5601 to DUAL 2N7002 for isolate MD/DA signal between PCH and ODD. A3
QUEEN 15 A00
5 4 3 2 1
SSID = ESATA
D
USB CHARGER D
0803 Modify:
0629 Modify Change U5702 USB CHARGER circuit to
PI5USB14550 from MAX14556.
U5702
0809 1 11 0R0402-PAD
USB_PP8_R S0 GND CB
2 D+ S1 10 1 2 USBCHARGER_CB0 27
USB_PN8_R 3 9 R5721
D- Y+ USB_PP8 18
4 GND Y- 8 USB_PN8 18 0809
0806 5 A+ VDD 7 5V_S5
A- 6
2
1122 X02 Modify: PI5USB14550AZEE-GP
Change TR5701CM choke to 69.10103.041 C5701
and un-stuff R5718,R5719 from EMC Neo Suggestion. Switch Control Bit:
1
1123 X02 Modify:
CB=0 (AM):auto detection charger identification active.
SCD1U10V2KX-4GP
Change R5718,R5719 to 0603 from 0402.
S0
0
S1
0 Auto
CB=1 (PM):connect DP/DM to TDP/TDM.
0 1
1 0
1 1 D+/- connects to Y+/-
C C
A00 1229
ESATA CONN
USB_PN8_R USB_PN8_C
TR5701
1 2
4 3
0831
5V_USB1_S3 ESATA1
FILTER-4P-6-GP R5722 0R0402-PAD
USB_PP8_R
69.10103.041 USB_PP8_C 1 VBUS DT1 12
13
ESATA1_D1 1 2
DT2 USBDET_CON# 27
2nd = 69.10084.071 21 SATA_TXP5 C5707 1 SCD01U16V2KX-3GP

2 SATA_TXP5_C 6 4
C5708 1 SCD01U16V2KX-3GP SATA_TXN5_C A+ GND
21 SATA_TXN5 2 7 A- GND 5 1
GND 8
21 SATA_RXP5 C5705 1 SCD01U16V2KX-3GP
2 SATA_RXP5_C 10 11
C5702 1 SCD01U16V2KX-3GP SATA_RXN5_C B+ GND AFTP5717
21 SATA_RXN5 2 9 B- GND 14
15 AFTE14P-GP
USB_PP8_C GND
3 D+ GND 16
USB_PN8_C 2 17
D- GND
close to ESATA1 0629 Modify: SKT-ESATA-USB-11P-6-GP-U
AFTE14P-GP 1 5V_USB1_S3 Move All of 0.01uF cap closed to ESATA
AFTE14P-GP 1 USB_PN8_C connector base on Layout guideline. 22.10321.W11
AFTE14P-GP 1 USB_PP8_C 0706 Modify: 2nd = 22.10339.261
B Change ESATA1 part number to 22.10321.F71 B
base on latest EMN and DXF.
AFTP5716
0713 Modify:
AFTP5715
AFTP5703
Add USBDET_CON# on ESATA1 pin15 for E-SATA USB 2.0 Combo
USB temporary detect solution ESATA1 CONN
should be searched for detect type connector.CE/H=-0.16/2.83mm with detect function
0719 Modify:
ME Double provide temporary foxconn ESATA conn
22.10290.141 for SSI stage function test.
A <Core Design> A
Wistron Corporation
Title
ESATA
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
SSID = AUDIO
D D
6SHDNHU&RQQHFWRU
ACES-CON4-7-GP-U
R5801 0R0402-PAD-2-GP 6
1 2 AUD_SPK_L-_C 4
29 AUD_SPK_L- AUD_SPK_L+_C
C
29 AUD_SPK_L+ 1R5802 0R0402-PAD-2-GP
2 3 C
1R5803 0R0402-PAD-2-GP
2 AUD_SPK_R-_C 2
29 AUD_SPK_R-
1R5804 0R0402-PAD-2-GP
2 AUD_SPK_R+_C 1
29 AUD_SPK_R+
5
A00
SPK1
SC470P50V-2-GP
SC470P50V-2-GP
SC470P50V-2-GP
SC470P50V-2-GP
20.F0772.004
2
2
EC5801
EC5802
EC5803
EC5804
0913 X01 Modify:
2nd = 20.F1804.004 Change SPK1 to 20.F0772.004 from
20.F1647.004 from Double updated.
1
1
0914 X01 Modify:
Re-assign SPK1 pin define base on
1110 X02 Modify: Roy updated excel file for 20.F0772.004
1122 X02 Modify: Add 2nd 20.F1804.004 on SPK1 from
stuff EC5801~EC5804 470pF from EMC ME updated connector list.
Neo suggestion.
B B
TPAD14-GP AFTP5801 1 AUD_SPK_L-_C

TPAD14-GP AFTP5802 1 AUD_SPK_L+_C
TPAD14-GP AFTP5803 1 AUD_SPK_R-_C
TPAD14-GP AFTP5804 1 AUD_SPK_R+_C
<Core Design>
A
Wistron Corporation A
Title
SPEAKER CONN
A4
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
Notes:
SSID = Flash.ROM The total SPI interface signal between EC and PCH
SPI FLASH ROM (4M byte) for PCH cant not exceed 6500mil. The mismatch between
3D3V_S5 SPI signal must be within 500mil
0701 Modify:
3D3V_S5 Change RN6001 4.7K to R6003,R6004,R6005
4.7K 0402 for layout routing.
D D
1
C6002
C6001
SC10U6D3V5KX-1GP
2
2
R6003 R6004 R6005
DY
SCD1U10V2KX-5GP
4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP
1
SPI_HOLD_0#
3D3V_S5
U6001
21,27 SPI_CS0#_R 1 CS# VCC 8

21,27 SPI_SO_R 1 2 SPI_SO 2 7
R6001 33R2J-2-GP SPI_W P# DO HOLD#
3 WP# CLK 6 SPI_CLK_R 21,27
4 VSS DI 5 SPI_SI_R 21,27
1
DY
1
EC6002 W 25Q32BVSSIG-1-GP
SC4D7P50V2CN-1GP EC6003 DY DY EC6001
72.25Q32.A01
2
SC10P50V2JN-4GP
SC4D7P50V2CN-1GP
2
2
2nd = 72.25320.C01
3rd = 72.25P32.C01 0917 X01 Modify:
EC6001 change to 10p from 4.7p and
C 0629 Modify: default stuff from Neo suggestion. C
Change U6001 part number to 72.25320.C01
base on Sourcer provide recommand ROM list.
X02
X02
SSID = RBATT
3D3V_AUX_S5
B B
RTC_AUX_S5 Q6001 A00 1224 Update RTC1
2
+RTC_VCC
3 RTC1
1 RTC_PW R 1 R6002
2 1 PWR
2
1KR2J-1-GP 2
C6003 GND
CH715FPT-GP NP1
SC1U6D3V2KX-GP NP1
NP2
1
TPAD14-GP TP6001 NP2

83.R0304.B81 1
2nd = 83.00040.E81
Width=20mils BAT-330DG02PSS0301CE-GP-U
62.70001.051
2nd = 62.70014.001
1111 X02 Modify: 3rd = 62.70001.061
Add Q6002,R6007 fo FACTORY RTC detect function TPAD14-GP TP6002 1 +RTC_VCC
R6006
1 DY 2
100R2J-2-GP
X02 1111 0615 Modify:
2N7002K-2-GP Change RTC1 connector part number to 62.70001.051
RTC_PW R G base on ME EMN and DXF.
1
D RTC_DET# 22
R6007
10MR2J-L-GP S
A
Q6002 VccRTC is now connected to VccDSW3_3 <Variant Name> A
2
84.2N702.J31
2ND = 84.2N702.031 through the Schottky diode instead of the 3.3V Sus well. Wistron Corporation
Title
Flash/RTC
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
SSID = USB CRT Board and COMBO USB Power

USB_OC#8_9 18
5V_S5
Support 2A
U6101 5V_USB1_S3
at least 160 mil 1 GND FLG1 8 at least 80 mil

2 IN OUT1 7
27 USB_PW R_EN# 3 EN1# OUT2 6
4 5 A00 1221
22 USB2_CRT_ON# EN2# FLG2
1
C6103 C6101
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
D C6102 TC6101 D
AP2182SG-13-GP SC1U10V2KX-1GP ST100U6D3VAM-3-GP
2
5V_USB2_S3 80.10715.B1L
74.02182.071 2nd = 77.C1071.20L
1123 X02 Modify: 2nd = 74.00546.A7D at least 80 mil
Removed C6105,C6103.
SC10U6D3V5KX-1GP
USB_OC#0_1 18
TC6102
3rd = 74.02062.079
1
1122 X02 Modify: C6104
Change U6101 to dual USB power switch from single SC1U10V2KX-1GP
2
for Layout limitation and placement.
1123 X02 Modify:
Change U6101 1st(74.02182.071);2nd(74.00546.A7D)
;3rd(74.02062.079) from Sourcer Harrison suggestion.
C C
B B
<Core Design>
A A
Wistron Corporation
Title
USB Power SW
QUEEN&NIRVANA 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
R6303
1 2
DY
0R2J-2-GP
Q6301
D BT_LED G DY Bluetooth Module conn. D
D W LAN_W W AN_LED# A00 1224 Update BT1

BT1
S 15
NP1
AFTP6301 1 BLUETOOTH_DET# 1 2 BT_ACT 3D3V_S0
2N7002K-2-GP
84.2N702.J31 W LAN_ACT 3 DY 4 x01 change tolerant 20091118
AFTP6302 1 BDC_ON 5 6 USB_PP3
2ND = 84.2N702.031 BLUETOOTH_EN 7 8 USB_PN3
AFTP6304 1 BT_LED 9 10
1
AFTP6305 1 BLUETOOTH_GPIO3 11 12 C6301
AFTP6307 1 BLUETOOTH_GPIO5 13 14 SC2D2U6D3V3MX-1-GP
NP2
2
16 0721 Modify:
1 AFTP6306 Change C6301 to 78.22510.5BL follow
0722 Modify: common parts data base.
Add Q6301 and combine BT_LED to
HRS-CONN14D-GP-U1 DY
WLAN_WWAN_LED#. 20.F0987.014
2nd = 20.F1500.014
68,82 W LAN_W W AN_LED#
18 USB_PP3 AFTP6309 1 W LAN_ACT
18 USB_PN3 AFTP6310 1 BLUETOOTH_EN
82 BT_ACT BT_ACT AFTP6308 1 BT_ACT
27,82 BLUETOOTH_EN BLUETOOTH_EN AFTP6311 1 3D3V_S0
82 W LAN_ACT W LAN_ACT AFTP6312 1 USB_PP3
AFTP6313 1 USB_PN3
C C
0709 Modify:
PM confirmed there is no stand-alone BT module,
so DY BT1 connector, add BT enable signal
EC6301
SC220P50V2KX-3GP
10KR2J-3-GP
100KR2J-1-GP
1
1
and 5V_S5 power option on WLAN connector pin 51.
1
0712 Modify:
R6301
R6302
Stuff BT relatek component to verify function.
DY DY DY
2
2
B B
A <Core Design> A
Wistron Corporation
Title
Bluetooth
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
Finger Printer Connector
0707 Modify:
Add FP_DET# signal on FP1 pin1.
0715 Modify:
Add FP_DET# signal on FP1 pin1. FP1
0806 Swap pin.
0810 Change to 4 pin. 7
1123 X02 Modify:
0827 Change to 6 pin. Add C6402 0.1uF,C6403 180pF and stuff C6401 1
47pF from RF fine tune result.
2
3
3D3V_S0 Biometric_USBPN 4 DN15
SC47P50V2JN-3GP
Biometric_USBPP 5
EC6401
6
SCD1U10V2KX-4GP
SC180P50V2JN-1GP
1
1
EC6402
EC6403
8
2
ACES-CON6-13-GP
C 20.K0320.006
2nd = 20.K0382.006 C
DN15
18 USB_PN2 1 R6403 2 Biometric_USBPN AFTP42 DY 1 3D3V_S0
0R2J-2-GP AFTP43 Biometric_USBPN
AFTP44
DY 1
Biometric_USBPP
DY 1
A00 1229 0615 Modify:

0917 X01 Modify:
stuff TR6401 and un-stuff R6403,R6404 Change FP1 connector part number to 20.K0320.004
at X01 stage from EMC Neo suggestion. base on ME EMN and DXF.
0630 Modify:
Change FP1 connector part number to 20.K0320.006
B R6404 B
base on ME EMN and DXF.
18 USB_PP2 1 2 Biometric_USBPP
0R2J-2-GP 0707 Modify:
DN15
Reassign Figer print pin define base on EXCEL FILE.
0713 Modify:
Reassign Figer print pin define base on EXCEL FILE.
Removed FP_DET# on FP1.
A <Core Design> A
Wistron Corporation
Title
Size
RESERVED
Document Number Rev
A3 QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
RESERVED
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
0706 Modify:
FRONT POWER LED NEED confirm with ME actual
Change FPOWER_LED part number to
83.01221.R70 base on latest EMN and DXF.
Need change to LOW actived from KBC GPIO FPOWER_LED part number.
Q6801
R2
E
5V_S5
FPLED1 A00 1223 WLAN_LED
3
PW RLED#_C B 0706 Modify:
R1
C LED_PW R 1 2 FPOW ER_LED_A 1A K2 WLAN__LED# rename to WLAN_WWAN_LED#. 5V_S0
D R6806 390R2J-1-GP 0629 Modify Q6806 D
1
R2
EC6801 LED-W -27-GP E
PDTA143ET-GP
1 2 POW ER_SW _LED_B R6814
1 2 Q6806_B B
DYSC220P50V2KX-3GP R6808 1KR2J-1-GP 83.01221.R70 63,82 W LAN_W W AN_LED# 15KR2J-1-GP
R1
C
84.00143.M11
2
2nd = 84.02143.011 2nd = 83.00110.R70
RN6802 3rd = 84.00143.N11 1 2 POW ER_SW _LED_C PDTA143ET-GP
1 4 R6811 1KR2J-1-GP A00 1229 delete Liteon for package
27 PW RLED#
2 3
21 SATA_LED# 84.00143.M11
2nd = 84.02143.011
SRN15KJ-3-GP
X02 1116 NEED confirm with ME actual
5V_S0 3rd = 84.00143.N11
HDD_LED part number.
Q6805 A00 1223
HDLED1
R2 0706 Modify:
E
3
SATA_LED#_C B Change HDD_LED part number to
R1
C SATA_LED_R 1 2 HDD_LED_A 1A K2 83.01221.R70 base on latest EMN and DXF.
R6812 390R2J-1-GP
SC220P50V2KX-3GP
SATA HDD LED(White)
1
0923 X01 Modify: W LED1 A00 1223
EC6810
LED-W -27-GP
PDTA143ET-GP Add 2nd source 83.00110.J70 on FPOWERLED1
DY 83.01221.R70
3
HDDLED1,WLANLED1 from Sourcer Anya suggestion.
84.00143.M11
2
2nd = 84.02143.011 2nd = 83.00110.R70 2K A1 W LAN_LED_A 1 2 W LAN_LED_R
3rd = 84.00143.N11 R6815
SC220P50V2KX-3GP
1
390R2J-1-GP
EC6811
LED-W -27-GP
A00 1229 delete Liteon for package 83.01221.R70 DY
2
2nd = 83.00110.R70
A00 1229 delete Liteon for package
NEED confirm with ME actual
C 5V_S5 0706 Modify: C
HDD_LED part number.
Battery LED2(WHITE_LED) Q6807
R2
E
Change WLAN_LED part number to
83.01221.R70 base on latest EMN and DXF.
B A00 1223
Need change to LOW actived from KBC GPIO R1
C W HITE_LED_BAT 1 2 BAT_W HITE 0923 X01 Modify:
0702 Modify: R6801 390R2J-1-GP Add 2nd source 83.00110.J70 on FPOWERLED1
SC220P50V2KX-3GP
1
Rename CHARGE_LED# to CHG_AMBER_LED# CHLED1 HDDLED1,WLANLED1 from Sourcer Anya suggestion.
EC6807
Rename DC_BATFULL# to BATT_WHITE_LED#. PDTA143ET-GP WHITE
RN6801 DY 2
84.00143.M11
WHITE
2
+
1 4 W HITE_LED_BAT# 2nd = 84.02143.011 3
27 BATT_W HITE_LED#
-
2 3 AMBER_LED_BAT# 3rd = 84.00143.N11 1
+
27 CHG_AMBER_LED# ORANGE
SRN15KJ-3-GP 5V_S5 ORANGE

Q6808
LED-OW -8-GP
Battery LED1(AMBER_LED) B R1
R2
E
83.01222.X80
C AMBER_LED_BAT 1 2 BAT_AMBER 2nd = 83.00327.D70
R6803 390R2J-1-GP
A00 delete 83.01108.070
PDTA143ET-GP
1
0923 X01 Modify:
Need change to LOW actived from KBC GPIO EC6809 Add 2nd source 83.00327.D70 on
84.00143.M11
2nd = 84.02143.011
DY SC220P50V2KX-3GP CHARGERLED1from Sourcer Anya suggestion.
2
3rd = 84.00143.N11 0706 Modify:
Change TP_LOCK_LED part number to
TPLOCK LED NEED confirm with ME actual

83.19217.J70 base on latest EMN and DXF.
5V_S0
B HDD_LED part number. B
Q6804 0706 Modify:
R2 A00 20110103 Add PWRBTN2 for DQ15,PWRBTN1 FOR DN15.
0629 Modify E
R6807
1 2 Q6804_B B R6813 TPLED2 A00 20110103
27 TP_LOCK_LED# 15KR2J-1-GP
R1
TP_LOCK_LED_R
C 1 2TP_LOCK_LED_A A DN15 K
A00 1223
SC220P50V2KX-3GP
1
390R2J-1-GP
EC6803
LED-Y-57-GP
Need change to LOW actived from KBC GPIO PDTA143ET-GP
DY 0923 X01 Modify: 83.01921.P70
2nd = 83.00190.S7A PW RBT2
84.00143.M11
2
Add 2nd source 83.00190.Z70 on TPLOCKLED1

2nd = 84.02143.011 TPLOCKLED2 from Sourcer Anya suggestion.
5
3rd = 84.00143.N11
TPLED1 1
A K A00 20110103
DQ15 KBC_PW RBTN#_C 2
0706 Modify: LED-Y-57-GP POW ER_SW _LED_C 3
DN15
Change TP_LOCK_LED1 part number to POW ER_SW _LED_B 4
83.19217.J70 base on latest EMN and DXF. 83.01921.P70
2nd = 83.00190.S7A
6
ACES-CON4-10-GP-U
27 KBC_PW RBTN# 1 2 PW RBT1 A00 1223 20.K0320.004

R6802 100R2J-2-GP 5 2nd = 20.K0382.004
1
KBC_PW RBTN#_C 2
A POW ER_SW _LED_C 3
DQ15 <Core Design>
A
POW ER_SW _LED_B 4
0715 Modify:
Removed PWR_BTN_LED# control circuit
6 Wistron Corporation
base on Dell feedback. KBC_PW RBTN#_C 1 AFTP6801 Taipei Hsien 221, Taiwan, R.O.C.
ACES-CON4-10-GP-U POW ER_SW _LED_C 1 AFTP6802
POW ER_SW _LED_B 1 AFTP6803 Title
20.K0320.004
2nd = 20.K0382.004 LED Bard/Power Button
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
SSID = KBC SSID = Touch.Pad

0715 Modify:
Add R6908,R6909 for TPAD1 co-lay power option.
Internal KeyBoard Connector
0630 Modify:
Change KB1 part number to 20.K0565.030 KROW [0..7] 27
D D
base on ME updated EMN and DXF. 0624 Modify:
Removed TP LOCKED CONTROL combin TP_VDD 5V_S0
KCOL[0..16] 27 with KEYBOARD Function KEY. R6908
1 2
KB1 1 AFTP45 DY
31 0630 Modify: 0R2J-2-GP
1 0713 Modify: Change TPAD1 part number to 20.K0320.006 3D3V_S0
KB_DET# 21 Change TPAD1 power source to 3D3V_S0 from base on ME updated EMN&DXF. R6909
KROW 7 5V_S0 base on DELL latest spec A02. 0712 Modify:
2 1 Change TPAD1 part number to 20.K0320.004 1 2
3 KROW 6 1 AFTP46
4 KROW 4
KROW 2
1 AFTP47
AFTP48
TouchPad Connector from 20.K0320.006.
0R2J-2-GP
5 1
6 KROW 5 1 AFTP49
7 KROW 1 1 AFTP50 TP_VDD TP_VDD
8 KROW 3 1 AFTP51
9 KROW 0 1 AFTP52
10 KCOL5 1 AFTP53 0721 Modify:
11 KCOL4 1 AFTP54 SWAP RN6901
1
2
12 KCOL7 1 AFTP55
1
13 KCOL6 1 AFTP56 RN6901 C6901
14 KCOL8 1 AFTP57 SRN10KJ-5-GP SCD1U10V2KX-5GP
15 KCOL3 1 AFTP58
2
16 KCOL1 1 AFTP59 TPAD1
17 KCOL2 1 AFTP60 6
4
3
18 KCOL0 1 AFTP61
19 KCOL12 1 AFTP62 4
20 KCOL16 1 AFTP63 27 TPCLK 3
21 KCOL15 1 AFTP64 27 TPDATA 2
C 22 KCOL13 1 AFTP65 C
23 KCOL14 1 AFTP66 1
1
24 KCOL9 1 AFTP68
25 KCOL11 1 AFTP67 C6902 DY DY C6903 1 5
26 KCOL10 1 AFTP69 SC33P50V2JN-3GP SC33P50V2JN-3GPAFTP71
2
27 AFTP70 CAP_LED_R CAP_LED_R ACES-CON4-10-GP-U
28
29
20.K0320.004
30 1
AFTP72
2nd = 20.K0382.004
32
0927 0707 Modify:

JAE-CON30-7-GP
20.K0565.030 High Active from KBC GPIO.
CAP LED CONTROL AFTP73
1
1
TP_VDD
TPCLK
Change TPAD1 pin define to follow
TOUCH PAD DATASHEET.
0713 Modify:
5V_S5 AFTP74 TPDATA Change TPAD1 pin define to follow
2nd = 20.K0592.030 Q6902 1 TOUCH PAD DATASHEET.
AFTP75
R2
R6905 E
1 2 Q6902_B
B
X02 1116 CAP_LED_R
27 CAP_LED R1
CAP_LED_Q CAP_LED_R
C 1 2
15KR2J-1-GP R6906 1KR2J-1-GP
0915 X01 Modify: PDTA143ET-GP

un-stuff R6907 and stuff R6905,Q6902,R6906
for 5V drive CAP LED. 84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
1 2
R6907 DY100R2J-2-GP
CAP_LED:(Default HIGH actived)
B Connect to KB driving internal LED directly.(MAX 25mA) B
KB Backlight Connector
5V_S0 +5V_KB_BL
F6901
1 2
DY MAX 260mA
1
FUSE-D5A6V-2-GP C6905
SCD1U10V2KX-5GP
1 2 R6902
DN15
2
0R2J-2-GP
KBLIT1
DN15 5
1
R6904
1 2 KB_LED_DET_C 2
18 KB_LED_BL_DET DN15 3
DN15
1
0624 Modify: 51KR2J-1-GP 4

1
Change KB Backlight control all of related R6903 C6906

KB_BL_CTRL#
6
circuit component column to VOSTRO from DY.
SCD1U10V2KX-5GP
100KR2J-1-GP
0708 Modify: DN15 DY

2
R6904 change to 51K 0402 from 100ohm for ACES-CON4-34-GP

2
KB_LED_BL_DET to PCH GPIO.

updated KBLIT1 pin define base on KB DATA SHEET. 20.K0589.004
1
0901 X01 Modify:
2nd = 20.K0613.004
AFTP82 Change KBLIT1 to 20.K0320.004 from
D
20.K0218.004 base on ME updated X01 DXF&EMN.

A Re-assign KBLIT1 pin define sync with DQ15_NV. <Core Design> A
Q6901
P8503BMG-GP 0914 X01 Modify:
Add 2nd source 20.K0382.004 on KBLIT1
27 KB_BL_CTRL G
DN15 base on updated connector list.
0923 X01 Modify:
Wistron Corporation
1

84.P8503.031 Change KBLIT1 part number to 20.K0589.004
S
R6901 Taipei Hsien 221, Taiwan, R.O.C.

100KR2J-1-GP
2nd = 84.03404.C31 and re-assign pin define base on Roy updated.
+5V_KB_BL 1 Title
DN15 KB_LED_DET_C AFTP76
1
Key Board/Touch Pad
2
KB_BL_CTRL# 1 AFTP77
AFTP78 Size Document Number Rev
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
HALL1
NP1
0729
12
13 11
10 1
9 2 LID_CLOSE# 27
8 3
7 4 0804 swap
3D3V_S5
6 5
16 14
AFTP85
15
NP2
1
TCN-CONN10C-GP
AFTP83 AFTE14P-GP
AFTE14P-GP
1 3D3V_S5
1 LID_CLOSE# 20.F1655.010
C C
AFTP84 AFTE14P-GP
2nd = 20.F0962.010
1110 X02 Modify:

Add 2nd 20.F0962.010 on HALL1 from
ME updated connector list.
B B
<Core Design>
A A
Wistron Corporation
Title
Hall Sensor
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
3D3V_S0
DB1
11
1
21,27 LPC_AD0 2
21,27 LPC_AD1 3
21,27 LPC_AD2 4
21,27 LPC_AD3 5 DY
C 6 C
21,27 LPC_FRAME#
5,18,27,75,82,83 PLT_RST# 7
8
18 CLK_PCI_LPC 9
10
12
PAD-10P-177042-GP
ZZ.00PAD.Y41
A00 1229 DB1 change to ZZ.00PAD.Y41(solder kmask type)

and keep un-stuffat X-Build stage
B B
<Core Design>
A A
Wistron Corporation
Title
Dubug connector
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
SSID = SDIO
3D3V_CARD_S0 Close to CARD1
SC2D2U6D3V3MX-1-GP
SC10U6D3V5MX-3GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD01U16V2KX-3GP
D D
SD/XD/MS/MMC+ Card Reader

C7403
C7404
C7405
1
1
C7401
C7402
DY DY DY
2
2
0906 X01 Modify:
Change CARD1 to 20.I0129.001 from 62.10051.931
from ME double updated latest DXF&EMN on X01.
3D3V_CARD_S0
CARD1
P13 SD_VCC XD_CD 1 XD_CD# 32

XD_R/B 2 SP1 32
P22 MS_VCC XD_RE 3 SP2 32
XD_CE 4 SP3 32
18 XD_VCC XD_CLE 5 SP4 32
XD_ALE 6 SP5 32
XD_WE 7 SP6 32
32 SP4 P4 SD_DAT0 XD_WP_IN 8 SP7 32
32 SP3 P3 SD_DAT1
32 SP13 P25 SD_DAT2 XD_D0 10 SP8 32
32 SP12 P23 SD_DATA3 XD_D1 11 SP9 32
XD_D2 12 SP10 32
32 SP8 P10 SD_CLK XD_D3 13 SP11 32
32 SP6 P1 SD_CD XD_D4 14 SP12 32
32 SP1 P2 SD_WP XD_D5 15 SP13 32
32 SP10 P19 SD_CMD XD_D6 16 SP14 32
C 17 C
XD_D7 XD_D7 32
32 SP14 P9 MS_BS
32 SP2 P16 MS_INS SD_WP_COM/SDIO_GND P26
32 SP1 P20 MS_SCLK SD_CD_COM/SDIO_GND P27
SD_GND P7
32 SP9 P12 MS_DATA0 SD_GND P15
32 SP12 P11 MS_DATA1
32 SP8 P14 MS_DATA2 MS_GND P6
32 SP5 P18 MS_DATA3 MS_GND P24
XD_GND 9
32 SP11 P21 MMC_DATA4 XD_GND 19
32 SP9 P17 MMC_DATA5
32 SP7 P8 MMC_DATA6 NP1 NP1
32 SP5 P5 MMC_DATA7 NP2 NP2
CARD-PUSH-46P-1-GP-U
20.I0129.001 1119 X02 Modify:

Add 2nd 20.I0135.001 on HALL1 from
ME updated connector list.
2nd = 20.I0135.001
B B
For EMI Reserved

SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
SP13
SP14
XD_D7
XD_CD#
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
SC220P50V2KX-3GP
1
1
EC7402
EC7403
EC7404
EC7405
EC7406
EC7407
EC7408
EC7409
EC7410
EC7411
EC7412
EC7413
EC7414
EC7415
EC7416
EC7417
A
DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY <Core Design> A
2
2
Wistron Corporation
Title
SD/XD/MS/MMC Card CONN

A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
0824 X01 Modify:

Due to our NEW1 change to Express card to
bottom side so re-assign NEW1 pin define same
1D5V_S0_CARD Max. 650mA, Average 500mA. as DQ15-NV.
D D
3D3V_S0_CARD Max. 1300mA, Average 1000mA 0906 X01 Modify:
Add 2nd source 20.K0382.026 on NEW1 base on
3D3V_S5_CARDAUX Max. 275mA updated connector list.
SB-25
NEW 1
27
1
20 PCIE_TXP8 1 DN15 2
R7505 0R2J-2-GPPCIE_TXP8_CON 2
1 DN15 2 PCIE_TXN8_CON 3
20 PCIE_TXN8 R7506 0R2J-2-GP 4
1 DN15 2 PCIE_RXP8_CON 5
20 PCIE_RXP8
R7508
1 DN15 20R2J-2-GPPCIE_RXN8_CON 6
20 PCIE_RXN8
R7507 0R2J-2-GP 7
1122 X02 Modify: 1 DN15 2 CLK_PCIE_NEW _C 8
Change TR7501 CM choke to 69.10103.041 20 CLK_PCIE_NEW
20 CLK_PCIE_NEW # R7503
1 DN15 20R2J-2-GPCLK_PCIE_NEW #_C 9
and un-stuff R7501,R7502 from EMC Neo Suggestion. R7504 0R2J-2-GP 10
Change R7501,R7502 to 0603 from 0402.
20 CLK_PCIE_NEW _REQ# 1 DN15 2 CLK_PCIE_NEW _REQ#_CON 11
R7509 0R2J-2-GP 12
3D3V_S0 13 DN15
14
3D3V_S5 15
18 USB_PP13 USB_PP13_R 27,82 PCIE_W AKE# 1 DN15 2 PCIE_W AKE#_CON 16
R7510 0R2J-2-GP 17
69.10103.041 1D5V_S0
18
C
2nd = 69.10084.071 20 SMB_DATA SMB_DATA 19 C
FILTER-4P-6-GP 20 SMB_CLK SMB_CLK 20
19,27,46 PM_SLP_S4# PM_SLP_S4# 21
2 1 A00 1229 PM_SLP_S3# 22
19,27,36,37,47 PM_SLP_S3#
5,18,27,71,82,83 PLT_RST# PLT_RST# 23
3 DN15 4 USB_PP13_R 24
USB_PN13_R 25
TR7501 26
0913 X01 Modify:
Rename NEW1 pin24,25 to USB_PP13_R&USB_PN13_R. 28
Rename NEW1 pin8,9 to CLK_PCIE_NEW_C&CLK_PCIE_NEW#_C
ACES-CON26-6GP-U
USB_PN13_R
18 USB_PN13 20.K0320.026
2nd = 20.K0382.026
For EMI
AFTE14P-GP AFTP107 1 3D3V_S5
AFTE14P-GP AFTP108 1 3D3V_S0
AFTE14P-GP AFTP109 1 1D5V_S0 CLK_PCIE_NEW #_C PCIE_TXP8_CON CLK_PCIE_NEW _REQ#
AFTE14P-GP AFTP110 1 USB_PN13_R CLK_PCIE_NEW _C PCIE_TXN8_CON PCIE_W AKE#
AFTE14P-GP AFTP111 1 USB_PP13_R PCIE_RXP8
AFTE14P-GP AFTP112 1 CLK_PCIE_NEW _REQ#_CON PCIE_RXN8
2
AFTE14P-GP AFTP113 1 SMB_CLK
AFTE14P-GP AFTP114 1 SMB_DATA EC7501 EC7502 EC7507 EC7508
2
1 PM_SLP_S3#
AFTE14P-GP AFTP115 DY
1
DY DY DY
1
AFTE14P-GP AFTP116 1 PM_SLP_S4# SC4D7P50V2CN-1GP EC7505 EC7506 EC7503 EC7504 SC4D7P50V2CN-1GP
B PLT_RST# SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP B
1
AFTE14P-GP AFTP117 DY DY DY DY
1
AFTE14P-GP AFTP118 1 CLK_PCIE_NEW #_C SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP
AFTE14P-GP AFTP119 1 CLK_PCIE_NEW_C SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP
AFTE14P-GP AFTP120 1 PCIE_TXN8_CON
AFTE14P-GP AFTP121 1 PCIE_TXP8_CON
AFTE14P-GP AFTP122 1 PCIE_RXN8_CON
AFTE14P-GP AFTP123 1 PCIE_RXP8_CON
AFTE14P-GP 1 PCIE_W AKE#_CON 0913 X01 Modify:
AFTP124 Add R7503,R7504 and reserved EC7501,EC7502 on
CLK_PCIE_NEW &CLK_PCIE_NEW# for EMC suggestion.
0921 X01 Modify:
Add R7505~R7508 0ohm and reserved EC7503~EC7506
on PCIE_TX8&RX8 signal base on EMC Lance suggestion.
Add R7509,R7510 0ohm and reserved EC7507,EC7508
on CLK_PCIE_NEW_REQ#&PCIE_WAKE# signal base
on EMC Lance suggestion.
<Core Design>
A A
Wistron Corporation
Title
Express Card
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D
Free Fall Sensor D
Note
- no via, trace, under the sensor (keep out area around 2mm)
- stay away from the screw hole or metal shield soldering joints
3D3V_S0 - design PCB pad based on our sensor LGA pad size (add 0.1mm)
- solder stencil opening to 90% of the PCB pad size
- mount the sensor near the center of mass of the NB as possible as you can
1
C7901 DY DY C7902
SC10U6D3V5MX-3GP SCD1U10V2KX-4GP
2
3D3V_S0
1
U7901
1
R7902
14,15,20,82 PCH_SMBCLK 100KR2J-1-GP
DY
VDD_IO
VDD
14,15,20,82 PCH_SMBDATA
3D3V_S0
2
PCH_SMBCLK 14 8 HDD_FALL_INT1
SCL/SPC INT1 HDD_FALL_INT1 18
1
3D3V_S0 PCH_SMBDATA R7903
R7901
13 SDA/SDI/SDO INT2 9 DY 100KR2J-1-GP
C 1 DY 2 HDD_FALL_SDO 12 SDO
C
100KR2J-1-GP
2
7 FALL_INT2
CS
GND 2
GND 4
3 RESERVED#3 GND 5
11 RESERVED#11 GND 10
1
DY 3D3V_S0 Q7901 5V_S0
2N7002KDW -GP DY
84.2N702.A3F
1
DE351DLTR8-GP
6
2nd = 84.DM601.03F
09/0422 74.00351.0B3 DYR7904

100KR2J-1-GP
DY R7906
10KR2J-3-GP
(#1) Just pull +3.3V_RUN ~ Ref. Rothschild
2
0802
(#2) FAE/ DY is ok, chip internal pull-up resistors
0701 Modify: FFS_INT2_R
(#3) From spec, Slave ADdress(SAD) is 001110xb Change G-SENSOR U7901 back to DE351DLTR8. FFS_INT2 56
Pull HIGH SAD is 0011101b 0705 Modify: 0706 Modify:
Change DUMMY column to:MAIN source->ADI solution. R2220 and R7904 double PH. R7905
Pull GND SAD is 0011100b second source->ST solution. 1
DY 2
0R2J-2-GP
FFS_INT2_R 18
B B
Note
(1) Keep all signals are the same trace width. (included VDD, GND).
(2) No VIA under IC bottom.
A <Core Design> A
Wistron Corporation
Title
Free Fall Sensor

A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
IO Board CONN 80 pin

1112 X02 Modify:
Dell required us to disable PCIE port of WWAN slot
,If PCIE port 1 is disabled, it will cause all PCIE port 82
disabled,so change WWAN to PCIE port 3 from port1
at ST stage. NP1
2 1
/$1&/.
:/$186%
20 CLK_PCIE_W W AN_REQ#
18 USB_PP11
4
6
3
5
CLK_PCIE_LAN 20
CLK_PCIE_LAN# 20
18 USB_PN11 8 7 CLK_PCIE_W W AN 20
::$186% 20 PCIE_CLK_LAN_REQ#
18 USB_PP4
10
12
9
11
CLK_PCIE_W W AN# 20 ::$1&/.
18 USB_PN4 14 13 CLK_PCIE_W LAN 20
D
::$13&,( 20 PCIE_TXP3
16
18
15
17
CLK_PCIE_W LAN# 20
CLK_PCIE_USB3 20
:/$1&/. D
X02 1116 20 PCIE_TXN3 20 19 CLK_PCIE_USB3# 20 86%&/.

::$13&,( 20 PCIE_RXN3
22
24
21
23 3G_EN 22
20 PCIE_RXP3 26 25
/$13&,( 20 PCIE_TXN2
28
30
27
29 3D3V_S0
0916 X01 Modify:
20 PCIE_TXP2 32 31 Keep original X00 IOBD1 pin define.
0917 X01 Modify:
/$13&,( 20 PCIE_RXP2
34
36
33
35 1D5V_S0
Change IOBD1 part number to 20.F1849.080
base on Double updated latest DXF&EMN.
20 PCIE_RXN2 38 37 5V_S5 0920 X01 Modify:
40 39 Re-assign IOBD1 pin define due to updated
:/$13&,( 20
20
PCIE_RXN4
PCIE_RXP4
42
44
41
43
connector pin define is different as before.
Add R8206,R8207 to isolated AGND and DGND.
:/$13&,( 20 PCIE_TXP4
46
48
45
47
CLK_PCIE_W LAN_REQ# 20
E51_TXD 27
20 PCIE_TXN4 50 49 E51_RXD 27
86%3&,( 20 PCIE_RXN5
52
54
51
53
W IFI_RF_EN 27
W LAN_W W AN_LED# 63,68
20 PCIE_RXP5 56 55 PM_LAN_ENABLE 27
58 57 PLT_RST# 5,18,27,71,75,83
86%3&,( 60 59 PCIE_W AKE# 27,75 1122 X02 Modify:
20 PCIE_TXP5 stuff EC8201,EC8202 0.1u(closed H3)
20 PCIE_TXN5 62 61 BLUETOOTH_EN 27,63 between GND and GND from EMC Neo suggestion.
64 63 BT_ACT 63
A00 stuff EC8206 between 3D3V_S5 and GND from
3D3V_S5 66 65 1R8206 2 EMC Neo suggestion.
18 USB30_SMI# 68 67 0R0603-PAD-2-GP
AUD_HP1_JD# 29
63 W LAN_ACT 70 69 EXT_MIC_JD# 29
20 USB3_PEGB_CLKREQ# 72 71 MIC_IN_L 29
::$1:/$160%86
C
14,15,20,79 PCH_SMBDATA 74 73 3D3V_S5 C
MIC_IN_R 29
14,15,20,79 PCH_SMBCLK 76 75 AUD_HP1_JACK_L2 29
EC8201
SCD1U50V3KX-GP
EC8202
SCD1U50V3KX-GP
EC8206
SCD1U50V3KX-GP
27 USB3_PW R_ON 78 77 AUD_HP1_JACK_R2 29
1
A00 1229 80 79 A00 1R8207 2
NP2 0R0603-PAD-2-GP
81
2
IOBD1
X02 1122
ACES-CONN80D-1-GP AUD_AGND
0913 X01 Modify:
20.F1849.080 Change R8201~R8203 to 470ohm from 100ohm. 5V_S5
Add RN8209 PH 5V_S5 on MEDIA_LED1~3# for
2nd = 20.F1908.080 PWM OD mode. MEDIA_LED1# 1 2
MEDIA_LED2#R8204
1
DY 210KR2J-3-GP
AFTP8201 1 MEDIA1_1 MEDIA_LED3#R8205
1
DY 210KR2J-3-GP
AFTP8202 1 MEDIA1_2 R8208 DY 10KR2J-3-GP
AFTP8203 1 MEDIA1_3
86%3&,(
AFTP8204 1 5V_S5 1119 X02 Modify:
CRT Board Connector AFTP8205 1 INSTANT_ON# Reserved EC8203~EC8205 470p on all of
DATA_RECOVERY# MEDIA_LED# signal from EMC Neo suggestion.
86%3&,(
AFTP8206 1
0906 X01 Modify: AFTP8207 1 MEDIA_BTN3#
Add 2nd source 20.F0085.040 on CRTBD1 MEDIA_LED1# 1 2
base on updated connector list. MEDIA_LED2#EC82031 2SC470P50V-2-GP
0915 X01 Modify: MEDIA1 MEDIA_LED3#EC82041 2SC470P50V-2-GP
NP1
Re-assign CRTBD1 pin define base on CRTBD1 EC8205 SC470P50V-2-GP

42
EMC suggestion. 9
43 41 1 5V_S5
CRT_BLUE A00
B 5V_CRT_S0_R 2 1
MEDIA1_1 1 R8201 2
High active B
2 MEDIA_LED1# 27
3D3V_S0 4 3 3 MEDIA1_2 1KR2J-1-GP
1 4 MEDIA_LED2# 27
6 5 CRT_GREEN 4 MEDIA1_3 2 3 MEDIA_LED3# 27
CRT_HSYNC_CON 8 7 5 INSTANT_ON# 27
CRT_VSYNC_CON 10 9 CRT_RED 6 RN8201 DATA_RECOVERY# 27
12 11 7 SRN1KJ-7-GP MEDIA_BTN3# 27
14 13 8
16 15 20101220 R8202 R8203 for change to parallel resistor
18 17 10
AD+ 20 19 AD+
22 21
24 23 ACES-CON8-19-GP
26 25 1110 X02 Modify:
28 27
20.K0320.008 Add 2nd 20.K0465.008 on MEDIA1 from
30 29 CRT_DDC_CLK ME updated connector list.
27 PSID_EC
32 31 CRT_DDC_DATA 2nd = 20.K0465.008 1112 X02 Modify:
27 RCID change Media resistor from 430 ohm to 1K on
34 33 5V_S5 both DQ/DN15(R8201, R8202, R8203)
18 USB_PN1 36 35 3D3V_S5 for Media button LED light spot issue
18 USB_PP1 38 37 5V_USB2_S3
40 39 A00 1224
46 44 1123 X02 Modify: 5V_CRT_S0_R R8211 5V_CRT_S0 5V_S0
Removed R8211,R8212 and connect
5V_USB2_S3 to CRTBD1 pin 37 directly.
1 DY 2
0R3J-0-U-GP
D8201
45
NP2
1 2 2 1
ACES-CONN40D-GP 1120 X02 Modify:
Reserved R8211,R8212 0ohm 0805 on CRTBD1 F8201
0814
20.F1121.040 pin37,39 to separate EATA and CRT USB power in FUSE-1D1A6V-4GP-U CH551H-30PT-GP
ST build. 69.50007.691 2ND = 83.R5003.H8H
A 2nd = 20.F0085.040 <Core Design> A
A00 0103 add 3rd T-conn(20.F1932.040) at XBuild batch run

2nd = 69.50007.771 3rd = 83.5R003.08F
3rd = 20.F1932.040
0625 Modify: 83.R5003.C8F RN8205
Change CRTBD1 part number to 20.F0957.030
from 20.F1521.030 base on EMN updated part number.
0810 17 CRT_VSYNC 1 4 CRT_VSYNC_CON Wistron Corporation
2 3 CRT_HSYNC_CON 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
0720 Modify: 17 CRT_HSYNC Taipei Hsien 221, Taiwan, R.O.C.
CRT_DDC_DATA
Change CRTBD1 connector to 20.F1121.040 from 17 CRT_DDC_DATA
CRT_DDC_CLK SRN22-3-GP
30pin base on ME Double provide final solution. 17 CRT_DDC_CLK A00 1224 Title
0721 Modify: 1122 X02 Modify: 1120 X02 Modify:
re-assign CRTBD1 pin define to follow Joseph
release PIN define. 17 CRT_RED
CRT_RED Swap RN8205 pin4,3 and pin2,1 each other
base on Connie swap report.
Add RN8205
base on HSYNC&VSYNC report. Size
IO Board Connector
Document Number Rev
CRT_GREEN
17 CRT_GREEN
17 CRT_BLUE
CRT_BLUE A3 QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
Optiums Optimus OptimusOptimus

Optumus 150mA
1 2 1V_VGA_S0 1 L8301 2 VIO_PLLVDD
R8323 VGA2N 14 OF 16
1
SC10U6D3V3MX-GP
A00 0R0402-PAD-2-GP 0R0603-PAD-2-GP C8355 C8346 C8343 XTAL_PLL
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
VGA2A 1 OF 16 1V_VGA_S0 A00
PCI_EXPRESS Near BALLS 0818 Near BGA AE9
2
U8301 3D3V_S5 De-cap PLLVDD
AK16 AD9
PEX_IOVDD C8348 C8356 VID_PLLVDD
18 DGPU_HOLD_RST# 1 AK17 AF9
1
B PEX_IOVDD SP_PLLVDD
SC22U6D3V5MX-2GP
5 AK21 C8342 C8339 C8338 C8362
VCC PEX_IOVDD
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
SC10U6D3V3MX-GP
PLT_RST# DY C8347
5,18,27,71,75,82 PLT_RST# 2
A PEX_IOVDD
AK24 DY DY 0723
SCD1U10V2KX-5GP
4 PEX_RST# AK27
2
Y PEX_RST# 51,85,86 PEX_IOVDD
3
GND
Optimus
74LVC1G08GW-1-GP
1
73.01G08.L04 0927 AG11 0818 C8360S C8345S XTALSSIN D2 D1 XTALOUTBUFF
PEX_IOVDDQ De-cap XTAL_SSIN XTAL_OUTBUFF
AG12 DY
CD1U10V2KX-4GP
CD1U10V2KX-4GP
1
PEX_IOVDDQ
2nd = 73.7SZ08.DAH AG13
1
PEX_IOVDDQ R8319
D AG15 B1 B2 D
PEX_IOVDDQ XTAL_IN XTAL_OUT 10KR2J-3-GP
PEX_IOVDDQ
AG16 Optimus Optimus Optimus Optimus Optimus R8318
DY PEX_IOVDDQ
AG17 10KR2J-3-GP N12P-GE-A1-GP Optimus
R8314 1 2 100KR2J-1-GP AG18 1V_VGA_S0 Optimus
2
PEX_IOVDDQ
AG22
OPTIMUS
2
PEX_IOVDDQ
AG23
PEX_RST# PEX_IOVDDQ
AM16 AG24
1
PEX_RST# PEX_IOVDDQ C8326S C8334S C8321S C8349S C8350 R8302
SC4D7U6D3V3KX-GP
NV_PEG_CLKREQ# AR13 AG25 DY DY C8317 C8361 20 CLK_27M_VGA 1 2
CD1U10V2KX-5GP
CD1U10V2KX-5GP
CD1U10V2KX-5GP
C1U6D3V2KX-GP
PEX_CLKREQ# PEX_IOVDDQ
SC10U6D3V5KX-1GP
AG26
DY
2
PEX_IOVDDQ
SC4D7U6D3V3KX-GP
AJ14 XTALIN XTALOUT
PEX_IOVDDQ
PEX_IOVDDQ
AJ15
AJ19
X02 11/29 0R2J-2-GP
PEX_IOVDDQ C8354 SC15P50V2JN-2-GP
AJ21
PEX_IOVDDQ
PEX_IOVDDQ
AJ22 Optimus 2 1 Stuff PD on XTAL_SSIN and
AJ24 XTAL_OUTBUFF when EXT_SS is not
PEX_IOVDDQ
R8315 DY 200R2F-L-GP
PEX_IOVDDQ
AJ25 OptimusOptimus Optimus
1 2 PEXTSTCLK_OUT AJ17 AJ27 Optimus used.
2
PEXTSTCLK_OUT# PEX_TSTCLK_OUT PEX_IOVDDQ 0818
AJ18
PEX_TSTCLK_OUT# PEX_IOVDDQ
AK18 Optimus
AK20 De-cap R8321
1
PEX_IOVDDQ 0818
AR16 AK23
20 CLK_PCIE_VGA
20 CLK_PCIE_VGA# AR17
PEX_REFCLK PEX_IOVDDQ
AK26 0728 De-cap 82.30034.641 X8301
0R2J-2-GP
PEX_REFCLK# PEX_IOVDDQ
AL16 2nd = 82.30034.651 XTAL-27MHZ-85-GP
1MR2F-GP Optimus
1
4 PEG_RXP[0..15] PEG_RXP0 Optimus PEX_IOVDDQ R8320
1 2 C8337 SCD1U10V2KX-5GP PEG_C_RXP0 AL17 3rd = 82.30034.681 MUXLESS
4 PEG_RXN[0..15] PEG_RXN0 Optimus PEX_TX0
1 2 C8333 SCD1U10V2KX-5GP PEG_C_RXN0AM17
2
PEX_TX0#
2
4 PEG_TXP[0..15] PEG_TXP0 3D3V_VGA_S0 3D3V_VGA_S0
AP17
4 PEG_TXN[0..15] PEG_TXN0 PEX_RX0
AN17 Near BALLS
PEX_RX0#
0728 C8353 SC15P50V2JN-2-GP
1
PEG_RXP1 Optimus 1 2 C8336 SCD1U10V2KX-5GP PEG_C_RXP1AM18 AG19 2 1 XTALOUT_R R8324
PEG_RXN1 Optimus PEX_TX1 PEX_SVDD_3V3
1 2 C8335 SCD1U10V2KX-5GP PEG_C_RXN1AM19 F7 Optimus
PEX_TX1# NC#F7
10KR2J-3-GP
Optimus
1
PEG_TXP1 AN19 C8330S C8363S C8364
PEX_RX1
SC4D7U6D3V3KX-GP
PEG_TXN1 AP19 DY VGA2M 13 OF 16
CD1U10V2KX-5GP
C1U6D3V2KX-GP
2
PEX_RX1# MISC2
2
PEG_RXP2 Optimus 1 2 C8332 SCD1U10V2KX-5GP PEG_C_RXP2 AL19 A2 J26 C3 GPU_ROM_CS#
PEG_RXN2 Optimus PEX_TX2 NC#A2 NC#J26 ROM_CS#
1 2 C8328 SCD1U10V2KX-5GP PEG_C_RXN2 AK19 A7 J25
PEX_TX2# NC#A7 NC#J25 GPU_ROM_SI
AA4 D3
PEG_TXP2 NC#AA4 ROM_SI GPU_ROM_SO
AR19 AB4 C4
PEG_TXN2 PEX_RX2 NC#AB4 ROM_SO GPU_ROM_SCLK
AR20 AB7 D4
PEX_RX2# NC#AB7 ROM_SCLK
AC5
PEG_RXP3 Optimus NC#AC5
C 1 2 C8331 SCD1U10V2KX-5GP PEG_C_RXP3 AL20 AD6 Optimus C
PEG_RXN3 Optimus PEX_TX3 NC#AD6 3D3V_VGA_S0
1 2 C8327 SCD1U10V2KX-5GP PEG_C_RXN3AM20 AF6 Optimus
PEX_TX3# NC#AF6 3D3V_VGA_S0 STRAP0
AG6 W5
PEG_TXP3 NC#AG6 STRAP0 STRAP1
AP20 AJ5 W7
PEG_TXN3 PEX_RX3 NC#AJ5 STRAP1 STRAP2
AN20 AK15 V7
PEX_RX3# NC#AK15 STRAP2
AL7
1
PEG_RXP4 Optimus NC#AL7
1 2 C8329 SCD1U10V2KX-5GP PEG_C_RXP4AM21 B7
PEG_RXN4 Optimus PEX_TX4 NC#B7
1 2 C8325 SCD1U10V2KX-5GP PEG_C_RXN4AM22 C7 R8306
4
3
PEX_TX4# NC#C7 10KR2J-3-GP HDCP_CLK
D5 F6
PEG_TXP4 NC#D5 I2CH_SCL
AN22
PEX_RX4 NC#D6
D6 Optimus RN8301
PEG_TXN4 AP22 D7 G6 HDCP_SDA SRN4K7J-8-GP Optimus
2
PEX_RX4# NC#D7 I2CH_SDA
E5
PEG_RXP5 Optimus NC#E5
1 2 C8324 SCD1U10V2KX-5GP PEG_C_RXP5 AL22 E7 CEC AB5
PEG_RXN5 Optimus PEX_TX5 NC#E7 CEC
1 2 C8322 SCD1U10V2KX-5GP PEG_C_RXN5 AK22 F4 0723
1
2
PEX_TX5# NC#F4 HDCP_CLK
G5 A5
PEG_TXP5 NC#G5 NC#A5 HDCP_SDA
AR22 H32
PEG_TXN5 PEX_RX5 NC#H32
AR23 P6 A4
PEX_RX5# NC#P6 BUFRST#
U7 C5
PEG_RXP6 Optimus NC#U7 3D3V_VGA_S0 NC#C5
1 2 C8323 SCD1U10V2KX-5GP PEG_C_RXP6 AL23 V6 Near BALLS STRAP_3V3 N9
PEG_RXN6 Optimus PEX_TX6 NC#V6 MULTI_STRAP_REF0_GND
1 2 C8320 SCD1U10V2KX-5GP PEG_C_RXN6AM23 Y4 STRAP_MIOB M9
PEX_TX6# NC#Y4 MULTI_STRAP_REF1_GND
Optimus Optimus AK14
1
PEG_TXP6 GND
AP23
PEX_RX6 VDD33
J10 OPTIMUS GND
K9
PEG_TXN6 AN23 J11 R8303 R8304
1
PEX_RX6# VDD33 C8341S C8344S C8351S C8352S C8359 40K2R2F-GP 40K2R2F-GP N12P-GE-A1-GP
J12
VDD33
SC4D7U6D3V3KX-GP
PEG_RXP7 Optimus 2 C8319 SCD1U10V2KX-5GP PEG_C_RXP7AM24 Optimus Optimus
1 J13 DY
CD1U10V2KX-5GP
CD1U10V2KX-5GP
CD1U10V2KX-5GP
C1U6D3V2KX-GP
PEG_RXN7 Optimus PEX_TX7 VDD33
1 2 C8318 SCD1U10V2KX-5GP PEG_C_RXN7AM25 J9
2
PEX_TX7# VDD33
PEG_TXP7 AN25
PEG_TXN7 PEX_RX7
AP25
PEX_RX7# STRAPPING MODE TABLE
PEG_RXP8 Optimus 1 2 C8316 SCD1U10V2KX-5GP PEG_C_RXP8 AL25
PEG_RXN8 Optimus PEX_TX8
1 2 C8315 SCD1U10V2KX-5GP PEG_C_RXN8 AK25 PIN NAME MULTI-LEVEL BINARY PRODUCTION BINARY BRINGUP
PEX_TX8#
OptimusOptimus
PEG_TXP8 AR25
PEG_TXN8 PEX_RX8
AR26
PEX_RX8# MULTI_STRAP_REF1_GND 40.2K TO GND 40.2K TO GND NC
PEG_RXP9 Optimus 1 2 C8314 SCD1U10V2KX-5GP PEG_C_RXP9 AL26 D35 MULTI_STRAP_REF0_GND 40.2K TO GND NC NC
PEG_RXN9 Optimus PEX_TX9 VDD_SENSE#D35
1 2 C8313 SCD1U10V2KX-5GP PEG_C_RXN9AM26 P7 VGA_SENSE 92
PEX_TX9# VDD_SENSE#P7
AD20
PEG_TXP9 VDD_SENSE#AD20
AP26
PEX_RX9 GND_SENSE#AD19
AD19 GPU_ROM_SI
PEG_TXN9 AN26 R7 STRAP0
PEX_RX9# GND_SENSE#R7 GND_SENSE 92
B E35 for Hynix VRAM for Samsung VRAM for Hynix VRAM for Samsung VRAM B
PEG_RXP10Optimus GND_SENSE#E35
1 2 C8312 SCD1U10V2KX-5GP PEG_C_RXP10
AM27 USER[0]=1 Need check panel resolution (64Mx16) (0x2) (64Mx16) (0x3) (128Mx16) (0x6) (128Mx16) (0x7)
PEG_RXN10Optimus PEX_TX10
1 2 C8310 SCD1U10V2KX-5GP PEG_C_RXN10
AM28 USER[1]=1 1366x768 RAM_CFG[0]=0 RAM_CFG[0]=1 RAM_CFG[0]=0 RAM_CFG[0]=1
PEX_TX10#
PEG_TXP10
USER[2]=1 RAM_CFG[1]=1 RAM_CFG[1]=1 RAM_CFG[1]=1 RAM_CFG[1]=1
AN28
PEG_TXN10 PEX_RX10 USER[3]=1 RAM_CFG[2]=0 RAM_CFG[2]=0 RAM_CFG[2]=1 RAM_CFG[2]=1
AP28
PEX_RX10#
PEG_RXP11Optimus 1 2 C8311 SCD1U10V2KX-5GP PEG_C_RXP11AL28
120mA Optimus 1009 RAM_CFG[3]=0 RAM_CFG[3]=0 RAM_CFG[3]=0 RAM_CFG[3]=0
PEG_RXN11Optimus PEX_TX11 L8303 1V_VGA_S0
1 2 C8309 SCD1U10V2KX-5GP PEG_C_RXN11AK28
PEX_TX11# PEX_PLLVDD
PEX_PLLVDD
AG14 1 2 STRAP1 GPU_ROM_SO
PEG_TXP11 AR28
PEG_TXN11 PEX_RX11
AR29 EBMS160808A121-GP 3GIO_PADCFG[0]=0 VGA_DEVICE =1
1
PEX_RX11# C8340S C8357S C8358 68.00375.101 3GIO_PADCFG[1]=1 SMB_ALT_ADDR =0

SC4D7U6D3V3KX-GP
PEG_RXP12Optimus 1 2 C8308 SCD1U10V2KX-5GP PEG_C_RXP12AK29 Notebook configure.

CD1U10V2KX-5GP
C1U6D3V2KX-GP
PEG_RXN12Optimus PEX_TX12 3GIO_PADCFG[2]=1 FB_0_BAR_SIZE =0

1 2 C8306 SCD1U10V2KX-5GP PEG_C_RXN12AL29
2ND = 68.00119.101
2
PEX_TX12# 3GIO_PADCFG[3]=0 XCLK_417 =0

PEG_TXP12 AP29 Optimus
PEG_TXN12 PEX_RX12
AN29
PEX_RX12#
Optimus
PEG_RXP13Optimus 1 2 C8307 SCD1U10V2KX-5GP PEG_C_RXP13
AM29 STRAP2 N12P-GE N12P-GV1 N12M-GE N11P-GE N11P-GS GPU_ROM_SCLK
AM30 [0] 1 1 TBD 1 0
PEX_TX13#
Optimus PCI_DEVID[0]=0 PEX_PLL_EN_TERM =0
PEG_TXP13 AN31 [1] 0 1 0 0
PEX_RX13 PCI_DEVID[1]=0 SLOT_CLK_CFG =1
PEG_TXN13 AP31 [2] 1 1 0 0
PEX_RX13# Near BALLS Near BGA PCI_DEVID[2]=1
[3] 0 0 0 0
SUB_VENDOR =0 N12P-GE N12P-GV1 N12M-GE N11P-GE N11P-GS
PEG_RXP14Optimus PCI_DEVID[3]=0 PCI_DEVID[4] =1 [4] 1 1 TBD 1 1
1 2 C8304 SCD1U10V2KX-5GP PEG_C_RXP14
AM31
AM32
PEX_TX14#
PEG_TXP14 AR31 AG20
PEG_TXN14 PEX_RX14 NC#AG20 STRAP0 GPU_ROM_SI
AR32
PEX_RX14#
AG21 PEX_TERMP STRAP1 GPU_ROM_SO
PEG_RXP15Optimus PEX_TERMP
1 2 C8303 SCD1U10V2KX-5GP PEG_C_RXP15AN32 STRAP2 GPU_ROM_SCLK
1
1 2 C8301 SCD1U10V2KX-5GP PEG_C_RXN15AP32 Logical Strap Bit Mapping 0901
PEX_TX15# R8301 Resistor Pull-up Pull-down
PEG_TXP15 AR34 2K49R2F-GP 1 2 R8309 1 2 R8305
PEX_RX15 5Kohms 1000 0000 3D3V_VGA_S0
PEG_TXN15 AP34 AP35 PEX_TESTMODE Optimus DY 10KR2F-2-GP 30KR2F-GP 1 2 R8310 1 2 R8311
PEX_RX15# TESTMODE 10Kohms 1001 0001 3D3V_VGA_S0
OPTIMUS DIS_DID_L DIS_DID_H 15KR2F-GP DY 15KR2F-GP
2
1
15Kohms 1010 0010 1 2 R8326 1 2 R8308

N12P-GE-A1-GP R8313 20Kohms 1011 0011 DY 34K8R2F-1-GP Optimus 34K8R2F-1-GP 1 2 R8317 1 2 R8316
10KR2J-3-GP 25Kohms 1100 0100 DY 10KR2F-2-GP Optimus 10KR2F-2-GP
A
Optimus 30Kohms 1101 0101 1 2 R8307 1 2 R8325
A
Optimus 45K3R2F-L-GP DY 2KR2J-1-GP 1 2 R8327 1 2 R8312
2
35Kohms 1110 0110 DY 2KR2J-1-GP DIS_SAM_HYX 15KR2F-GP

DY 45Kohms 1111 0111
PQ8309 1 R8322 2 NV_PEG_CLKREQ#
2N7002K-2-GP
0R2J-2-GP
22,92,93 DGPU_PWROK G
DY <Variant Name>
D GPU_ROM_SI
PEG_CLKREQ# 20 STRAP 2: DIS_DID_L GPU_ROM_SCLK: DIS_DID_H Hynix 64x16 = PL 15K
Wistron Corporation
S 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
0xDF5 N12P-GE PH = NC, PL = 30K(64.30025.6DL) N12P-GE PH = 15K(64.15025.6DL), PL = NC Samsung 64x16 = PL 20K Taipei Hsien 221, Taiwan, R.O.C.
N12P-GV1 PH = NC, PL = 15K(64.15025.6DL) N12P-GV1 PH = 15K(64.15025.6DL), PL = NC
84.2N702.J31 N12M-GE PH = TBD, PL = TBD N12M-GE PH = TBD, PL = TBD Title
2ND = 84.2N702.031 N11P-GE-A1 PH = TBD, PL = 10K N11P-GE-A1 PH = 15K(64.15025.6DL), PL = NC N12P(1/6)_PEG
N11P-GS-A1 PH= NC, PL = 4.99K N11P-GS-A1 PH = 15K(64.15025.6DL), PL = NC Size Document Number Rev
0728 A2
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
VGA2B 2 OF 16
FBA VGA2C 3 OF 16
FBB
0818
De-cap 1D5V_VGA_S0 1D5V_VGA_S0
88 FBAD[0..31] 90 FBBD[0..31]
OptimusOptimusOptimus OptimusOptimus
FBAD0 L32 AA27 FBBD0 B13 N27
FBAD1 FBA_D0 FBVDDQ FBBD1 FBB_D0 FBVDDQ
N33 FBA_D1 FBVDDQ AA29 Near BALLS D13 FBB_D1 FBVDDQ P27
1
FBAD2 L33 AA31 C8425 C8424 C8423 C8422 C8421 C8420 FBBD2 A13 R27
FBA_D2 FBVDDQ FBB_D2 FBVDDQ
SCD01U50V2KX-1GP
SCD1U10V2KX-4GP
SCD01U50V2KX-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
FBAD3 N34 AB27 DY FBBD3 A14 T27
FBA_D3 FBVDDQ FBB_D3 FBVDDQ
SC1U6D3V2KX-GP
FBAD4 N35 AB29 FBBD4 C16 U27
2
P35 FBA_D5 FBVDDQ AC27 B16 FBB_D5 FBVDDQ U29
FBAD6 P33 AD27 FBBD6 A17 V27
D P34 FBA_D7 FBVDDQ AE27 D16 FBB_D7 FBVDDQ V29 D
FBAD8 K35 AJ28 FBBD8 C13 V34
K33 FBA_D9 FBVDDQ B18 B11 FBB_D9 FBVDDQ W27
FBAD10 K34 E21 FBBD10 C11 Y27
FBAD11 FBA_D10 FBVDDQ 0818 FBBD11 FBB_D10 FBVDDQ
H33 FBA_D11 FBVDDQ G17 A11 FBB_D11
FBAD12 G34 G18 De-cap FBBD12 C10
FBAD13 FBA_D12 FBVDDQ FBBD13 FBB_D12
G33 FBA_D13 FBVDDQ G22 Optimus Optimus Optimus Optimus C8 FBB_D13
FBAD14 E34 G8 C8426 FBBD14 B8
FBA_D14 FBVDDQ FBB_D14
1
SC1U6D3V2KX-GP
FBAD15 E33 G9 C8419 C8409 C8414 FBBD15 A8
FBA_D15 FBVDDQ FBB_D15
SCD1U10V2KX-5GP
SCD01U50V2KX-1GP
SCD1U10V2KX-4GP
FBAD16 G31 H29 FBBD16 E8
F30 J14 F8
2
G30 FBA_D18 FBVDDQ J15 F10 FBB_D18
FBAD19 G32 J16 FBBD19 F9
K30 J17 F12
K32 J20 D8
FBAD22 FBA_D21 FBVDDQ 0818 FBBD22 FBB_D21
H30 J21 D11
FBAD23 K31
FBA_D22
FBA_D23
FBVDDQ
FBVDDQ
J22 De-cap 0723 FBBD23 E11
FBB_D22
FBB_D23
FBAD24 L31 J23 FBBD24 D12 0810
L30 J24 E13
M32 J29 F13
N30 Near BGA F14
FBA_D27 FBB_D27
1
FBAD28 M30 C8410 C8411 FBBD28 F15 ODTx & CKEx & RST termination.
FBA_D28 FBB_D28
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
FBAD29 P31 DY Optimus FBBD29 E16
FBAD30 FBA_D29 FBBD30 FBB_D29 RN8402
R32 F16 Optimus
2
FBAD31 FBA_D30 FBBD31 FBB_D30 FBB_CMD_16
89 FBAD[32..63] R30 91 FBBD[32..63] F17 4 5
AG30 D29 3 6
AG32 F27 2 7
FBAD34 FBA_D33 0818 FBBD34 FBB_D33 FBB_CMD_0
AH31 F28 1 8
FBAD35 FBA_D34 De-cap FBBD35 FBB_D34
AF31 E28
FBAD36 FBA_D35 FBBD36 FBB_D35 SRN10KJ-6-GP
AF30 D26
FBAD37 FBA_D36 FBBD37 FBB_D36
AE30 F25
FBAD38 FBA_D37 FBBD38 FBB_D37 R8403
AC32 D24
AD30 E25 1 2
AN33 E32
FBAD41 FBA_D40 FBBD41 FBB_D40 10KR2J-3-GP
AL31 F32
AM33
FBA_D42
D33
FBB_D42 Optimus
FBAD43 AL33 Mode E is necessary for DDR3 FBBD43 E31
C AK30 that require compatibility C33 C
AK32 F29
FBAD46 FBA_D45 with previous generation FBBD46 FBB_D45
AJ30 D30
AH30
FBA_D47 GPUs (GB1-128) and only ODTx & CKEx & RST termination. E29
FBB_D47
FBAD48 AH33 FBBD48 B29
FBAD49 AH35
FBA_D48 applies to GB2-128 package. RN8401 Optimus FBBD49 C31
FBB_D48
FBAD50 FBA_D49 FBA_CMD_16 FBBD50 FBB_D49
AH34 4 5 C29
AH32 3 6 B31
AJ33 U30 FBA_CMD_0 88 2 7 C32 F18 FBB_CMD_0 90
FBAD53 FBA_D52 FBA_CMD0 FBA_CMD_0 FBBD53 FBB_D52 FBB_CMD0
AL35 V30 1 8 B32 E19
FBAD54 FBA_D53 FBA_CMD1 FBBD54 FBB_D53 FBB_CMD1
AM34 U31 FBA_CMD_2 88 B35 D18 FBB_CMD_2 90
FBAD55 FBA_D54 FBA_CMD2 0802 swap SRN10KJ-6-GP FBBD55 FBB_D54 FBB_CMD2
AM35 V32 FBA_CMD_3 88 B34 C17 FBB_CMD_3 90
AF33 T35 FBA_CMD_4 88,89 A29 F19 FBB_CMD_4 90,91
FBAD57 FBA_D56 FBA_CMD4 R8401 FBBD57 FBB_D56 FBB_CMD4
AE32 U33 FBA_CMD_5 88,89 B28 C19 FBB_CMD_5 90,91
FBAD58 FBA_D57 FBA_CMD5 FBA_CMD_20 FBBD58 FBB_D57 FBB_CMD5
AF34 W32 FBA_CMD_6 88,89 1 2 A28 B17 FBB_CMD_6 90,91
AE35 W33 FBA_CMD_7 88,89 C28 E20 FBB_CMD_7 90,91
FBAD60 FBA_D59 FBA_CMD7 10KR2J-3-GP FBBD60 FBB_D59 FBB_CMD7
AE34 W31 FBA_CMD_8 88,89 C26 B19 FBB_CMD_8 90,91
AE33
FBA_D61 FBA_CMD9
W34 FBA_CMD_9 88,89 Optimus D25
FBB_D61 FBB_CMD9
D20 FBB_CMD_9 90,91
FBAD62 AB32 U34 FBA_CMD_10 88,89 FBBD62 B25 A19 FBB_CMD_10 90,91
AC35 U35 FBA_CMD_11 88,89 A25 D19 FBB_CMD_11 90,91
FBA_D63 FBA_CMD11 FBB_D63 FBB_CMD11
U32 FBA_CMD_12 88 C20 FBB_CMD_12 90
FBA_CMD12 FBB_CMD12
T34 FBA_CMD_13 88,89 F20 FBB_CMD_13 90,91
FBA_CMD13 FBB_CMD13
P32 T33 FBA_CMD_14 89 A16 B20 FBB_CMD_14 91
88 FBADQM0 FBA_DQM0 FBA_CMD14 90 FBBDQM0 FBB_DQM0 FBB_CMD14
H34 W30 FBA_CMD_15 88,89 D10 G21 FBB_CMD_15 90,91
J30 AB30 FBA_CMD_16 89 F11 F22 FBB_CMD_16 91
P30 AA30 D15 F24
AF32 AB31 FBA_CMD_18 89 D27 F23 FBB_CMD_18 91
AL32 AA32 FBA_CMD_19 89 D34 C25 FBB_CMD_19 91
AL34 AB33 FBA_CMD_20 88,89 A34 C23 FBB_CMD_20 90,91
AF35 Y32 FBA_CMD_21 88,89 D28 F21 FBB_CMD_21 90,91
Y33 FBA_CMD_22 88,89 E22 FBB_CMD_22 90,91
FBA_CMD22 FBB_CMD22
AB34 FBA_CMD_23 88,89 D21 FBB_CMD_23 90,91
FBA_CMD23 FBB_CMD23
L34 AB35 FBA_CMD_24 88,89 C14 A23 FBB_CMD_24 90,91
88 FBADQSP0 FBA_DQS_WP0 FBA_CMD24 90 FBBDQSP0 FBB_DQS_WP0 FBB_CMD24
H35 Y35 FBA_CMD_25 88,89 A10 D22 FBB_CMD_25 90,91
J32 W35 FBA_CMD_26 88,89 E10 B23 FBB_CMD_26 90,91
N31 Y34 FBA_CMD_27 88 D14 C22 FBB_CMD_27 90
AE31 Y31 FBA_CMD_28 88,89 E26 B22 FBB_CMD_28 90,91
B AJ32 Y30 FBA_CMD_29 88,89 D32 A22 FBB_CMD_29 90,91 B
AJ34 W29 FBA_CMD_30 89 A32 A20 FBB_CMD_30 91
AC33 Y29 B26 G20
T32 FBA_CLK0 FBA_CLK0 88
FBA_CLK0 FBA_CLK0#
L35 T31 FBA_CLK0# 88 B14
88 FBADQSN0 FBA_DQS_RN0 FBA_CLK0# FBA_CLK1 90 FBBDQSN0 FBB_DQS_RN0
G35 AC31 FBA_CLK1 89 B10
88 FBADQSN1 FBA_DQS_RN1 FBA_CLK1 FBA_CLK1# 90 FBBDQSN1 FBB_DQS_RN1 FBB_CLK0
H31 AC30 FBA_CLK1# 89 D9 E17 FBB_CLK0 90
88 FBADQSN2 FBA_DQS_RN2 FBA_CLK1# 90 FBBDQSN2 FBB_DQS_RN2 FBB_CLK0 FBB_CLK0#
N32 E14 D17 FBB_CLK0# 90
88 FBADQSN3 FBA_DQS_RN3 90 FBBDQSN3 FBB_DQS_RN3 FBB_CLK0# FBB_CLK1
AD32 F26 D23 FBB_CLK1 91
89 FBADQSN4 FBA_DQS_RN4 91 FBBDQSN4 FBB_DQS_RN4 FBB_CLK1 FBB_CLK1#
AJ31 D31 E23 FBB_CLK1# 91
89 FBADQSN5 FBA_DQS_RN5 91 FBBDQSN5 FBB_DQS_RN5 FBB_CLK1#
AJ35 A31
89 FBADQSN6 FBA_DQS_RN6 91 FBBDQSN6 FBB_DQS_RN6
AC34 A26
89 FBADQSN7 FBA_DQS_RN7 91 FBBDQSN7 FBB_DQS_RN7
P29
FBA_WCK0
Differential write clocks R29
FBA_WCK0#
L29 T30 FBA_DEBUG0 1 TP8411 TPAD14-GP G14 G19 FBC_DEBUG0 1 TP8413 TPAD14-GP
for GDDR5 for Frame Buffers. M29
FBA_WCK1 FBA_DEBUG0
T29 FBA_DEBUG1 1 TP8412 TPAD14-GP G15
FBB_WCK0 FBB_DEBUG0
G16 FBC_DEBUG1 1 TP8414 TPAD14-GP
Reference for read and write FBA_WCK1# FBA_DEBUG1 FBB_WCK0# FBB_DEBUG1
AG29 G11
FBA_WCK2 FBB_WCK1
data. AH29
FBA_WCK2#
G12
FBB_WCK1#
AD29 G27
FBA_WCK3 FBB_WCK2
AE29 G28
FBA_WCK3# FBB_WCK2#
G24
FBB_WCK3
G25
1V_VGA_S0 FBB_WCK3#
L8401
Optimus Optimus Optimus Optimus
AG27 FB_PLLAVDD0 1 2
FB_DLLAVDD
AF27
FB_PLLAVDD C8417 C8412 C8413 A00
0R0603-PAD-2-GP
1
1
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
J19 1D5V_VGA_S0
2
FB_DLLAVDD
FB_PLLAVDD
J18 1009 K27 FBCAL_PD_VDDQ 1 2Optimus
FB_CAL_PD_VDDQ R8404 40D2R2F-GP
L27 FBCAL_PU_GND 1 2Optimus
TP8415 FB_VREF FB_CAL_PU_GND R8405 40D2R2F-GP
1 J27 NC#J27
A TPAD14-GP M27 FB_CAL_TERM_GND 1 2Optimus A
FB_CAL_TERM_GND R8402 60D4R2F-GP
1V_VGA_S0
L8402
N12P-GE-A1-GP Optimus Optimus Optimus Optimus N12P-GE-A1-GP
FB_PLLAVDD1 1 2 <Variant Name>
OPTIMUS C8418 C8415 C8416 A00 OPTIMUS
0R0603-PAD-2-GP
1
1
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
Wistron Corporation
2
Title
N12P(2/6)_MEMORY
GB1-128 do not need. Size Document Number Rev
Custom
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
3D3V_VGA_S0
If a DAC interface is not required, it should be disabled by: 10.28
1. Adding a pull-down to the DACx_VDD with a 10 kilohm resistor to GND.
2
2. All other DAC I/O pins can be left floating. VENTURA
R8514 R8515
2K2R2J-2-GP 2K2R2J-2-GP
4 OF 16 6 OF 16
VENTURA
VGA2D VGA2F VENTURA
1
DACA DACB
DACA_VDD AJ12 G1 NV_I2CA_SCL DACB_VDD AG7 G3 SMBC_INA219_C 1R8511 2 0R0402-PAD-2-GP
DACA_VDD I2CA_SCL DACB_VDD I2CB_SCL SMBC_INA219 43,92
G4 NV_I2CA_SDA G2 SMBD_INA219_C 1R8512 2 0R0402-PAD-2-GP SMBD_INA219 43,92
1
I2CA_SDA I2CB_SDA
Optimus R8503
AK12
DACA_VREF R8507
AK6
DACB_VREF A00
VENTURA
10KR2J-3-GP AK13 AM13 Optimus 10KR2J-3-GP AH7 AM1
DACA_RSET DACA_HSYNC 3D3V_VGA_S0 DACB_RSET DACB_HSYNC
AL13 AM2
DACA_VSYNC DACB_VSYNC
2
RN8501
AM15 NV_I2CA_SDA 1 4 AK4
DACA_RED NV_I2CA_SCL DACB_RED
2 3
D AM14 AL4 D
DACA_GREEN DACB_GREEN
SRN2K2J-1-GP
Ventura I2C must connect to I2CB_SCL & I2CB_SDA.
AL14 AJ4
DACA_BLUE DACB_BLUE
Optimus
In Optimus mode the GPU does not drive certain 0723
interfaces. These interfaces should be treated as NV suggest un-used I2C pull-up.
unused and appropriate terminations per the GPU design N12P-GE-A1-GP 0804 swap N12P-GE-A1-GP
guide should be applied th the signal or the power
supply block. OPTIMUS OPTIMUS
The following guidelines only apply to a fully unused IFP macro:

1. Pull down IFPxy_IOVDD with 10 kilohm resistor.
2. Pull down IFPxy_PLLVDD with 10 kilohm resistor.
3. The other IO pins can be NC; this includes unused data lines.
VGA2G 7 OF 16 VGA2I 9 OF 16
IFPAB IFPEF
AL8 AD4
IFPA_TXD0# IFPE_AUX_I2CY_SDA#
AM8 AE4
IFPA_TXD0 IFPE_AUX_I2CY_SCL
AM9 AE5
IFPA_TXD1# IFPEF_PLLVDD IFPEF_PLLVDD IFPE_L3#
AM10 AJ6 AE6
IFPA_TXD1 IFPEF_PLLVDD IFPE_L3
AL1 AF5
IFPAB_PLLVDD IFPAB_PLLVDD IFPEF_RSET IFPE_L2#
AK9 AL10 AF4
IFPAB_PLLVDD IFPA_TXD2# IFPE_L2
AK10
IFPA_TXD2 A00 IFPEF_IOVDD
AJ11 AG4
IFPAB_RSET IFPE_L1#
AH4
IFPAB_IOVDD IFPE_L1
AL11
4
3
IFPA_TXD3#
C AK11 AH5 C
IFPA_TXD3 RN8502 IFPE_L0#
AH6
IFPE_L0
Optimus SRN10KJ-5-GP
AM12
4
3
IFPA_TXC#
AM11 L1
RN8503 IFPA_TXC GPIO15
1
2
Optimus SRN10KJ-5-GP
A00 AP8
IFPB_TXD4# IFPEF_IOVDD
AN8 AE7 AF2
1
2
IFPB_TXD4 IFPE_IOVDD IFPF_AUX_I2CZ_SDA#

AF3
IFPF_AUX_I2CZ_SCL
IFPAB_IOVDD AG9 AN10 IFPEF_IOVDD AD7
IFPA_IOVDD IFPB_TXD5# 20101220 R8504 R8506 for change to parallel resistor IFPF_IOVDD
AP10 AH3
IFPAB_IOVDD IFPB_TXD5 IFPF_L3#
AG10 AH2
IFPB_IOVDD IFPF_L3
AR10 AH1
20101220 R8501 R8502 for change to parallel resistor IFPB_TXD6# IFPF_L2#
AR11 AJ1
IFPB_TXD6 IFPF_L2
AJ2
IFPF_L1#
AP11 AJ3
IFPB_TXD7# IFPF_L1
AN11
IFPB_TXD7
AL3
IFPF_L0#
AL2
IFPF_L0
AN13
IFPB_TXC#
AP13
IFPB_TXC
K6
GPIO21
N12P-GE-A1-GP
K1
OPTIMUS
GPIO0
N12P-GE-A1-GP
OPTIMUS
B B
VGA2H 8 OF 16 VGA2E 5 OF 16
3D3V_VGA_S0 220mA IFPC NEED CHECK PAGE 51. IFPD
A00 L8503
Optimus Optimus Optimus
1 2 IFPCD_PLLVDD AJ9 IFPCD_PLLVDD AC6
IFPC_PLLVDD IFPD_PLLVDD
1
Optimus 0R0603-PAD-2-GP C8508S C8507S C8506S C8516S IFPC_RSET AK7 IFPD_RSET AB6
IFPC_RSET IFPD_RSET
DY AN3 AN4
CD1U10V2KX-5GP
CD1U10V2KX-5GP
C1U6D3V2KX-GP
C4D7U6D3V3KX-GP
GPU_HDMI_DATA 51
1
1
IFPC_AUX_I2CW_SDA# IFPD_AUX_I2CX_SDA#
AP2 GPU_HDMI_CLK 51 AP4
2
R8509 IFPC_AUX_I2CW_SCL R8508 IFPD_AUX_I2CX_SCL

1KR2F-3-GP Optimus 1KR2F-3-GP
300ohm@100MHz ESR=0.25 Optimus IFPC_L3#

AR2 HDMI_CLK# 51 IFPD_L3#
AR4
AP1 HDMI_CLK 51 AR5
2
2
IFPC_L3 IFPD_L3
AM4 HDMI_DATA0# 51 AP5
IFPC_L2# IFPD_L2#
280mA IFPC_L2
AM3 HDMI_DATA0 51 IFPD_L2
AN5
1V_VGA_S0 AM5 AN7
L8502 IFPC_L1# HDMI_DATA1# 51 IFPD_L1#
A00 Optimus Optimus Optimus AL5 AP7
IFPC_L1 HDMI_DATA1 51 IFPD_L1
1 2 IFPCD_IOVDD AJ8 IFPCD_IOVDD AK8
IFPC_IOVDD IFPD_IOVDD
AM6 HDMI_DATA2# 51 AR7
1
IFPC_L0# IFPD_L0#
Optimus 0R0603-PAD-2-GP C8512S C8505S C8511S AM7 HDMI_DATA2 51 AR8
IFPC_L0 IFPD_L0
CD1U10V2KX-5GP
C1U6D3V2KX-GP
C4D7U6D3V3KX-GP
2
L7
GPIO19
K2 GPU_HDMI_HPD 51
GPIO1
220ohm@100MHz ESR=0.05
N12P-GE-A1-GP N12P-GE-A1-GP
OPTIMUS
If either IFPC or IFPD is used, then the whole IFPCD interface is OPTIMUS
1009
considered as being used. This is because IFPC and IFPD share one
macro design so one IO interface cannot be independently disabled.
A X02 1110 A
DY 0927
U8501 3D3V_S0
1 <Variant Name>
51 HDMI_HPD_DET B
5
U8501_2 VCC
93 9025_PGOOD_1V
2
DYR8510
1
0R2J-2-GP
2
A
4 GPU_HDMI_HPD
2 R8513
1 3
Y Wistron Corporation
2
51,83,86 PEX_RST# 0R2J-2-GP GND 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
DY0927 74LVC1G08GW-1-GP R8505 Taipei Hsien 221, Taiwan, R.O.C.
73.01G08.L04 DY 100KR2J-1-GP
Title
2ND = 73.7SZ08.DAH
N12P(3/6)_DAC
1
Optimus systems with HDMI connected to GPU.

(Option A). A2
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
RN8601
NV_OVERTEMP# 1 4 3D3V_VGA_S0
3D3V_VGA_S0 VGA2J 10 OF 16 NV_GPIO9 2 3
1
DY 2 MIOA_VDDQ P9 N1
NC#P9 NC#N1 SRN10KJ-5-GP
R9 NC#R9 NC#P4 P4
R8601 0R2J-2-GP T9 P1 0915 Optimus
NC#T9 NC#P1
1
C8602 U9 P2
NC#U9 NC#P2
SCD1U10V2KX-4GP
DY NC#P3 P3
D R8603 T3 D
2
NC#T3
10KR2J-3-GP NC#T2 T2
NC#T1 T1
Optimus U4
2
NC#U4 VGA2L 12 OF 16
NC#U1 U1
U2 MISC1
NC#U2 TPAD14-GP
U5 NC#U5 NC#U3 U3 1P2800_VGA_DXN B4 THERMDN I2CS_SCL E2 SMBC_THERM_NV
0728 Reserve for N12M. R6 TP8611 E1 SMBD_THERM_NV 3D3V_VGA_S0
NC#R6 I2CS_SDA RN8605
T5 NC#T5 NC#T6 T6
N6 E3 NV_LCD_EDID_CLK 4 1
NC#N6 A00 1231 add probe point I2CC_SCL NV_LCD_EDID_DAT
I2CC_SDA E4 3 2
N5 NC#N5 SRN2K2J-1-GP
TPAD14-GP 1P2800_VGA_DXP B5
TP8612 THERMDP Optimus
NC#P5 P5
NC#N3 N3 GPIO2 K3
NC#L3 L3 GPIO3 H3
NC#N2 N2 GPIO4 H2
H1 PW RCNTL_0 PW RCNTL_0 92
GPIO5 PW RCNTL_1
GPIO6 H4 PW RCNTL_1 92
H5 NV_GPIO7 1 TP8601 TPAD14-GP
GPIO7 NV_OVERTEMP#
NC#R4 R4 GPIO8 H6
T4 20 JTAG_TCK_VGA JTAG_TCK_VGA AP14 J7 NV_GPIO9 0915
NC#T4 MIOA_CLKIN_NC TPAD14-GP JTAG_TCK GPIO9
NC#N4 N4 1TP8608 NV_TMS AR14 JTAG_TMS GPIO10 K4
OPTIMUS TPAD14-GP 1TP8609 NV_TDI AN14 K5
TPAD14-GP JTAG_TDI GPIO11
C 1TP8610 NV_TDO AN16 JTAG_TDO GPIO12 H7 PW R_LEVEL C
N12P-GE-A1-GP JTAG_TRST# AP16 J4
JTAG_TRST# GPIO13
GPIO14 J6
2
1
MIOA_CLKIN_NC RN8602 L2
GPIO16
Optimus SRN10KJ-5-GP GPIO17 L4
MIOB_CLKIN_NC M4
3D3V_VGA_S0 VGA2K 11 OF 16 GPIO18
0728
L5
DY
3
4
MIOB_VDDQ GPIO20
1 2 AA9 NC#AA9 NC#Y1 Y1
2
1
AB9 NC#AB9 NC#Y2 Y2 GPIO22 L6
R8602 0R2J-2-GP W9 Y3 RN8606 M6 GPU_GPIO23 1 TP8606 TPAD14-GP
NC#W9 NC#Y3 GPIO23
1
C8601 Y9 AB3 SRN10KJ-5-GP M7

NC#Y9 NC#AB3 GPIO24
1
SCD1U10V2KX-4GP
DY NC#AB2 AB2 OPTIMUS

R8605 AB1 Optimus N12P-GE-A1-GP
2
10KR2J-3-GP NC#AB1
AC4
3
4
NC#AC4
Optimus NC#AC1 AC1
AC2 MIOx_CLKIN signals should
2
NC#AC2
AC3
NC#AC3
NC#AE3 AE3
have 10K pull-down 3D3V_VGA_S0 GPIO12
0728 Reserve for N12M. AA7 AE2 resistors.
NC#AA7 NC#AE2
NC#U6 U6 1 - > AC mode.
1
AA6 W6
NC#AA6 NC#W6
NC#Y6 Y6 R8604 0 -> Battery mode.
10KR2J-3-GP
AF1 Optimus D8601
2
NC#AF1 PW R_LEVEL 1
B B
3 AC_PRESENT 19,27
3D3V_VGA_S0 BAS16-6-GP
0723 2
NC#W3 W3
NC#W1 W1 83.00016.K11
NC#W2 W2 2ND = 83.00016.F11
3
4
NC#Y5 Y5
RN8603
SRN2K2J-1-GP
Optimus
NC#V4 V4 Q8601
W4 Optimus
2
1
NC#W4
NC#AE1 AE1 MIOB_CLKIN_NC SMBC_THERM_NV 1 6 SML1_CLK 20,27
OPTIMUS
2 5
N12P-GE-A1-GP
SML1_DATA 20,27
3 4
SMBD_THERM_NV
2N7002KDW -GP
2ND = 84.2N702.031 84.2N702.A3F
2nd = 84.DM601.03F
84.2N702.J31
MIOA/B Support 2N7002K-2-GP
R8606 DY
G Q8602_G 2 1 PEX_RST# 51,83,85
A <Variant Name> A
1
Package MIOA MIOB D C8603

27,28,36 PURE_HW _SHUTDOW N# 0R2J-2-GP
DY
S SCD1U10V2KX-4GP
Wistron Corporation
2
GB1-192 15-bit, available TBD DY

Q8602 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
GB2-128 Not available Not available 0915 Title
NV_OVERTEMP#
N12P(5/6)_MIO/ GPIO
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
VGA2O 15 OF 16
GND VGA_CORE VGA2P 16 OF 16 VGA_CORE
AA11 E15 NVVDD
GND GND VGA_CORE
AA12
AA13
GND
GND
GND
GND
E18
E24
AB11
AB13
VDD
VDD
VDD
VDD
P21
P23 OptimusOptimus Under GPU VGA_CORE Near GPU
AA14 E27 AB15 P25 0818
GND GND VDD VDD De-cap
AA15 GND GND E30 AB17 VDD VDD R11
1
AA16 E6 AB19 R12 C8704 C8716
GND GND VDD VDD
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
AA17 E9 AB21 R13 C8722
GND GND VDD VDD
1
AA18 F2 AB23 R14
2
GND GND VDD VDD
SC10U6D3V3MX-GP
AA19 F31 AB25 R15 C8723
GND GND VDD VDD
SC4D7U6D3V3KX-GP
D AA2 F34 AC11 R16 D
2
GND GND VDD VDD
AA20 GND GND F5 AC12 VDD VDD R17
AA21 GND GND J2 AC13 VDD VDD R18
AA25 L9 AC17 R22 Optimus Optimus Optimus OptimusOptimusOptimus
GND GND VDD VDD
AA34 GND GND M11 AC18 VDD VDD R23
1
AA5 M13 AC19 R24 C8708 C8705 C8709 C8715 C8719 C8714 C8720 C8721 DY Optimus
GND GND VDD VDD
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
AB12 GND GND M15 AC20 VDD VDD R25 DY DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
AB14 M17 AC21 T12
2
GND GND VDD VDD
AB16 GND GND M19 AC22 VDD VDD T14
AB18 M2 AC23 T16 C8724 C8725
GND GND VDD VDD
1
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
AB24 M25 AD12 T22
2
GND GND VDD VDD
AC9 GND GND M31 AD14 VDD VDD T24
AD11 GND GND M34 AD16 VDD VDD V11
AD13 GND GND M5 AD18 VDD VDD V13 OptimusOptimusOptimus
AD15 GND GND N11 AD22 VDD VDD V15
1
AD17 N12 AD24 V17 C8711 C8717 C8712
GND GND VDD VDD
AD2 GND GND N13 L11 VDD VDD V19
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
AD21 N14 L12 V21
2
GND GND VDD VDD
AD23 GND GND N15 L13 VDD VDD V23 OptimusOptimus
AD25 GND GND N16 L14 VDD VDD V25
AD31 GND GND N17 L15 VDD VDD W11
1
AE11 N20 L18 W14 C8710
GND GND VDD VDD
SC4D7U10V3KX-GP
C AE12 N21 L19 W15 Optimus C
GND GND VDD VDD
AE13 N22 L20 W16 Optimus Optimus
2
GND GND VDD VDD
AE14 GND GND N23 L21 VDD VDD W17
1
AE15 N24 L22 W18 C8703 C8706
GND GND VDD VDD C8707
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
AE16 GND GND N25 L23 VDD VDD W19 DY
SCD047U25V2KX-GP
AE17 P12 L24 W20
2
GND GND VDD VDD
AE18 GND GND P14 L25 VDD VDD W21
AE19 GND GND P16 M12 VDD VDD W22
AE23 GND GND P24 M20 VDD VDD Y12 0728
AE24 GND GND R2 M22 VDD VDD Y14
AE25 GND GND R31 M24 VDD VDD Y16 Optimus Optimus
AG2 GND GND R34 P11 VDD VDD Y18 0818
1
AG31 R5 P13 Y20 C8718 C8701 C8702
GND GND VDD VDD De-cap
SCD1U10V2KX-5GP
SCD1U10V2KX-4GP
AG34 GND GND T11 P15 VDD VDD Y22 DY
SCD1U10V2KX-5GP
AG5 T13 P17 Y24
2
GND GND VDD VDD
AK2 GND GND T15 P19 VDD
AK31 GND GND T17
AK34 T19 N12P-GE-A1-GP
GND GND
AK5 GND GND T21
AL12 T23
AL15
GND GND
T25
OPTIMUS
GND GND
AL18 GND GND U11
AL21 GND GND U12 Optimus
AL24 GND GND U13
1
AL27 U14 C8713
GND GND
AL30 GND GND U15
SCD1U10V2KX-5GP
B B
AL6 U16
2
GND GND
AL9 GND GND U17
AN2 GND GND U18
AN34 GND GND U19
AP12 GND GND U20
AP15 GND GND U21 0728
AP18 GND GND U22
AP21 GND GND U23
AP24 GND GND U24
AP27 GND GND U25
AP3 GND GND V12
AP30 GND GND V14
AP33 GND GND V16
AP6 GND GND V18
AP9 GND GND V2
B12 GND GND V20
B15 GND GND V22
B21 GND GND V24
B24 GND GND V31
B27 GND GND V5
B3 GND GND V9
B30 GND GND Y11
B33 GND GND Y13
B6 GND GND Y15
B9 GND GND Y17
C2 GND GND Y19
C34 GND GND Y21
E12 GND GND Y23
A GND Y25 <Variant Name> A
N12P-GE-A1-GP
OPTIMUS
Wistron Corporation
Title
N12P(6/6)_POWER
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
Frame Buffer Patition A Lower 32 bits.

1D5V_VGA_S0 FBRAM1 FBRAM2
FBAD[0..31] 84 1D5V_VGA_S0 FBAD[0..31] 84
K8 E3 FBAD22 K8 E3 FBAD26
VDD DQL0 FBAD18 VDD DQL0 FBAD29
K2 VDD DQL1 F7 K2 VDD DQL1 F7
N1 F2 FBAD23 N1 F2 FBAD24
R9 VDD DQL3 F8 R9 VDD DQL3 F8
D B2 H3 FBAD21 B2 H3 FBAD25 D
D9 VDD DQL5 H8 D9 VDD DQL5 H8
G7 G2 FBAD20 G7 G2 FBAD28
R1 VDD DQL7 H7 R1 VDD DQL7 H7
1D5V_VGA_S0 N9 1D5V_VGA_S0 N9
VDD FBAD13 VDD FBAD4 1D5V_VGA_S0
DQU0 D7 DQU0 D7
A8 C3 FBAD11 A8 C3 FBAD3
VDDQ DQU1 FBAD14 VDDQ DQU1 FBAD7
A1 VDDQ DQU2 C8 A1 VDDQ DQU2 C8 OptimusOptimus OptimusOptimusOptimusOptimusOptimusOptimusOptimus
C1 C2 FBAD8 C1 C2 FBAD0
VDDQ DQU3 VDDQ DQU3
1
C9 A7 FBAD12 C9 A7 FBAD5 C8802 C8803 C8804 C8805 C8806 C8807 C8808 C8809 C8810 C8811
VDDQ DQU4 VDDQ DQU4
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
FBAD10 0730 swap pin FBAD2
D2 VDDQ DQU5 A2
FBAD15
D2 VDDQ DQU5 A2
FBAD6
DY
E9 B8 E9 B8
2
F1 VDDQ DQU7 A3 F1 VDDQ DQU7 A3
H9 VDDQ H9 VDDQ
C8801 Optimus H2 C7 FBADQSP1 84 H2 C7 FBADQSP0 84
SCD01U50V2KX-1GP VDDQ DQSU VDDQ DQSU
DQSU# B7 FBADQSN1 84 DQSU# B7 FBADQSN0 84
Optimus 2 1 FBA_VREF12 H1 VREFDQ
FBA_VREF12 H1 VREFDQ
R8804 M8 F3 FBADQSP2 84 Optimus M8 F3 FBADQSP3 84
FBA_ZQ0 VREFCA DQSL R8803 2 VREFCA DQSL
2 1 L8 ZQ DQSL# G3 FBADQSN2 84 1FBA_ZQ1 L8 ZQ DQSL# G3 FBADQSN3 84
243R2F-2-GP OptimusOptimusOptimusOptimusOptimusOptimusOptimusOptimusOptimus
243R2F-2-GP K1 FBA_CMD_0 FBA_CMD_0 84 K1 FBA_CMD_0 FBA_CMD_0 84
ODT ODT
1
84,89 FBA_CMD_7 FBA_CMD_7 N3 84,89 FBA_CMD_7 FBA_CMD_7 N3 C8812 C8813 C8814 C8815 C8816 C8817 C8818 C8819 C8820 C8822
A0 A0
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
84,89 FBA_CMD_10 FBA_CMD_10 P7 84,89 FBA_CMD_10 FBA_CMD_10 P7 DY
A1 A1
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SC1U6D3V2KX-GP
84,89 FBA_CMD_24 FBA_CMD_24 P3 L2 FBA_CMD_2 FBA_CMD_2 84 84,89 FBA_CMD_24 FBA_CMD_24 P3 L2 FBA_CMD_2 FBA_CMD_2 84
2
FBA_CMD_6 A2 CS# FBA_CMD_20 FBA_CMD_6 A2 CS# FBA_CMD_20
84,89 FBA_CMD_6 N2 A3 RESET# T2 FBA_CMD_20 84,89 84,89 FBA_CMD_6 N2 A3 RESET# T2 FBA_CMD_20 84,89
84,89 FBA_CMD_22 FBA_CMD_22 P8 84,89 FBA_CMD_22 FBA_CMD_22 P8
FBA_CMD_26 A4 FBA_CMD_26 A4
84,89 FBA_CMD_26 P2 A5 84,89 FBA_CMD_26 P2 A5
84,89 FBA_CMD_5 FBA_CMD_5 R8 T7 84,89 FBA_CMD_5 FBA_CMD_5 R8 T7
FBA_CMD_21 A6 NC#T7 0729 FBA_CMD_21 A6 NC#T7 0729
84,89 FBA_CMD_21 R2 A7 NC#L9 L9 84,89 FBA_CMD_21 R2 A7 NC#L9 L9
C FBA_CMD_8 T8 L1 FBA_CMD_8 T8 L1 0818 C
84,89 FBA_CMD_8 A8 NC#L1 84,89 FBA_CMD_8 A8 NC#L1 De-cap
FBA_CMD_4 R3 J9 FBA_CMD_4 R3 J9 0818 0818
84,89 FBA_CMD_4 A9 NC#J9 84,89 FBA_CMD_4 A9 NC#J9 De-cap De-cap
84,89 FBA_CMD_25 FBA_CMD_25 L7 J1 84,89 FBA_CMD_25 FBA_CMD_25 L7 J1
FBA_CMD_23 A10/AP NC#J1 FBA_CMD_23 A10/AP NC#J1
84,89 FBA_CMD_23 R7 A11 84,89 FBA_CMD_23 R7 A11 Optimus Optimus OptimusOptimus OptimusOptimus
84,89 FBA_CMD_9 FBA_CMD_9 N7 84,89 FBA_CMD_9 FBA_CMD_9 N7
A12/BC# A12/BC#
1
84 FBA_CMD_12 FBA_CMD_12 T3 J8 84 FBA_CMD_12 FBA_CMD_12 T3 J8 C8821 C8829 C8823 C8824 C8825 C8826 C8827 C8828 C8840 C8830
A13 VSS A13 VSS
SC4D7U6D3V3KX-GP
SCD01U50V2KX-1GP
SCD1U10V2KX-4GP
SCD01U16V2KX-3GP
M7 NC#M7 VSS M1 M7 NC#M7 VSS M1 DY DY DY DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
0729 M9 0729 M9
2
VSS VSS
VSS J2 VSS J2
84,89 FBA_CMD_29 FBA_CMD_29 M2 P9 84,89 FBA_CMD_29 FBA_CMD_29 M2 P9
FBA_CMD_13 BA0 VSS FBA_CMD_13 BA0 VSS
84,89 FBA_CMD_13 N8 BA1 VSS G8 84,89 FBA_CMD_13 N8 BA1 VSS G8
84 FBA_CMD_27 FBA_CMD_27 M3 B3 84 FBA_CMD_27 FBA_CMD_27 M3 B3
160R3F-1-GP BA2 VSS BA2 VSS 0818 0818
VSS T1 VSS T1
OptimusR8807 1 2 A9 A9 De-cap De-cap
VSS VSS
84 FBA_CLK0 J7 CK VSS T9 84 FBA_CLK0 J7 CK VSS T9
84 FBA_CLK0# K7 CK# VSS E1 84 FBA_CLK0# K7 CK# VSS E1
VSS P1 VSS P1 OptimusOptimusOptimusOptimusOptimusOptimusOptimusOptimus
84 FBA_CMD_3 FBA_CMD_3 K9 84 FBA_CMD_3 FBA_CMD_3 K9
CKE CKE
1
G1 G1 C8831 C8832 C8833 C8834 C8835 C8836 C8837 C8838
VSSQ VSSQ
SC10U6D3V3MX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC10U6D3V3MX-GP
VSSQ F9 VSSQ F9
84 FBADQM1 D3 E8 84 FBADQM0 D3 E8
2
DMU VSSQ DMU VSSQ
84 FBADQM2 E7 DML VSSQ E2 84 FBADQM3 E7 DML VSSQ E2
VSSQ D8 VSSQ D8
VSSQ D1 VSSQ D1
84,89 FBA_CMD_28 FBA_CMD_28 L3 B9 84,89 FBA_CMD_28 FBA_CMD_28 L3 B9
FBA_CMD_15 WE# VSSQ FBA_CMD_15 WE# VSSQ
84,89 FBA_CMD_15 K3 CAS# VSSQ B1 84,89 FBA_CMD_15 K3 CAS# VSSQ B1
84,89 FBA_CMD_11 FBA_CMD_11 J3 G9 84,89 FBA_CMD_11 FBA_CMD_11 J3 G9
RAS# VSSQ RAS# VSSQ
Optimus Optimus 0818 0818
B H5TQ2G63BFR-11C-GP H5TQ2G63BFR-11C-GP De-cap De-cap B
72.52G63.A0U 72.52G63.A0U
2nd = 72.41164.I0U 2nd = 72.41164.I0U
PCB Footprint = BGA96D0913H48 PCB Footprint = BGA96D0913H48
1112 X02 Modify: 1112 X02 Modify:
All of VRAM PCB footprint change to CO-LAY type All of VRAM PCB footprint change to CO-LAY type
(DUMMY-BGA96D075133H48) from BGA96D0913H48 (DUMMY-BGA96D075133H48) from BGA96D0913H48
GB1-128 Mode C GB2-128 DRAM Function Modified in SB

Single Rank Mode E
1D5V_VGA_S0
0..31 32..63
1D5V_VGA_S0 1D5V_VGA_S0
CMD25 CMD0 ODT
CMD23 CMD1 CS1*
1
CMD2 CMD2 CS0*

CMD0 CMD3 CKE R8801
1
CMD10 CMD4 A9 A11 1K05R2F-GP
CMD26 CMD5 A6 A7 Optimus
CMD14 CMD6 A3 BA1 TC8802 TC8801
CMD7 CMD7 A0 A12 ST100U6D3VBM-16GP ST100U6D3VBM-16GP
2
2
CMD1 CMD8 A8 A8 FBA_VREF12 DY DY
CMD22 CMD9 A12 A0
1
CMD20 CMD10 A1 A2
CMD24 CMD11 RAS* RAS* Optimus
CMD18 CMD12 A13 A14 R8802 C8839
CMD9 CMD13 BA1 A3
Optimus 1K05R2F-GP SCD01U50V2KX-1GP
2
CMD29 CMD14 A14 A13

CMD8 CMD15 CAS* CAS*
CMD27 CMD16 CKE
2
CMD15 CMD17 CS1*

A <Variant Name> A
CMD11 CMD18 CS0*
CMD16 CMD19 ODT
CMD28 CMD20 RST RST
CMD3
CMD17
CMD21
CMD22
A7
A4
A6
A5 Wistron Corporation
CMD5 CMD23 A11 A9 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
CMD4 CMD24 A2 A1
CMD21 CMD25 A10 WE*
CMD6 CMD26 A5 A4
CMD13 CMD27 BA2 A15 Title
CMD19 CMD28 WE* A10
CMD12
CMD30
CMD29
CMD30
BA0
A15
BA0
BA2
VRAM(1/4)
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
Frame Buffer Patition A Upper 32 bits.

FBRAM4
1D5V_VGA_S0 FBAD[32..63] 84
FBRAM3
1D5V_VGA_S0 FBAD[32..63] 84
K8 E3 FBAD43
FBAD33 VDD DQL0 FBAD45
K8 VDD DQL0 E3 K2 VDD DQL1 F7
K2 F7 FBAD35 N1 F2 FBAD46
N1 VDD DQL2 F2 R9 VDD DQL3 F8
D R9 F8 FBAD39 B2 H3 FBAD44 D
B2 VDD DQL4 H3 D9 VDD DQL5 H8
D9 H8 FBAD37 G7 G2 FBAD47
G7 VDD DQL6 G2 R1 VDD DQL7 H7
R1 H7 FBAD38 1D5V_VGA_S0 N9
1D5V_VGA_S0 N9 VDD DQL7 VDD FBAD56
VDD DQU0 D7
D7 FBAD48 A8 C3 FBAD63
DQU0 FBAD52 VDDQ DQU1 FBAD57
A8 VDDQ DQU1 C3 A1 VDDQ DQU2 C8
A1 C8 FBAD50 C1 C2 FBAD62
C1 VDDQ DQU3 C2 C9 VDDQ DQU4 A7
C9 A7 FBAD51 D2 A2 FBAD59 0730 swap pin
VDDQ DQU4 FBAD54 0730 swap pin VDDQ DQU5 FBAD61
D2 VDDQ DQU5 A2 E9 VDDQ DQU6 B8
E9 B8 FBAD49 0802 swap pin F1 A3 FBAD60
VDDQ DQU6 FBAD53 VDDQ DQU7
F1 VDDQ DQU7 A3 H9 VDDQ
H9 VDDQ H2 VDDQ DQSU C7 FBADQSP7 84
Optimus H2 C7 B7 0730 swap pin
VDDQ DQSU FBADQSP6 84 DQSU# FBADQSN7 84
C8901 B7 0730 swap pin FBA_VREF34 H1
DQSU# FBADQSN6 84 VREFDQ
2 1 FBA_VREF34 H1 VREFDQ M8 VREFCA DQSL F3 FBADQSP5 84
SCD01U50V2KX-1GP M8 F3 FBADQSP4 84 2 R8905 1FBA_ZQ3 L8 G3 FBADQSN5 84
R8903 VREFCA DQSL ZQ DQSL#
2 1FBA_ZQ2 L8 ZQ DQSL# G3 FBADQSN4 84 243R2F-2-GP
Optimus Optimus K1 FBA_CMD_19 FBA_CMD_19 84
243R2F-2-GP FBA_CMD_19 FBA_CMD_9 ODT
ODT K1 FBA_CMD_19 84 84,88 FBA_CMD_9 N3 A0
84,88 FBA_CMD_9 FBA_CMD_9 N3 84,88 FBA_CMD_24 FBA_CMD_24 P7
FBA_CMD_24 A0 FBA_CMD_10 A1 FBA_CMD_18
84,88 FBA_CMD_24 P7 A1 84,88 FBA_CMD_10 P3 A2 CS# L2 FBA_CMD_18 84
84,88 FBA_CMD_10 FBA_CMD_10 P3 L2 FBA_CMD_18 FBA_CMD_18 84 84,88 FBA_CMD_13 FBA_CMD_13 N2 T2 FBA_CMD_20 FBA_CMD_20 84,88
FBA_CMD_13 A2 CS# FBA_CMD_20 FBA_CMD_26 A3 RESET#
84,88 FBA_CMD_13 N2 A3 RESET# T2 FBA_CMD_20 84,88 84,88 FBA_CMD_26 P8 A4
84,88 FBA_CMD_26 FBA_CMD_26 P8 84,88 FBA_CMD_22 FBA_CMD_22 P2
FBA_CMD_22 A4 FBA_CMD_21 A5
84,88 FBA_CMD_22 P2 A5 84,88 FBA_CMD_21 R8 A6 NC#T7 T7
FBA_CMD_21 R8 T7 FBA_CMD_5 R2 L9 0729
84,88 FBA_CMD_21 A6 NC#T7 84,88 FBA_CMD_5 A7 NC#L9
C FBA_CMD_5 R2 L9 0729 FBA_CMD_8 T8 L1 C
84,88 FBA_CMD_5 A7 NC#L9 84,88 FBA_CMD_8 A8 NC#L1
84,88 FBA_CMD_8 FBA_CMD_8 T8 L1 84,88 FBA_CMD_23 FBA_CMD_23 R3 J9
FBA_CMD_23 A8 NC#L1 FBA_CMD_28 A9 NC#J9
84,88 FBA_CMD_23 R3 A9 NC#J9 J9 84,88 FBA_CMD_28 L7 A10/AP NC#J1 J1
84,88 FBA_CMD_28 FBA_CMD_28 L7 J1 84,88 FBA_CMD_4 FBA_CMD_4 R7
FBA_CMD_4 A10/AP NC#J1 FBA_CMD_7 A11
84,88 FBA_CMD_4 R7 A11 84,88 FBA_CMD_7 N7 A12/BC#
84,88 FBA_CMD_7 FBA_CMD_7 N7 84 FBA_CMD_14 FBA_CMD_14 T3 J8
FBA_CMD_14 A12/BC# A13 VSS
84 FBA_CMD_14 T3 A13 VSS J8 M7 NC#M7 VSS M1
M7 M1 0729 M9
0729 NC#M7 VSS VSS
VSS M9 VSS J2
J2 84,88 FBA_CMD_29 FBA_CMD_29 M2 P9
FBA_CMD_29 VSS FBA_CMD_6 BA0 VSS
84,88 FBA_CMD_29 M2 BA0 VSS P9 84,88 FBA_CMD_6 N8 BA1 VSS G8
84,88 FBA_CMD_6 FBA_CMD_6 N8 G8 84 FBA_CMD_30 FBA_CMD_30 M3 B3
FBA_CMD_30 BA1 VSS BA2 VSS
84 FBA_CMD_30 M3 BA2 VSS B3 VSS T1
160R3F-1-GP T1 A9
VSS VSS
OptimusR8904 1 2 VSS A9 84 FBA_CLK1 J7 CK VSS T9
84 FBA_CLK1 J7 CK VSS T9 84 FBA_CLK1# K7 CK# VSS E1
84 FBA_CLK1# K7 CK# VSS E1 VSS P1
P1 84 FBA_CMD_16 FBA_CMD_16 K9
FBA_CMD_16 VSS CKE
84 FBA_CMD_16 K9 CKE VSSQ G1
VSSQ G1 VSSQ F9
VSSQ F9 84 FBADQM7 D3 DMU VSSQ E8
D3 E8 0730 swap pin E7 E2
84 FBADQM6 DMU VSSQ 84 FBADQM5 DML VSSQ
0730 swap pin E7 E2 D8
84 FBADQM4 DML VSSQ VSSQ
VSSQ D8 VSSQ D1
D1 84,88 FBA_CMD_25 FBA_CMD_25 L3 B9
FBA_CMD_25 VSSQ FBA_CMD_15 WE# VSSQ
84,88 FBA_CMD_25 L3 WE# VSSQ B9 84,88 FBA_CMD_15 K3 CAS# VSSQ B1
FBA_CMD_15 FBA_CMD_11
84,88 FBA_CMD_15
FBA_CMD_11
K3 CAS# VSSQ B1 84,88 FBA_CMD_11 J3 RAS# Optimus VSSQ G9
84,88 FBA_CMD_11 J3 RAS# Optimus VSSQ G9
B H5TQ2G63BFR-11C-GP B
H5TQ2G63BFR-11C-GP
72.52G63.A0U 72.52G63.A0U
2nd = 72.41164.I0U 2nd = 72.41164.I0U
PCB Footprint = BGA96D0913H48 PCB Footprint = BGA96D0913H48
1112 X02 Modify: 1112 X02 Modify:
All of VRAM PCB footprint change to CO-LAY type All of VRAM PCB footprint change to CO-LAY type
(DUMMY-BGA96D075133H48) from BGA96D0913H48 (DUMMY-BGA96D075133H48) from BGA96D0913H48
1D5V_VGA_S0
1
Optimus R8901
1K05R2F-GP
2
FBA_VREF34
1
Optimus R8902 Optimus C8902

1K05R2F-GP SCD01U50V2KX-1GP
2
2
A <Variant Name> A
Wistron Corporation
Title
VRAM(2/4)
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
Frame Buffer Patition B Lower 32 bits.
FBRAM5 FBRAM6
1D5V_VGA_S0 FBBD[0..31] 84 1D5V_VGA_S0
FBBD[0..31] 84
K8 E3 FBBD21 K8 E3 FBBD26
VDD DQL0 FBBD18 VDD DQL0 FBBD25
K2 VDD DQL1 F7 K2 VDD DQL1 F7
D N1 F2 FBBD17 N1 F2 FBBD30 D
R9 VDD DQL3 F8 R9 VDD DQL3 F8
B2 H3 FBBD16 B2 H3 FBBD29
VDD DQL4 FBBD23 VDD DQL4 FBBD27 0802 swap
D9 VDD DQL5 H8 D9 VDD DQL5 H8
G7 G2 FBBD19 G7 G2 FBBD31
R1 VDD DQL7 H7 R1 VDD DQL7 H7
1D5V_VGA_S0 N9 1D5V_VGA_S0 N9
VDD FBBD6 VDD FBBD14
DQU0 D7 DQU0 D7
A8 C3 FBBD1 A8 C3 FBBD11
VDDQ DQU1 FBBD5 VDDQ DQU1 FBBD15
C1 C2 FBBD7 C1 C2 FBBD8
C9 VDDQ DQU4 A7 C9 VDDQ DQU4 A7
D2 A2 FBBD2 D2 A2 FBBD10
E9 VDDQ DQU6 B8 E9 VDDQ DQU6 B8
F1 A3 FBBD0 F1 A3 FBBD9
VDDQ DQU7 VDDQ DQU7
H9 VDDQ H9 VDDQ
Optimus H2 VDDQ DQSU C7 FBBDQSP0 84 H2 VDDQ DQSU C7 FBBDQSP1 84
C9001 B7 0730 swap pin B7 0730 swap pin
DQSU# FBBDQSN0 84 DQSU# FBBDQSN1 84
2 1 FBB_VREF12 H1 VREFDQ
FBB_VREF12 H1 VREFDQ
SCD01U50V2KX-1GP M8 F3 FBBDQSP2 84 M8 F3 FBBDQSP3 84
VREFCA DQSL VREFCA DQSL
2 R9002 1FBB_ZQ0 L8 ZQ DQSL# G3 FBBDQSN2 84 2 R9001 1FBB_ZQ1 L8 ZQ DQSL# G3 FBBDQSN3 84
243R2F-2-GP 243R2F-2-GP
Optimus K1 FBB_CMD_0 FBB_CMD_0 84 Optimus K1 FBB_CMD_0 FBB_CMD_0 84
FBB_CMD_7 ODT FBB_CMD_7 ODT
84,91 FBB_CMD_7 N3 A0 84,91 FBB_CMD_7 N3 A0
84,91 FBB_CMD_10 FBB_CMD_10 P7 84,91 FBB_CMD_10 FBB_CMD_10 P7
FBB_CMD_24 A1 FBB_CMD_2 FBB_CMD_24 A1 FBB_CMD_2
84,91 FBB_CMD_24 P3 A2 CS# L2 FBB_CMD_2 84 84,91 FBB_CMD_24 P3 A2 CS# L2 FBB_CMD_2 84
84,91 FBB_CMD_6 FBB_CMD_6 N2 T2 FBB_CMD_20 FBB_CMD_20 84,91 84,91 FBB_CMD_6 FBB_CMD_6 N2 T2 FBB_CMD_20 FBB_CMD_20 84,91
FBB_CMD_22 A3 RESET# FBB_CMD_22 A3 RESET#
84,91 FBB_CMD_22 P8 A4 84,91 FBB_CMD_22 P8 A4
84,91 FBB_CMD_26 FBB_CMD_26 P2 84,91 FBB_CMD_26 FBB_CMD_26 P2
C FBB_CMD_5 A5 FBB_CMD_5 A5 C
84,91 FBB_CMD_5 R8 A6 NC#T7 T7 84,91 FBB_CMD_5 R8 A6 NC#T7 T7
FBB_CMD_21 R2 L9 0729 FBB_CMD_21 R2 L9 0729
84,91 FBB_CMD_21 A7 NC#L9 84,91 FBB_CMD_21 A7 NC#L9
84,91 FBB_CMD_8 FBB_CMD_8 T8 L1 84,91 FBB_CMD_8 FBB_CMD_8 T8 L1
FBB_CMD_4 A8 NC#L1 FBB_CMD_4 A8 NC#L1
84,91 FBB_CMD_4 R3 A9 NC#J9 J9 84,91 FBB_CMD_4 R3 A9 NC#J9 J9
84,91 FBB_CMD_25 FBB_CMD_25 L7 J1 84,91 FBB_CMD_25 FBB_CMD_25 L7 J1
FBB_CMD_23 A10/AP NC#J1 FBB_CMD_23 A10/AP NC#J1
84,91 FBB_CMD_23 R7 A11 84,91 FBB_CMD_23 R7 A11
84,91 FBB_CMD_9 FBB_CMD_9 N7 84,91 FBB_CMD_9 FBB_CMD_9 N7
FBB_CMD_12 A12/BC# FBB_CMD_12 A12/BC#
84 FBB_CMD_12 T3 A13 VSS J8 84 FBB_CMD_12 T3 A13 VSS J8
M7 NC#M7 VSS M1 M7 NC#M7 VSS M1
0729 M9 0729 M9
VSS VSS
VSS J2 VSS J2
84,91 FBB_CMD_29 FBB_CMD_29 M2 P9 84,91 FBB_CMD_29 FBB_CMD_29 M2 P9
FBB_CMD_13 BA0 VSS FBB_CMD_13 BA0 VSS
84,91 FBB_CMD_13 N8 BA1 VSS G8 84,91 FBB_CMD_13 N8 BA1 VSS G8
84 FBB_CMD_27 FBB_CMD_27 M3 B3 84 FBB_CMD_27 FBB_CMD_27 M3 B3
160R3F-1-GP BA2 VSS BA2 VSS
VSS T1 VSS T1
OptimusR9005 1 2 VSS A9 VSS A9
84 FBB_CLK0 J7 CK VSS T9 84 FBB_CLK0 J7 CK VSS T9
84 FBB_CLK0# K7 CK# VSS E1 84 FBB_CLK0# K7 CK# VSS E1
VSS P1 VSS P1
84 FBB_CMD_3 FBB_CMD_3 K9 84 FBB_CMD_3 FBB_CMD_3 K9
CKE CKE
VSSQ G1 VSSQ G1
VSSQ F9 VSSQ F9
84 FBBDQM0 D3 DMU VSSQ E8 84 FBBDQM1 D3 DMU VSSQ E8
84 FBBDQM2 E7 DML VSSQ E2 84 FBBDQM3 E7 DML VSSQ E2
0730 swap pin D8 0730 swap pin D8
VSSQ VSSQ
VSSQ D1 VSSQ D1
84,91 FBB_CMD_28 FBB_CMD_28 L3 B9 84,91 FBB_CMD_28 FBB_CMD_28 L3 B9
FBB_CMD_15 WE# VSSQ FBB_CMD_15 WE# VSSQ
84,91 FBB_CMD_15 K3 CAS# VSSQ B1 84,91 FBB_CMD_15 K3 CAS# VSSQ B1
FBB_CMD_11 FBB_CMD_11
B 84,91 FBB_CMD_11 J3 RAS# VSSQ G9 84,91 FBB_CMD_11 J3 RAS# Optimus VSSQ G9
B
Optimus
H5TQ2G63BFR-11C-GP H5TQ2G63BFR-11C-GP
72.52G63.A0U 72.52G63.A0U
2nd = 72.41164.I0U 2nd = 72.41164.I0U
PCB Footprint = BGA96D0913H48
PCB Footprint = BGA96D0913H48
1112 X02 Modify:
All of VRAM PCB footprint change to CO-LAY type 1112 X02 Modify:
(DUMMY-BGA96D075133H48) from BGA96D0913H48 All of VRAM PCB footprint change to CO-LAY type
1D5V_VGA_S0 (DUMMY-BGA96D075133H48) from BGA96D0913H48
1
R9003
Optimus 1K05R2F-GP
2
FBB_VREF12
1
Optimus
R9004 C9002
Optimus 1K05R2F-GP SCD01U50V2KX-1GP
2
A <Variant Name> A
2
Wistron Corporation
Title
VRAM(3/4)
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
Frame Buffer Patition B Upper 32 bits.

FBRAM8
1D5V_VGA_S0 FBBD[32..63] 84
FBRAM7
1D5V_VGA_S0 FBBD[32..63] 84
K8 E3 FBBD44
FBBD35 VDD DQL0 FBBD40
D K8 VDD DQL0 E3 K2 VDD DQL1 F7 D
K2 F7 FBBD37 N1 F2 FBBD43
N1 VDD DQL2 F2 R9 VDD DQL3 F8
R9 F8 FBBD36 B2 H3 FBBD45
B2 VDD DQL4 H3 D9 VDD DQL5 H8
D9 H8 FBBD38 G7 G2 FBBD46
G7 VDD DQL6 G2 R1 VDD DQL7 H7
R1 H7 FBBD39 1D5V_VGA_S0 N9
1D5V_VGA_S0 N9 VDD DQL7 VDD FBBD59
VDD DQU0 D7
D7 FBBD48 A8 C3 FBBD58
DQU0 FBBD53 VDDQ DQU1 FBBD61
A1 C8 FBBD50 C1 C2 FBBD62
C1 VDDQ DQU3 C2 C9 VDDQ DQU4 A7
C9 A7 FBBD51 D2 A2 FBBD63 0730 swap pin
VDDQ DQU4 FBBD52 0730 swap pin VDDQ DQU5 FBBD56
D2 VDDQ DQU5 A2 E9 VDDQ DQU6 B8
E9 B8 FBBD49 0802 swap pin F1 A3 FBBD60
VDDQ DQU6 FBBD55 VDDQ DQU7
F1 VDDQ DQU7 A3 H9 VDDQ
H9 VDDQ H2 VDDQ DQSU C7 FBBDQSP7 84
Optimus H2 C7 B7 0730 swap pin
VDDQ DQSU FBBDQSP6 84 DQSU# FBBDQSN7 84
C9101 B7 0730 swap pin FBB_VREF34 H1
DQSU# FBBDQSN6 84 R9101 VREFDQ
2 1 FBB_VREF34 H1 VREFDQ M8 VREFCA DQSL F3 FBBDQSP5 84
SCD01U50V2KX-1GP M8 F3 FBBDQSP4 84 2 1FBB_ZQ3 L8 G3 FBBDQSN5 84
VREFCA DQSL ZQ DQSL#
2 R9105 1FBB_ZQ2 L8 ZQ DQSL# G3 FBBDQSN4 84 243R2F-2-GP
243R2F-2-GP Optimus K1 FBB_CMD_19 FBB_CMD_19 84
FBB_CMD_19 FBB_CMD_9 ODT
Optimus ODT K1 FBB_CMD_19 84 84,90 FBB_CMD_9 N3 A0
84,90 FBB_CMD_9 FBB_CMD_9 N3 84,90 FBB_CMD_24 FBB_CMD_24 P7
FBB_CMD_24 A0 FBB_CMD_10 A1 FBB_CMD_18
84,90 FBB_CMD_24 P7 A1 84,90 FBB_CMD_10 P3 A2 CS# L2 FBB_CMD_18 84
84,90 FBB_CMD_10 FBB_CMD_10 P3 L2 FBB_CMD_18 FBB_CMD_18 84 84,90 FBB_CMD_13 FBB_CMD_13 N2 T2 FBB_CMD_20 FBB_CMD_20 84,90
FBB_CMD_13 A2 CS# FBB_CMD_20 FBB_CMD_26 A3 RESET#
84,90 FBB_CMD_13 N2 A3 RESET# T2 FBB_CMD_20 84,90 84,90 FBB_CMD_26 P8 A4
C
84,90 FBB_CMD_26 FBB_CMD_26 P8 84,90 FBB_CMD_22 FBB_CMD_22 P2 C
FBB_CMD_22 A4 FBB_CMD_21 A5
84,90 FBB_CMD_22 P2 A5 84,90 FBB_CMD_21 R8 A6 NC#T7 T7
FBB_CMD_21 R8 T7 FBB_CMD_5 R2 L9 0729
84,90 FBB_CMD_21 A6 NC#T7 84,90 FBB_CMD_5 A7 NC#L9
FBB_CMD_5 R2 L9 0729 FBB_CMD_8 T8 L1
84,90 FBB_CMD_5 A7 NC#L9 84,90 FBB_CMD_8 A8 NC#L1
84,90 FBB_CMD_8 FBB_CMD_8 T8 L1 84,90 FBB_CMD_23 FBB_CMD_23 R3 J9
FBB_CMD_23 A8 NC#L1 FBB_CMD_28 A9 NC#J9
84,90 FBB_CMD_23 R3 A9 NC#J9 J9 84,90 FBB_CMD_28 L7 A10/AP NC#J1 J1
84,90 FBB_CMD_28 FBB_CMD_28 L7 J1 84,90 FBB_CMD_4 FBB_CMD_4 R7
FBB_CMD_4 A10/AP NC#J1 FBB_CMD_7 A11
84,90 FBB_CMD_4 R7 A11 84,90 FBB_CMD_7 N7 A12/BC#
84,90 FBB_CMD_7 FBB_CMD_7 N7 84 FBB_CMD_14 FBB_CMD_14 T3 J8
FBB_CMD_14 A12/BC# A13 VSS
84 FBB_CMD_14 T3 A13 VSS J8 M7 NC#M7 VSS M1
M7 M1 0729 M9
0729 NC#M7 VSS VSS
VSS M9 VSS J2
J2 84,90 FBB_CMD_29 FBB_CMD_29 M2 P9
FBB_CMD_29 VSS FBB_CMD_6 BA0 VSS
84,90 FBB_CMD_29 M2 BA0 VSS P9 84,90 FBB_CMD_6 N8 BA1 VSS G8
84,90 FBB_CMD_6 FBB_CMD_6 N8 G8 84 FBB_CMD_30 FBB_CMD_30 M3 B3
FBB_CMD_30 BA1 VSS BA2 VSS
84 FBB_CMD_30 M3 BA2 VSS B3 VSS T1
160R3F-1-GP T1 A9
R9103 VSS VSS
Optimus 1 2 VSS A9 84 FBB_CLK1 J7 CK VSS T9
84 FBB_CLK1 J7 CK VSS T9 84 FBB_CLK1# K7 CK# VSS E1
84 FBB_CLK1# K7 CK# VSS E1 VSS P1
P1 84 FBB_CMD_16 FBB_CMD_16 K9
FBB_CMD_16 VSS CKE
84 FBB_CMD_16 K9 CKE VSSQ G1
VSSQ G1 VSSQ F9
VSSQ F9 84 FBBDQM7 D3 DMU VSSQ E8
D3 E8 0730 swap pin E7 E2
84 FBBDQM6 DMU VSSQ 84 FBBDQM5 DML VSSQ
0730 swap pin E7 E2 D8
84 FBBDQM4 DML VSSQ VSSQ
VSSQ D8 VSSQ D1
D1 84,90 FBB_CMD_25 FBB_CMD_25 L3 B9
FBB_CMD_25 VSSQ FBB_CMD_15 WE# VSSQ
84,90 FBB_CMD_25 L3 WE# VSSQ B9 84,90 FBB_CMD_15 K3 CAS# VSSQ B1
B FBB_CMD_15 FBB_CMD_11 B
84,90 FBB_CMD_15
FBB_CMD_11
K3 CAS# Optimus VSSQ B1 84,90 FBB_CMD_11 J3 RAS# Optimus VSSQ G9
84,90 FBB_CMD_11 J3 RAS# VSSQ G9
H5TQ2G63BFR-11C-GP
H5TQ2G63BFR-11C-GP 72.52G63.A0U
72.52G63.A0U 2nd = 72.41164.I0U
2nd = 72.41164.I0U PCB Footprint = BGA96D0913H48
PCB Footprint = BGA96D0913H48 1112 X02 Modify:
All of VRAM PCB footprint change to CO-LAY type
1112 X02 Modify: 1D5V_VGA_S0 (DUMMY-BGA96D075133H48) from BGA96D0913H48
All of VRAM PCB footprint change to CO-LAY type
(DUMMY-BGA96D075133H48) from BGA96D0913H48
1
R9104
Optimus 1K05R2F-GP
1 2
FBB_VREF34
1
R9102 Optimus
Optimus 1K05R2F-GP C9102
SCD01U50V2KX-1GP
2
2
A <Variant Name> A
Wistron Corporation
Title
VRAM(4/4)
A3
QUEEN 15 A00
5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
SSID = PWR.Plane.Regulator_GFX
J J
DCBATOUT_GPU
MUXLESS
MUXLESS MUXLESS
1
PC9204 PC9215 PC9213 PC9214 PC9202 PC9205 PC9203
6
5
2
1
6
5
2
1
MUXLESS
D
D
D
D
D
D
D
D
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SCD1U25V3KX-GP
PU9202 PU9203
5V_S5
2
IRF6721SPBF-GP-U IRF6721SPBF-GP-U
84.06721.030 84.06721.030 Vout=0.75V*(R1+R2)/R2
S
I MUXLESS MUXLESS 2nd = 84.45N03.A30 2nd = 84.45N03.A30 I
1
MUXLESS MUXLESS
3
PC9201
PWR_VGA_CORE_TON PR9202 1 2249KR2F-GP MUXLESS MUXLESS MUXLESS Design Current = 32A
SC1U10V2KX-1GP 45<OCP<50A
2 PU9201
0927
ST470U2VDM-6-GP-U
ST470U2VDM-6-GP-U
ST470U2VDM-6-GP-U
PR9205
MUXLESS PC9206 MUXLESS PL9201 change VGA_CORE
MUXLESS 16 13 PWR_VGA_CORE_BOOT 1 2PWR_VGA_CORE_BOOT_C 1 2
2 PR9201 1 9
TON
VDDP
BOOT 2D2R3-1-U-GP SCD1U25V3KX-GP like CPU core
10R2F-L-GP 12 PWR_VGA_CORE_UGATE 1 PR9218 2 VGA_CORE_UGATE MUXLESS PL9201
PWR_VGA_CORE_VDD 2
UGATE
11 PWR_VGA_CORE_PHASE 0R0402-PAD 1 2
power choke.
VDD PHASE PWR_VGA_CORE_LGATE VGA_CORE_LGATE
8 1 PR9219 2 L-D36UH-1-GP PG9205
LGATE 0R0402-PAD
68.R3610.20A
7
6
2
1
7
6
2
1
1
8209A_PGOOD_VGA 4 7 2nd = 68.R3610.20C
SCD1U10V2KX-4GP
PWRCNTL_0 86
GAP-CLOSE-PWR-3-GP
1
1
D
D
D
D
D
D
D
D
PWR_VGA_CORE_CS PGOOD G0 PWR_VGA_CORE_FB PU9204 PU9205
1 2 10 3
PR9204 6K2R2F-GP CS FB IRF6725MTRPBF-GP-U IRF6725MTRPBF-GP-U PR9230 A00 1224
G1
14
PWR_VGA_CORE_D1
PWRCNTL_1 86 DY 2D2R5F-2-GP Modify to PCMC135T-R36MF
MUXLESS PT9202 PT9203 PT9204
1
MUXLESS MUXLESS 5
2
H 8209A_EN/DEM_VGA D1 PWR_VGA_CORE_D0 H
PC9208
15 6 84.06725.030 84.06725.030
2
PC9207 EM/DEM D0
3
SC1U10V2KX-1GP
G
S
S
G
S
S
20100702_PWR PWR_VGA_CORE_VOUT PWR_VGA_CORE_VOUT
2
17 1 2nd = 84.17N03.030 2nd = 84.17N03.030
1PWR_VGA_SNUB
GND VOUT
MUXLESS MUXLESS MUXLESS
5
4
3
5
4
3
1
10R2J-2-GP
MUXLESS MUXLESS
PR9203
RT8208BGQW-GP 0809
MUXLESS
MUXLESS
2
PC9218
77.24771.15L 77.24771.15L 77.24771.15L
VGA_SENSE_R
2nd = 79.47719.9BL 2nd = 79.47719.9BL 2nd = 79.47719.9BL
DY SC330P50V3KX-GP
83 VGA_SENSE
1 PR9211 2
0R0402-PAD
2
0928
PC9209 PC9210
Follow Brian suggestion.
1
G PR9208 G
SC10P50V2JN-4GP
SC10P50V2JN-4GP
10KR2F-2-GP DY
DY
2
2
RT8208B
MUXLESS MUXLESS
3D3V_VGA_S0 PR9206 1 210KR2J-3-GP PWRCNTL_1 PWRCNTL_0
P-State PWR_VGA_CORE_FB
PD9201 (GPIO6) (GPIO5) VGA_CORE_PWR
2 1 8209A_EN/DEM_VGA
93 DGPU_PWR_EN
DY P0(Cold)
1
1
CH551H-30PT-GP PC9211 L L 0.975V
MUXLESS SCD1U10V2KX-4GP PR9210//R9209//PR9213 PR9209 PR9210 R9213
P0(Hot) 0.954V 300KR2F-GP 82KR2F-1-GP 75KR2F-GP
2
F L H (default boot up) MUXLESS MUXLESS MUXLESS F

PR9210//PR9213
2
PWR_VGA_CORE_D1
ES
PWR_VGA_CORE_D0
H L 0.878V
R9210//PR9209
P8 & P12
H H 0.853V
PR9210
1GND_SENSE_1
0923
0923 update table Update value of PR9210, PR9209 and PR9213
PR9216
3D3V_VGA_S0 1 2 for N12P.
GND_SENSE 83
0R0402-PAD
PR9207
1
E
10R2J-2-GP E
PR9225 PR9224 MUXLESS
10KR2J-3-GP 10KR2J-3-GP
2
MUXLESS DY
2
PWRCNTL_0
PWRCNTL_1 Frequency setting
470K -->165KHz
1
PR9227 PR9226
0728 10KR2J-3-GP 10KR2J-3-GP FOR NVIDIA VENTURA 200K -->323KHz
0805 DY MUXLESS DCBATOUT DCBATOUT_GPU 100K -->500KHz
2
0705 Modify
0705 Modify
A00 1223 not co-lay

D D
1 2 0705 Modify:
PR9217 D004R3720F-GP Removed PR9222 sense Resistor.
Add PR9215,PR9216,PC9201
2
PR9215 PR9221 0702 Modify:

10R2F-L-GP 10R2F-L-GP Change U4306 power source to
3D3V_VGA_S0 from 3D3V_S0. 0915
VENTURA VENTURA
PC9217
1
1
PU9205_VIN+
PU9205_VIN-
1 2
VENTURA 3D3V_VGA_S0
SCD1U25V2KX-GP 3D3V_S5
2
1
C HPA00900AIDCNR-GP VENTURA PC9216 DY PR9228 C

100KR2J-1-GP
1
2
3
4
74.00900.079 SCD1U10V2KX-5GP
2
PWR_VGA_CORE_EN_R#
1
VIN-
VS
VIN+
GND
3D3V_VGA_S0 0712 Modify:

Change VENTURA solution part number to
3D3V_VGA_S0 74.00900.079 from 74.00219.079.
4
VENTURA
VGA_CORE
SDA
SCL
1
0728 PQ9206
A1
A0
1
PR9212 DMN66D0LDW-7-GP DY
10KR2J-3-GP R9227 R9225 PU9206
8
7
6
5
2
3K3R2J-3-GP 3K3R2J-3-GP
3
MUXLESS
DY DY PR9229
2
DY 100R2J-2-GP
2
8209A_PGOOD_VGA 1 PR9214 2 DGPU_PWROK 22,83,93

0R0402-PAD PU9205_A1
1
PU9205_A0
DY
1
B B
8209A_EN/DEM_VGA PQ9206_3
SMBC_INA219 43,85
1
PC9212
SC100P50V2JN-3GP R9228 R9226
2
3K3R2J-3-GP SMBD_INA219 43,85

MUXLESS 3K3R2J-3-GP 0607
VENTURA VENTURA
2
JV10-CS
Wistron Corporation
A A
Title
DC/DC_VGA CORE_RT8208A
QUEEN 15 A00
10 9 8 7 6 5 4 3 2 1
5 4 3 2 1
3D3V_S0 to 3D3V_VGA_S0 Transfer

3D3V_VGA_S0
DY
3D3V_S0 1 PR9301
2
0R2J-2-GP
DMP2130L-7-GP
PQ9302
2 S
1
PR9316 D
D
10KR2F-2-GP PC9324 84.02130.031
G
MUXLESS 2ND = 84.03413.A31 3D3V_VGA discharge
2
D SCD1U10V2KX-5GP MUXLESS D
1
G
MUXLESS
PR9319
1 2 PQ9302_G
10KR2F-2-GP
MUXLESS
PR9319_1
2
6
4
PR9314
PQ9303 470R2J-2-GP
2N7002KDW-GP
MUXLESS
84.2N702.A3F MUXLESS
1
2nd = 84.DM601.03F
3
MUXLESS PR9337
A00 1 2 3.3V_RUN_VGA_1
19,45,46,47 RUNPWROK 100KR2J-1-GP
PR9321
1 2
3D3V_S0 DY
DGPU_PWR_EN
10KR2J-3-GP
2N7002K-2-GP
18 DGPU_PWR_EN#
G MUXLESS NV do not need 1.8V
D DGPU_PWR_EN 92
S
PQ9304
84.2N702.J31
2ND = 84.2N702.031
C C
DGPU_PWR_EN#
dGPU mode L
IGPU H
IGPU with BACO L
0628 Modify:
change low Rds(on) MOSFET Change PU9305 part number to 84.04468.037 same as U3601&U3602.
1D5V_VGA_S0 1D5V_S3
MUXLESS
1D5V_VGA_S0
G9731F11U-GP for 1V_S0
PU9305
AO4468, SO-8 8 D S 1
7 D S 2 0629 Modify: 3D3V_VGA_S0 should ramp-up before VGA_Core higih-side R + low-side R
Id=?A, Qg=9~12nC 6 D S Add PC9332 10uF 0603. Vout = 0.8 x low-side R
3 Iomax<4A
1
Rdson=17.4~22m ohm 5 D G 4 PC9332 VGA_Core should ramp-up before 1V_VGA_S0

1
1D5V_ENABLE_RC
PC9327
MUXLESS AO4468-GP SC10U6D3V3MX-GP 1V_VGA_S0 should ramp up before 1D8V_VGA_S0
2
84.04468.037 MUXLESS 0806

SC10U6D3V3MX-GP
2
2
2nd = 84.08882.037 so 1V_VGA_S0 EN have to fine tune RC delay PG9308
PR9315 1 2
after VGA_Core 15KR2F-GP
0927 MUXLESS GAP-CLOSE-PWR
0630 Modify
0714 Modify:
1
PR9312 A00 1224 Change PR9312 to 10K 0402 from MUXLESS PG9307
B PR9330 0ohm and stuff PC9318. B
Park_Madison Does Not Support BACO, So follow Old Sequence 1MUXLESS
2 1 2
Seymour_Whistler_Robson Support BACO, So Change Sequence 1 2
3D3V_VGA_S0 Change LDO to Max 4A. PR9322 4K7R2F-GP
1 2 GAP-CLOSE-PWR
Discharge Circuit 0R0402-PAD-2-GP
PC9315
1
20KR2F-L-GP 0629 Modify: PWR_1V_EN PG9305

MUXLESS
3D3V_AUX_S5 PC9326 MUXLESS 1D5V_VGA_S0 Reserved PD9302 connect DGPU_PWR_EN to PU9303 PWR_1V_ADJ 1 DY 2 1 2
SCD1U10V2KX-5GP
SCD01U50V2KX-1GP PWR_1V_EN for power down sequence.
2
PC9318
1 2 1D5V_VGA_EN# 9 1 1V_PWR GAP-CLOSE-PWR 1V_VGA_S0
1
PR9332 100KR2J-1-GP 3D3V_VGA_S0 GND GND SC100P50V2JN-3GP
PD9302 8 2
DY
1
VEN ADJ
MUXLESS D G S 92 DGPU_PWR_EN 2 DY 1 7
POK VO#3
3 PG9306
PR9336 6 4 1 2
2
1
CH551H-30PT-GP VPP VO#4
470R2J-2-GP 5
6
0629 Modify: PR9324 VIN GAP-CLOSE-PWR

MUXLESS Vo(cal.)=1.05V
1
Reserved PD9301 connect DGPU_PWR_EN to PQ9305 15V_S5 2K2R2J-2-GP PC9317 PC9316
DIS_1D5V_VGA_S02
PWR_1D5V_EN for power down sequence. 2N7002KDW-GP A00 1224 MUXLESS G9731F11U-GP DY
2ND = 84.2N702.031
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
84.2N702.A3F MUXLESS
2
PR9311
84.2N702.J31 MUXLESS
1
PD9301 2nd = 84.DM601.03F 9025_PGOOD_1V 1MUXLESS

2 PWR_1V_PGOOD
2 DY 1 MUXLESS S G D PR9331
2N7002K-2-GP 85 9025_PGOOD_1V 74.G9731.03D
92 DGPU_PWR_EN 100KR2J-1-GP G 1D5V_VGA_EN# 0R0402-PAD-2-GP
CH551H-30PT-GP MUXLESS A00 1224 2nd = 74.05930.03D
D
1
1 PR9326 2 1D5V_VGA_EN PR9313

22,83,92 DGPU_PWROK PWR_1V_VDD
S 5V_S5 1MUXLESS2
MUXLESS A00 1224 1D5V_ENABLE MUXLESS
0R0402-PAD-2-GP PQ9307 0R0402-PAD-2-GP
1
0630 Modify: PC9313 MUXLESS
SC1U6D3V2KX-GP
0628 Modify: Rename PWR_1D8V_EN to 1D8V_VGA_EN.
1D5V_S3
Simplify 1D5V_ENABLE control circuit. Rename PWR_1D5V_EN to 1D5V_VGA_EN.
1
Rmoved PQ9305,PR9327,PR9328 PQ9306.
PC9314
2
SC10U6D3V5MX-3GP MUXLESS
PR9318
0915
3D3V_S5 1 2 PWR_1V_EN#
A
0728 A
100KR2J-1-GP
DY
6
PQ9311
<Core Design>
2N7002KDW-GP
84.2N702.A3F
Wistron Corporation
1
2nd = 84.DM601.03F
DY 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
PR9317
Title
PQ9308_3 2 1 1V_VGA_S0 DISCRETE VGA POWER
PWR_1V_EN
470R2J-2-GP
DY
A2 QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
<Variant Name>
A A
Wistron Corporation
Title
LVDS_Switch
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
<Variant Name>
A A
Wistron Corporation
Title
CRT_Switch
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
SSID = SDIO
D D
C C
(Blanking)
B B
A <Variant Name> A
Wistron Corporation
Title
TOUCH PANEL
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
H2 H6 H9 H10
HOLE335R115-GP HOLE237R95-GP HOLE335R115-GP HOLE335R115-GP
ZZ.00PAD.D01 ZZ.00PAD.921 ZZ.00PAD.D01

Check test point
ZZ.00PAD.D01
1
DY DY DY DY
D D
0624 Modify:
Removed AFTP1,AFTP7~AFTP13.
H3 H4 H11 H12
stand off
HOLE256R126-GP HOLE256R126-GP HOLE256R126-GP HOLE256R126-GP
CPU Thermal module hole
HTML1 HTML2 HTML3
HOLE197R166-GP HOLE197R166-GP HOLE197R166-GP
0721 Modify:
1
1
Removed SPR1
ZZ.00PAD.J01 ZZ.00PAD.J01 ZZ.00PAD.J01 ZZ.00PAD.J01
1
DY DY DY
0915 X01 Modify:
RF CAP Reserved EC9701~EC9723 0.1uF for
RF suggestion.
1D5V_S3 1D5V_S3 5V_S0 5V_S0 3D3V_S5 3D3V_S5 3D3V_S5 5V_S5 3D3V_S0 3D3V_S0 DCBATOUT 5V_S5
SC47P50V3JN-GP
SCD22U50V3ZY-1GP
EC9716
SCD1U50V3KX-GP
EC9734
SCD1U50V3KX-GP
EC9718
SCD1U50V3KX-GP
EC9719
SCD1U50V3KX-GP
EC9736
SCD1U50V3KX-GP
EC9720
SCD1U50V3KX-GP
EC9735
EC9717
SCD1U50V3KX-GP
SC47P50V3JN-GP
EC9722
SCD1U50V3KX-GP
EC9721
SCD1U50V3KX-GP
H1 H5 H13 H7 H15
1
EC9737
EC9738
C HT10X10BE10R32-D-5-GP HT10X10BE10R32-D-5-GP HT10X10BE10R32-D-5-GP HT10X10BE10R32-D-5-GP HT10X10BE10R32-D-5-GP C
DY DY DY DY DY DY DY DY DY
DY DY DY DY DY
2
ZZ.00PAD.J91 ZZ.00PAD.J91 ZZ.00PAD.J91 ZZ.00PAD.J91 ZZ.00PAD.J91
1
1
5V_S5 DCBATOUT 1D05V_VTT 1D5V_S3 DCBATOUT 3D3V_S0 3D3V_S0 5V_S0 5V_S0 3D3V_S5 3D3V_S5 3D3V_S0
SC47P50V3JN-GP
EC9728
SCD1U50V3KX-GP
EC9723
SCD1U50V3KX-GP
EC9727
SCD1U50V3KX-GP
EC9731
SCD1U50V3KX-GP
EC9724
SCD1U50V3KX-GP
EC9732
SCD1U50V3KX-GP
EC9733
SCD1U50V3KX-GP
EC9725
SCD1U50V3KX-GP
EC9726
SCD1U50V3KX-GP
EC9739
1
1
EC9729
SC470P50V-2-GP
EC9730
SC470P50V-2-GP
DY DY DY DY DY DY DY DY DY
0901
2
3D3V_S0 1D8V_S0 DCBATOUT DCBATOUT DCBATOUT
1D5V_S3 1D5V_S3 1D5V_S3 1D5V_S0
1
1
B EC9701 EC9702 EC9703 EC9704 EC9705 EC9706 EC9707 EC9708 EC9709 EC9710 EC9711 B
1
DY DY DY EC9712 EC9713 EC9714 EC9715
DY SCD1U50V3KX-GP DY DY DY DY DY DY DY SCD1U50V3KX-GP DY DY DY DY
2
2
1D8V_S0 3D3V_S0
SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U50V3KX-GP SCD1U50V3KX-GP SCD1U50V3KX-GP SCD1U50V3KX-GP SCD1U50V3KX-GP SCD1U50V3KX-GP
SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GPSCD1U10V2KX-4GP
0802 For EMI/ESD.
GPU Thermal module hole

HHD1 HHD4 HBT1
STF237R117H83-1-GP HGPU1 HGPU2 STF237R117H83-1-GP STF237R117H123-GP
STF237R117H83-1-GP STF237R117H83-1-GP
A DY <Variant Name> A
34.4CK01.001 34.4CK01.001
1
1
34.4CK01.001 34.4CK01.001
1
2nd = 34.4CK01.401 2nd = 34.4CK01.401 Wistron Corporation

3rd = 34.4CK01.501 2nd = 34.4CK01.401 2nd = 34.4CK01.4013rd = 34.4CK01.501 34.4DM11.001
3rd = 34.4CK01.501 3rd = 34.4CK01.501 2nd = 34.4A902.001 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Title
0818
UNUSED PARTS/EMI Capacitors
A00 0103 add 3rd LIDON(34.4CK01.501) on HDD1,HDD4,HGPU1,HGPU2 at XBuild batch run Size Document Number Rev
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
Huron River Platform Power Sequence

(AC mode) red word: KBC GPIO
(DC mode) red word: KBC GPIO
+RTC_VCC
+RTC_VCC T1 >9ms
T1 >9ms
RTC_RST#
RTC_RST#
DCBATOUT
DCBATOUT T2
T2
Within logic high level and disable if
3D3V_AUX_S5
it is less than the logic low level.
3D3V_AUX_S5
KBC GPIO34 control power on by 3V_5V_EN
D D
S5_ENABLE Sense the power button status Press Power button
KBC_PWRBTN# Platform to KBC PSL_IN2
5V_S5 T3
V5REF_Sus must be powered up before EC_ENABLE#_1(GPIO31) keep low
VccSus3_3, or after VccSus3_3 within
0.7 V. Also, V5REF_Sus must power
3D3V_S5 T4 3D3V_AUX_KBC
down after VccSus3_3, or before
T3 KBC GPIO34 control power on by 3V_5V_EN
VccSus3_3 within 0.7 V.
+5VA_PCH_VCC5REFSUS T5 S5_ENABLE
KBC GPIO43 to PCH
PM_RSMRST#(EC Delay 40ms) T6 >10ms 5V_S5 T4
PCH to KBC GPIO00 V5REF_Sus must be powered up before
+5V_ALW & +3.3V_ALW need meet 0.7V difference
VccSus3_3, or after VccSus3_3 within
PCH_SUSCLK_KBC T7 >5ms 0.7 V. Also, V5REF_Sus must power
3D3V_S5 T5
KBC GPO84 to PCH down after VccSus3_3, or before
+5V_ALW & +3.3V_ALW need meet 0.7V difference
Not floating. VccSus3_3 within 0.7 V.
AC_PRESENT 0ms<T8 <90ms +5VA_PCH_VCC5REFSUS T6
T7 >16ms KBC GPIO20 to PCH

Press Power button
3D3V_AUX_KBC PM_PWRBTN#
Platform to KBC PSL_IN2
Sense the power button status
AC KBC_PWRBTN#
KBC GPIO43 to PCH
This signal has an internal T9 >16ms PM_RSMRST# T8 >10ms
pull-up resistor and has an KBC GPIO20 to PCH
internal 16 ms de-bounce on the PCH to KBC GPIO00
input. AC PM_PWRBTN#
PCH_SUSCLK_KBC T9 >5ms
AC PM_PWRBTN# DC PCH_RSMRST#
T10 T10
PCH to KBC GPIO44 PCH to KBC GPIO44
PM_SLP_S4# PM_SLP_S4#
T11 PCH to KBC GPIO01 T11 PCH to KBC GPIO01
PM_SLP_S3# >30us PM_SLP_S3# >30us
KBC GPIO23 to LAN KBC GPIO23 to LAN
PM_LAN_ENABLE PM_LAN_ENABLE
Enable by PM_SLP_S4# Enable by PM_SLP_S4#
1D5V_S3 T12 1D5V_S3 T12
DDR_VREF_S3(0.75V) T13 DDR_VREF_S3(0.75V) T13

C
+5V_RUN & +3.3V_RUN need meet 0.7V difference +5V_RUN & +3.3V_RUN need meet 0.7V difference C
5V_S0 T14 5V_S0 T14
V5REF must be powered up before 3D3V_S0 T15 V5REF must be powered up before 3D3V_S0 T15
Vcc3_3, or after Vcc3_3 within 0.7 V. Vcc3_3, or after Vcc3_3 within 0.7 V.
Also, V5REF must power down after Also, V5REF must power down after
Vcc3_3, or before Vcc3_3 within 0.7 V. Vcc3_3, or before Vcc3_3 within 0.7 V.
+5VS_PCH_VCC5REF T16 +5VS_PCH_VCC5REF T16
1D5V_S0 T17 1D5V_S0 T17
1D8V_S0 T18 1D8V_S0 T18
0D75V_S0 T19 0D75V_S0 T19

1D8V_S0 & 1D5V_S3 power ready 1D8V_S0 & 1D5V_S3 power ready
RUNPWROK T20 RUNPWROK T20
1D05V_VTT T21 1D05V_VTT T21

VT357FCX PGOOD VT357FCX PGOOD
1.05VTT_PWRGD T22 1.05VTT_PWRGD T22
0D85V_S0 T23 0D85V_S0 T23
0D85V_S0 0D85V_S0
T24 TPS51461RGER PGOOD T24 TPS51461RGER PGOOD
D85V_PWRGD D85V_PWRGD
SetVID ACK SetVID ACK

CPU SVID BUS 50us< T25 <2000us CPU SVID BUS 50us< T25 <2000us
VCC_CORE VCC_CORE
VCC_GFXCORE VCC_GFXCORE
T26 T26
<5ms
ISL95831 PGOOD to system <5ms
ISL95831 PGOOD to system
IMVP_PWRGD IMVP_PWRGD
CLK_EXP_P CLK_EXP_P
ALL_SYS_PWRGD=D85V_PWRGD ALL_SYS_PWRGD=D85V_PWRGD
B This signal represents the Power T27 >99ms KBC GPIO77 to PCH This signal represents the Power T27 >99ms KBC GPIO77 to PCH B
Good for all the non-CORE and Good for all the non-CORE and
non-graphics power rails.
PWROK non-graphics power rails.
PWROK
T28 >0us T28 >0us
D85V_PWRGD D85V_PWRGD
2ms< T29 <650ms PCH to CPU 2ms< T29 <650ms PCH to CPU
VDDPWRGOOD VDDPWRGOOD
T30 >1ms T30 >1ms
T31 >2ms T31 >2ms
1D8V_S0 1D8V_S0
5ms< T32 <650ms PCH to CPU 5ms< T32 <650ms PCH to CPU
H_CPUPWRGD H_CPUPWRGD
SYS_PWROK T33 >0ms SYS_PWROK T33 >0ms

T34 >1ms+60us T34 >1ms+60us
1ms< T35 <100ms PCH to all system 1ms< T35 <100ms PCH to all system
PLT_RST# PLT_RST#
T36 <200us T36 <200us
DMI DMI
N12P-GE Power-Up/Down Sequence
3D3V_S0
PCH GPIO54 output
DGPU_PWR_EN#(Discrete only)
3D3V_VGA_S0(VDD33)
8209A_EN/DEM_VGA(Discrete only)
VGA_CORE(NVVDD) tNVVDD >0ms

RT8208 PGOOD
DGPU_PWROK(Discrete only)
A A
1D5V_VGA_S0(FBVDDQ) tNV-FBVDDQ >0ms
First rail to power down VGA_CORE,1V_VGA_S0

1D5V_VGA_S0,3D3V_VGA_S0
Last rail to power down
tPOWER-OFF <10ms
<Core Design>
For power-down, reversing the ramp-up sequence is recommended. Wistron Corporation

Title
Power Sequence
A1
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
Wistron HURON RIVER POWER UP SEQUENCE DIAGRAM

5V_S5 DCBATOUT
-6
AC AD+
Adapter in
Page38
-3.1 -3.1 -3.1
VDDP VIN 1D5V_S3
D PWR_5V3D3V_ENC 3V_5V_EN S5_ENABLE VOUT D
3
PM_SLP_S4#
EN
-3.2 -3.3 DDR_VREF_S3
PWR_CHG_ACOK REF
SWITCH ENC 5V_S5 15V_S5
LL1 PUMP
Page40
3D3V_S5 TPS51116RGER
LL2
0D75V_S0
5V_AUX_S5 VTT
RT8223MGQW VREG5
DC/DC 3D3V_AUX_S5 -5
-6.1 (3V/5V) VREG3 3 RUNPWROK
PGD
DCBATOUT 3V_5V_POK PM_SLP_S4#

VIN PGOOD -2 Page46
5
Page41
4 5V_S5 3D3V_S5
DC BQ24745 5V_S0
BT+ PM_SLP_S3#
Battery Charger SWITCH
Page39 -3 BJT Page37
3D3V_AUX_KBC VDD VIN 1D8V_S0
-3.1 4 VOUT
Page40 ACOK 3D3V_S0
S5_ENABLE SWITCH
-4 Page37 PM_SLP_S3# TPS53311RGTR
EN
RUNPWROK
AC_IN# GPIO34 1D5V_S0
PGD
GPIO70 Page47
C SWITCH C
Page37 5
1 SLP_S4# SLP_S3#
-1 KBC
KBC_PWRBTN#
GPIO6 NPCE795P -2.1
11 AND GATE
Power Button PM_RSMRST# 0D75V_EN
PM_SLP_S4# GPIO43 RSMRST# B VDDPWRGOOD
GPIO44 PM_PWRBTN# PM_DRAM_PWRGD Y SM_DRAMPWROK
PM_SLP_S3# GPIO20 PWRBTN# DRAMPWRGD A
GPIO01
2 H_CPUPWRGD H_CPUPWRGD_R
PROCPWRGD UNCOREPWRGOOD
Page27 Cougar Point 12
GPIO77 PCH Sandy Bridge
13 CPU
S0_PWR_GOOD
APWROK
PWROK PLT_RST# BUF_CPU_RST#
PLTRST# RSTIN#
SYS_PWROK SVID
SYS_PWROK
SVID
10
8
5V_S5 DCBATOUT
B V5IN VIN B
1D05_VTT
VOUT
5 AND GATE 10
S0_PWR_GOOD
RUNPWROK TPS51218DSCR A SYS_PWROK
EN 1.05VTT_PWRGD IMVP_PWRGD Y
Page45 PGOOD B
5V_S5 DCBATOUT 5a
VDDP VIN 0D85_S0 -5

VOUT
5a -7 3D3V_AUX_S5
1.05VTT_PWRGD RT8208BGQW RTC_AUX_S5
EN D85V_PWRGD
Page48 PGOOD -8
+RTC_VCC
6
DCBATOUT
RTC battery
8 VIN VCC_CORE
OUTPUT
SVID
SVID VCC_GFXCORE
A VR OUTPUT A
6 7 ISL95831HRTZ
D85V_PWRGD IMVP_VR_ON 9 <Core Design>
VR_ON IMVP_PWRGD
Page42 & 43 & 44 PGOOD
Wistron Corporation
Power Up Sequence: -8 ~ 13 Title

Power Sequence Diagram
Rev
A2
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
1V_VGA_S0 RT9025
RT8208B VGA_CORE For Discrete
D D
DCBATOUT TPS51216RUKR
Adapter
ISL95831HRTZ TPS51218DSCR
AO4407A DDR_VREF_S3 0D75V_S0 1D5V_S3
Charger
BQ24745 VCC_CORE VCC_GFXCORE 1D05V_VTT
For UMA
TPCA8062 AO4468
Battery +PBATT
APL5916KAI
1D5V_S0 1D5V_DDR_S0
C C
0D85V_S0
TPS51123RGER
For Discrete
3D3V_AUX_S5
3D3V_S5
15V_S5 5V_AUX_S5 5V_S5
AO4468 G547F2P81U AO4468 PA102FMG

DMP2130L TPS51311RGTR
5V_S0 5V_USB1_S3 3D3V_S0 3D3V_LAN_S5

3D3V_AUX_KBC 1D8V_S0
B B
CRT Board USB Power
AO4468 G5285T11U RTS5138 DMP2130L RTL8111E
1D8V_VGA_S0 LCDVDD 3D3V_CARD_S0 3D3V_VGA_S0 +1.2V_LOM
For Discrete For Discrete
Power Shape
Regulator LDO Switch

A <Core Design> A
Wistron Corporation
Title
Size
Power Block Diagram
Document Number Rev
A3
QUEEN 15 A00
5 4 3 2 1
A B C D E
PCH SMBus Block Diagram 3D3V_S5 3D3V_S0 KBC SMBus Block Diagram
3D3V_S0
E E
3D3V_S0 E
SRN2K2J-1-GP SRN2K2J-1-GP
E
SMBCLK SMB_CLK
DIMM 1 SRN10KJ-5-GP
E EPCH_SMBCLK
1 SMBDATA SMB_DATA
E E PCH_SMBDATA
SCL
SDA PSDAT1 TPDATA TPDATA TPDATA

TouchPad Conn. 1
3D3V_S5 E
PSCLK1 TPCLK TPCLK TPCLK
SMBus Address:A0 E
2N7002SPT
E 3D3V_AUX_KBC
SRN2K2J-8-GP 3D3V_S5
E
E
SML1CLK SML1_CLK
SRN4K7J-8-GP
SML1DATA SML1_DATA To KBC SRN2K2J-1-GP
DIMM 2
SML0CLK SML0_CLK
EPCH_SMBCLK SCL SRN100J-3-GP Battery Conn.
E PCH_SMBDATA SDA
GPIO17/SCL1 BAT_SCL BATA_SCL_1 CLK_SMB
SML0DATA SML0_DATA GPIO22/SDA1 BAT_SDA BATA_SDA_1 DAT_SMB SMBus address:16

SMBus Address:A4
3D3V_S0 G-Sensor BQ24745

E EPCH_SMBCLK SCLK
KBC SCL
SDA SMBus address:12

PCH E PCH_SMBDATA SDATA
NPCE795P
SRN2K2J-1-GP
UMA SMBus address:xx
2 2
SDVO_CTRLCLK PCH_HDMI_CLK Level DDC_CLK_HDMI
SDVO_CTRLDATA PCH_HDMI_DATA
Shift DDC_DATA_HDMI Minicard
UMA
EPCH_SMBCLK
WLAN
SMB_CLK
3D3V_S0
E PCH_SMBDATA SMB_DATA
E
SRN2K2J-1-GP Minicard GPIO73/SCL2 SML1_CLK SCL
UMA SRN0J-6-GP
PCH_SMBCLK
W-WAN GPIO74/SDA2 SML1_DATA SDA PCH
SMB_CLK
L_DDC_CLK LVDS_DDC_CLK_R
PCH_SMBDATA
SMB_DATA
L_DDC_DATA LVDS_DDC_DATA_R
UMA
3D3V_VGA_S0
CRT_DDC_CLK CRT_DDC_CLK
CRT_DDC_DATA CRT_DDC_DATA
E
SRN2K2J-1-GP
DIS
SRN0J-6-GP
3 DDC1CLK GPU_LVDS_CLK LVDS_DDC_CLK CLK 3
DDC1DATA GPU_LVDS_DATA LVDS_DDC_DATA DATA LCD CONN

DIS SRN0J-6-GP
DDC2CLK VGA_CRT_DDCCLK
DDC2DATA VGA_CRT_DDCDATA
3D3V_S0 DIS 5V_S0
VGA E E
3D3V_S0
SRN2K2J-1-GP SRN10KJ-6-GP
UMA
E
SRN0J-6-GP UMA
CRT_DDCCLK_CON
CRT_DDCDATA_CON
CRT CONN
5V_HDMI
3D3V_VGA_S0 UMA
2N7002DW-1-GP
E
E
3D3V_S0
SRN1K5J-GP
SRN2K2J-1-GP
4 4
DIS
DDC2CLK GPU_HDMI_CLK Level DDC_CLK_HDMI
DDC2DATA GPU_HDMI_DATA
Shift DDC_DATA_HDMI
HDMI CONN <Core Design>
SRN0J-6-GP
Wistron Corporation
Title
SMBUS Block Diagram

DIS Size Document Number Rev
A2 QUEEN 15 A00
A B C D E
A B C D E
Thermal Block Diagram Audio Block Diagram

1 1
SPKR_PORT_D_L-
PAGE28 DXP P2800_DXP SPKR_PORT_D_R+ SPEAKER

MMBT3904-3-GP
SC2200P50V2KX-2GP
DXN P2800_DXN
UMA Place near CPU
Codec
Thermal PWM CORE
92HD79B1
P2800 HP1_PORT_B_L HP
MMBT3904-3-GP HP1_PORT_B_R
PAGE27 GPIO5 SYS_THRM TDR T8

OUT
2
KBC GPIO92 CPU_THRM TDL
OTZ THERM_SYS_SHDN#
2N7002
D
PURE_HW_SHUTDOWN#
EN 3V/5V 2
NPCE795P S
G
IMVP_PWRGD PGOD
VR
Put under CPU(T8 HW shutdown)
GPIO94 GPIO56
GPIO4 VGA_THRM TDR
PAGE28
HP0_PORT_A_L MIC
P2800_VGA_DXP HP0_PORT_A_R
DXP THRMDA
VREFOUT_A_OR_F IN
FAN_TACH1
SC2200P50V2KX-2GP SC2200P50V2KX-2GP
VGA DXN
P2800_VGA_DXN
THRMDC
VGA
Thermal
FAN1_DAC
TACH Place near GPU(DISCRETE only).

P2800
FAN
VIN
MMBT3904-3-GP DMIC_CLK/GPIO1 Digital
5V
DMIC0/GPIO2
3 MIC 3
PH
OTZ
VSET VOUT
VIN
FAN CONTROL
P2793 PORTC_L
PAGE28 PORTC_R
Analog
VREFOUT_C MIC
4 4
<Core Design>
Wistron Corporation
Title
Size
Thermal/Audio Block Diagram
Document Number Rev
Custom
QUEEN 15 A00
A B C D E
5 4 3 2 1
VERSION DATA PAGE Change Iteam VERSION DATA PAGE Change Iteam
08/25 14 SWAP SA0_DM1 and SA1_DIM1 each other for DM2 can't boot up issue. 09/06 15 DM1 2nd=62.10017.Q31, 3rd=62.10017.K01.
08/29 28 Change U2802 Main source to 74.00991.031, 2nd 74.02793.A31,3rd 74.05606.071 09/06 14 DM2 2nd=62.10017.P31, 3rd=62.10017.K11.
08/29 61 Add 2nd 77.C1071.20L on TC6101. 09/07 68 Add 2nd source 20.K0343.004 on PWRBTN1& PWRBTN2 base on updated connector list.
D D
08/29 64 Re-assign FP1 pin define. 09/07 69 Add 2nd source 20.K0343.004 on KBLIT1 base on updated connector list.
08/29 71 Un-stuff Debug port connector(DB1) on X01. 09/07 82 Add 2nd source 20.F0085.040 on CRTBD1 base on updated connector list.
Change U3701 pin2 to RUNPWROK from 0D75V_EN. Reserved R3717 0ohm between
08/29 37 PM_DRAM_PWRGD and VDDPWRGOOD_R. 09/07 64 Add 2nd source 20.K0382.006 on FP1 base on updated connector list.
08/29 37 Change R2724 to 20K 0402 from 10K for X01 stage. 09/07 75 Add 2nd source 20.K0382.026 on NEW1 base on updated connector list.
08/29 40 Change 3D3V_AUX_S5 to 3D3V_AUX_KBC to avoid leakage Voltage to 3D3V_AUX_KBC under DC mode. 09/07 4~10 Updated CPU1 footprint to SKT-BGA989C470395-1H180 from SKT-BGA989C470395-1H186 base on data
base updated.
08/31 51 HDMI1 change to 22.10296.311 from 22.10296.271 Add 2nd source 62.10040.771 on CPU1 base on updated connector list.
08/31 28 FAN1 change to 20.F0772.003 from 20.F1639.004 09/07 75 Change CARD1 to 20.I0129.001 from 62.10051.931 from ME double updated latest DXF&EMN on X01.
08/31 57 E-SATA1 change to 22.10321.W11 from 22.10290.141 09/07 93 PQ9308 change name to PQ9311.
09/01 41 PU4104 and PU 4105 horizontally mirror. 09/07 ALL Change all of single 2N7002 to 84.2N702.J31 from 84.2N702.D31 due to 84.2N702.D31 will EOL.
09/01 83 R8305 Change to 30K ohm. 09/07 28 Change U2801,U2803 to 74.02800.A71 from 74.02800.071 from vender updated parts.
C C
Change R2803&R2817 to 107K from 499K,R2804&R2818 to 226K from 102K base on updated ADJ Table.
09/01 97 H1, H5, H13, H7 and H15 change to ZZ.00PAD.J91 from ZZ.00PAD.D01.
09/08 18, 22 Change FFS_INT2_R from PCH GPIO48 to GPIO14 Keep PCH_GPIO5 PH R2201,PCH_GPIO48 PH R2220.
09/01 56 HDD1 add 2nd=62.10065.121. Add R1818.
09/01 79 U7901 change main source to 74.00351.0B3. 09/08 82 1.Rename IOBD1 pin20,22,26,28 to IOBD1_20,22,26,28 from PCIE_TXN5,PCIE_TXP5,PCIE_RXP5,PCIE_RXN5.
2.Add RN8207,RN8208 for optional USB3.0 PCIE or USB2.0 signal.
X01 09/01 42 PR4226 change to 5.62K ohm.
09/01 45 PTC4502 change to 79.3971V.30L. X01 09/08 18 Reserved USBP9~USBP10 to IOBD1 pin20,22,26,28.
09/03 61 U6101 add 2nd=74.00547.079. 09/08 37 Stuff Q3704,R3710; un-stuff R3716. U3701 pin2 change to 1.05VTT_PWRGD from RUNPWROK.
09/03 49 U4901 add 2nd=74.09724.09F. 09/08 20 DY R2002.
09/03 40 PU4002 and PU4003 add 2nd=84.P1403.B37. 09/08 47 Mount PC4710.
09/03 24 L2401,L2402,L2403 add 2nd=68.10090.10B. 09/08 98 Update N12P power sequence.
B B
09/03 27 DY C2713. Add C2722. 09/09 82 R8201, R8202 and R8203 change to 62 ohm.
09/03 47 Add PR4702 09/10 45 Change PL4501 to 68.2R210.20C from IND-D56UH-27-GP base on Brian updated.
09/03 22 Change FFS_INT2_R from PCH GPIO48 to GPIO15 09/10 41 Change PL4101,PL4102 to 68.2R210.20B from 68.2R210.20Q base on Brian updated.
Removed R2220 and change R2201 default pull up to pull down.
09/10 82 Rename IOBD1 pin14 to IOBD1_14 from USB30_SMI#.
Add R8207 for USB20 USB_OC#10_11
09/06 20 X2001 add 3rd=82.30020.A31. Add R8206 for USB30 USB30_SMI#
Add R8208 for USB20 USB signal.
Add R8207 for USB30 PCIE signal.
09/06 56 U5601 add 2nd=74.02191.079.
09/06 93 PU9303 add 2nd=74.05930.03D. 09/10 49 Add TPNL1 for touch panel solution 4pin connector.
Change LCD1 to 20.F1816.030 for 30pin
09/06 37 U3701 add 2nd=73.7SZ08.DAH. Re-assign LCD1 pin define base on Roy updated cable pin define list.
09/06 23 Add 2nd and 3rd for L2301. 09/10 51 Change HDMI1 part number to 22.10296.331 from 22.10296.311 base on ME Double updated.
09/06 23 R434 change name to PR9321. Add PC9324 and PR9319 for soft start.
A <Core Design> A
09/06 61 TC6101=80.10715.B1L, 2nd=77.C1071.21L, 3rd=77.C1071.20L.

Wistron Corporation
09/06 56 ODD1 add 2nd and 3rd source. HDD1 add 3rd source. 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
09/06 49 LCD1 add 2nd source. Title
Change History
09/06 69 TPAD1 add 2nd. Size Document Number Rev
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
09/13 83 Change X8501 to 82.30034.641;2nd 82.30034.651;3rd 82.30034.681 from sourcer suggestion. 09/17 40,41 Stuff EC4002 0.1uF from EMC Neo suggestion.
Stuff EC4008 0.1uF from EMC Neo suggestion.
09/13 Change KBLIT1, PWRBTN2 and TPAD1 2nd source from 20.K0343.004 to 20.K0382.004. Stuff EC4102,EC4103 0.1uF from EMC Neo suggestion.
Stuff EC4107 0.1uF from EMC Neo suggestion.
Stuff PC4119,PC4120 0.1uF from EMC Neo suggestion.
09/13 47 Change 1.8V power solution. Stuff EC4006,EC4007 0.1uF from EMC Neo suggestion.
D D
09/14 82 Change R8201~R8203 to 470ohm from 100ohm. 09/17 60,18 EC6001 change to 10p from 4.7p and default stuff from Neo suggestion.
Add RN8209 PH 5V_S5 on MEDIA_LED1~3# for PWM OD mode. EC1801 change to 10p from 4.7p and default stuff from Neo suggestion.
09/14 40 Add 2nd source 84.04835.H37 on PU4002,PU4003 base on Brian updated 2nd source excel file. 09/17 44 default stuff EC4407,EC4405,EC4403,EC4410 base on EMC Neo suggestion.
09/14 58 Change SPK1 to 20.F0772.004 from 20.F1647.004 from Double updated. 09/17 49 Add 2nd source 20.F1561.004;3rd source 20.F1686.004 on TPNL1 from updated connector list.
09/14 51 Add R5101~R5108and reserved TR5101~TR5104 on all of HDMI differential pair for EMC suggestion. 09/17 49 Add 2nd source 20.F1561.004;3rd source 20.F1686.004 on TPNL1 from updated connector list.
Rename HDMI1 CONN NET name.
09/17 82 Change R8201~R8203 to 430ohm.
09/14 29 Add R2920,R2921 and reserved EC2901,EC2902 on AUD_DMIC_CLK &AUD_DMIC_IN0 for EMC suggestion.
09/17 48 Change PR4809 to 4.7K from 100K PH power source change to 3D3V_S0 from S5.
09/14 75 Add R7503,R7504 and reserved EC7501,EC7502 on CLK_PCIE_NEW &CLK_PCIE_NEW# for EMC suggestion.
Rename NEW1 pin24,25 to USB_PP13_R&USB_PN13_R. 09/17 40,27,83 Rename PCIE_RST# to AD_IA_HW2 on KBC GPIO50 for power Tom suggest.
Rename NEW1 pin8,9 to CLK_PCIE_NEW_C&CLK_PCIE_NEW#_C Reserved PQ4004,PR4036,PR4037 for AD_IA_HW2 function.
09/14 20 Reserved EC2004,EC2005 on CLK_PCIE_NEW &CLK_PCIE_NEW# for EMC suggestion. 09/17 68 Rename CHARGER_LED1 to CHARGERLED1.
Rename FPOWER_LED1 to FPOWERLED1.
C 09/14 49 Reserved EC4910~EC4915 on LVDS signal for EMC suggestion. Rename HDD_LED1 to HDDLED1. C
Rename TP_LOCK_LED1 to TPLOCKLED1.
Rename TP_LOCK_LED2 to TPLOCKLED2.
09/15 58 Re-assign SPK1 pin define base on Roy updated excel file for 20.F0772.004 Rename WLAN_LED1 to WLANLED1
09/15 51 Add 2nd source 22.10296.311 on HDMI1 from updated connector list. X01 09/17 21,22 Base on layout routing,Add RN2104 10K instead of R2111 10K.
Move EC_SCI#,DBC_EN to RN2201. Move S_GPIO to RN2103. Move PSW_CLR# to RN2104.
09/15 68 Add 2nd source 20.K0382.004 on PWRBTN1& PWRBTN2 base on updated connector list.
09/17 56 Change R5605 to 100K from 10K and PH to 5V_S0 from 3D3V_S0 to meet Vgs>2V turn on.
X01
09/15 82 Re-assign CRTBD1 pin define base on EMC suggestion.
09/17 56 Add Q2706 2N7002 to avoid leakage loop from 3D3V_S5 to 3D3V_AUX_KBC issue when 10mW latched fail timing.
09/15 49 Change BLON_OUT_C to pin 15 and pin 4 to NC on LCD1.
09/17 ALL Change all of 0402 0ohm to 0R0402 short pad.
PR4008,PR4010,PR4012,PR4020,PR4023,PR4024,PR4027,PR4028,PR4029,PR4225PR4102,PR4113,PR4118,
09/15 28, 51,82 Add test point for WKS AFTE request.
PR4121,PR4203,PR4204,PR4215,PR4222,PR4231,PR4243,PR4301,PR4509,PR4510,PR4801,PR4804,PR4805,
PR4808,PR4810,PR9211
09/15 All ADD 2nd source follow Power team suggestion.
F4902,PR4017,PR4018,PR4106,PR4611,PR4710,PR4807,R2304,R2403,R2406,R2409,R2702,R2902,R2903,R2904
09/15 92, 93 Modify PR9318 and PR9228 power source from 3D3V_AUX_S5 to 3D3V_S5. R2305
09/15 86 Reserve Q8602, C8603 and R8606 for VGA over temp. 09/20 9 Add 2nd for TC901.
B B
09/15 20 RN2005 swap net. 09/20 83 Add 2nd for L8303.
09/15 19 RN2005 swap net. 09/20 82 Add 2nd for LD8201.
09/15 48 Change PR4809 to 10K from 100K PH power source change to 3D3V_S0 from S5. 09/20 86 Add 2nd for Q8601.
09/15 82 Re-assign CRTBD1 pin define base on EMC suggestion. 09/20 83 Add R8321. C8353 and C8354 change to 12pF.
09/15 97 Reserved EC9701~EC9723 0.1uF for RF suggestion. 09/20 82 Redefine IOBD1.
09/15 41 Un-stuff PU4101,PD4105,PR4124, PR4125,PR4101 at X01 stage for 5mW issue. 09/20 75 AFTP111 and AFTP110 connect to USB_PP13_R and USB_PN13_R.
09/15 69 un-stuff R6907 and stuff R6905,Q6902,R6906 for 5V drive CAP LED. 09/20 51 Change P/N of Q5102.
09/17 82 Change IOBD1 part number to 20.F1849.080 base on Double updated latest DXF&EMN. 09/21 42 Change PU4201 VDD power source to 5V_S5 from 5V_S0 to avoid abnormal MVP_PWRGD waveform.
09/17 49,57 stuff TR4901 and un-stuff R4911,R4912 at X01 stage from EMC Neo suggestion. 09/21 47 stuff PC4714 22uF from Brian updated.
32,64 stuff TR4902 and un-stuff R4908,R4909 at X01 stage from EMC Neo suggestion.
stuff TR5701 and un-stuff R5718,R5719 at X01 stage from EMC Neo suggestion.
A <Core Design> A
Wistron Corporation
09/17 20 Change RN2010~RN2016 to 33ohm from 0ohm from EMC Neo suggestion. Taipei Hsien 221, Taiwan, R.O.C.
Title
09/17 37 Change R3710 to 100K from 0ohm to avoid impact 1.05VTT_PWRGD turn off sequence directly.
Change History
09/17 17 Add R1703~R1705 on RGB signal and reserved EC1701~EC1703 0.1u from EMC Neo suggestion. A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
49, 57
09/21 45 Change PR4507 to 20K from 20.5K from Brian updated. 09/27 32, 64 TR4901, TR4902, TR5701, TR3201 and TR6401 DY. Stuff 0 ohm.
09/21 46 Change PR4602 to 110K from 68K from Brian updated. 09/27 69 AFTP73 connect to TP_VDD.
09/21 42 Change PR4217 to 1.27K from 1K from Brian updated. 09/27 85 U8501 power change to 3D3V_S0.
Change PR4213 to 3.6K from 3.16K from Brian updated.
D D
Change PR4236 to 3.01K from 3.32K from Brian updated. 09/27 92 PL9201 change like CPU core power choke.
09/21 44 Change PC4410 to 0.01u from 0.022uF from Brian updated. 09/28 83, 84 L8303, L8401, L8402, L8502 and L8503 follow NV DG spec.
09/21 39 Add 2nd 83.00099.K11;3rd 83.00099.T11 on D3901,D3902,D3903 from Sourcer Eden suggestion. 09/28 46 Change PR4606 to 4.02K from 240ohm for fine tune 1.5V output Voltage.
09/21 39 Add 2nd 84.02143.011;3rd 84.00143.N11 on 6801,Q6804,Q6805,Q6806,Q6807,Q6808 09/28 92 PTC9202, PTC9203 and PTC9204 2nd=79.47719.9BL
from Sourcer Eden suggestion.
09/28 22 Change R2220 to 10K from 100K.
09/21 43 Change PU4303,PU4306,PU4309 dummy field only for QC CPU stuff.
Change PC4307,PC4316 dummy field only for QC CPU stuff.
EC6001 change to 10p from 4.7p and default un-stuff from Neo suggestion.
Add 2nd for PTC4306. 09/28 60 EC1801 change to 10p from 4.7p and default un-stuff from Neo suggestion
09/21 41 PD4101, PD4103, PD4104 and PD4105 add 2nd source.
09/21 69 Q6902 add 2nd source. 09/28 27 Change R2710, R2739, R2724 and R2726 change to 1%.
09/21 40 PD4001 add 2nd source. 09/29 27 Default mount R2756, Dummy R2734.
09/21 19 move PCH_WAKE# to RN1901 pin4;Add R1909 PH 100K on AC_PRESENT. 10/04 24 Add 2nd source 68.1001E.10N on L2401,L2402,L2403 from sourcer Renee Lee updated.
C C
09/21 37 R3710 change to 0ohm. Remove R3701 and C3701. 10/07 43 PTC4306 cahnge second source to 79.47612.60L.
X01
09/21 42 Add PR4214, PC4230, PR4216 and PC4231 from Brian updated. X01 10/09 85 Change L8503 to 68.00375.091,and add second source 68.00206.171
09/23 20 RN2016, RN2010, RN2011, RN2012, RN2014 and RN 2013 keep 0ohm. 10/09 85 Change L8502 to 68.00115.191,and add second source 68.00206.131
09/23 ALL PR9216, R504, R1812,R1813,R1815,R1817, R1903, R1906,R1910,R1912,R1913,R1924,R1925, R2213,R2219, 10/09 84 Change L8401 and L8402 to 68.00115.181,and add second source 68.00206.341
R2711,R2720,R2733,R2761, R2807,R2814, R3708, R5125, R5127, R5721, R5722.
10/09 83 Change L8303 to 68.00375.101,and add second source 68.00119.101
09/23 75 Add R7505~R7508 0ohm and reserved EC7503~EC7506 on PCIE_TX8&RX8 signal base on EMC Lance suggestion.
Add R7509,R7510 0ohm and reserved EC7507,EC7508 on CLK_PCIE_NEW_REQ#&PCIE_WAKE# signal base
on EMC Lance suggestion.
09/23 ALL RN5101, RN2201, RN1702, RN1901, RN1705 swap pin. 10/09 42 Change PR4217 to 64.84505.6DL for Dual-core OCP
09/23 79 DUMMY G-SENSOR. 10/09 42 Change PR4213 to 64.23715.6DL for Dual-core loadline
09/23 92 Update value of PR9210, PR9209 and PR9213 for N12P. 10/09 42 Change PR4207 to 64.22025.6DL for CPU(35W) Turbo setting
B B
09/23 43 PR4320 change to 4 m ohm. 10/09 42 Change PR4202 to 64.22025.6DL for GFX Turbo setting
09/23 68 Add 2nd source 83.00110.J70 on FPOWERLED1,HDDLED1,WLANLED1 from Sourcer Anya suggestion. 10/09 20,83 Dummy R2004 R2003 and PQ8309, stuff R2005
Add 2nd source 83.00326.G70 on CHARGERLED1from Sourcer Anya suggestion.
Add 2nd source 83.00190.Z70 on TPLOCKLED1,TPLOCKLED2 from Sourcer Anya suggestion. 10/19 28 Change R2817 from 107K to 124K (64.12435.6DL) for VGA temperature setting change
09/23 69 Change KBLIT1 part number to 20.K0589.004 and re-assign pin define base on Roy updated. 10/25 84 Change R8402 from 40D2R to 60D4R (64.60R45.6DL) for meeting the spec
09/23 42, 44 Add 2nd source 69.60011.201 on PR4405,PR4245 from Sourcer Kitty suggestion. 10/25 14 15 Add DM1 and DM2 second source:62.10017.Q41 and 62.10017.P61
09/23 42 Add 2nd source 69.60037.021 on PR4246,PR4247 from Sourcer Kitty suggestion. 10/25 85 Ventura SMBC_INA219_C and SMBD_INA219_C add 3.3V pull high schematic
09/24 23 Add 2nd source 68.00214.211 on L2301 updated from DN13ATI. 11/01 51 85 Change HDMI HPD schematic for cost down
09/24 68, 69 Change R6806,R6808,R6811~R6813,R6801,R6803,R6815,R6906 to 390ohm from 1K to fine tune all of MB LED X02 11/10 27 Change R2724 to 64.33025.6DL for PCB version change
for 5mA spec.
09/27 51 Reserve R5114 and R5115.

A <Core Design> A
09/27 85 Reserve R8510 and R8513.

Wistron Corporation
09/27 83 DY U8301, mount R8323. 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
09/27 92 R9206 change to 10K, PC9211 mount 0.1u. Title
Change History
09/27 93 R9312 change to 1K. Size Document Number Rev
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
11/11 14 DM2 1st change to 62.10017.P61; 2nd change to 62.10017.N41 on ST stage from ME updated connector list. 11/18 28 Rename U2801&U2804 pin 8 to THERM_SYS_SHDN#_OTZ from HERM_SYS_SHDN#.
11/11 15 DM1 1st change to 62.10017.Q41; 2nd change to 62.10017.N11 on ST stage from ME updated connector list. 11/18 20 Change X2001 to 82.30020.D41 from 82.30020.851 from Sourcer Dick updated.
11/18 23 Reserved R2308,R2309 on VCCVRM power rail.Reserved U2302 LDO circuit on VCCVRM power rail
11/11 60 U6001 1st change to 72.25Q32.A01; 2nd change to 72.25320.C01; 3rd change to 72.25P32.C01 on ST stage
D Rename USB3_PWR_ON to PCH_GPIO57. D
11/18 22 82 Add R8209,R8210 for PM_SLP_S4# and VGA_THRM to control USB3_PWR_ON
11/11 68 Change CHARGERLED1 2nd to 83.00327.D70 from Sourcer updated.
11/11 37 Change U3701 1st to 73.7SZ08.EAH;2nd to 73.01G08.L04;3rd to 73.7SZ08.DAH from 11/18 48 Change PTC4801 to 100u(77.21071.07L) from 150u from power team Brian updated
Sourcer Eason updated.
11/19 74 Add 2nd 20.I0135.001 on CARD1 from ME updated connector list.
11/11 69 Add 2nd 20.K0592.030 on KB1 from ME updated connector list.
11/19 82 Add 2nd 20.F1908.080 on IOBD1 from ME updated connector list.
11/11 82 Add 2nd 20.K0465.008 on MEDIA1 from ME updated connector list. 11/20 3 Updated PCIE ROUTING
11/11 58 Add 2nd 20.F1804.004 on SPK1 from ME updated connector list.

Change U2801,U2804,U2805 VCC power to 3D3V_DAC_S0 from 3D3V_S0.
11/20 28 Stuff R2812, un-stuff R2805
11/11 28 Add 2nd 20.F1841.003 on FAN1 from ME updated connector list.
X02
11/11 70 Add 2nd 20.F0962.010 on HALL1 from ME updated connector list.
Reserved R2308 on VCCVRM power rail.
11/20 23 Reserved U2302 LDO circuit on VCCVRM power rail.
11/11 23 Add G9091 LDO circuit for CRT DAC power to avoid monitor noise issue.
C C
Change VCCADAC power source to 3D3V_DAC_S0 from 3D3V_S0.
Set TPS51461 PWM solution dummy field for VCCSA_PWM and APL5916 LDO solution dummy field for
X02 11/20 48 VCCSA_LDO. defualt stuff VCCSA_LDO at ST stage
11/11 60 Add Q6002,R6007 fo FACTORY RTC detect function
11/11 28 ADJ&ADJ_VGA power source change to 3D3V_DAC_S0 from 3D3V_S0 to solve T8 shut down issue. 11/20 22 Rename GFX_CRB_DET to GSENSOR_DET on GPIO39.
11/20 60 Un-stuff R6007 10M.

11/11 28 Reserved G709T1UF for T8 solution sync with DN13.
11/20 82 Reserved EC8201,EC8202 0.1u(closed H3) between AGND and GND from EMC Neo suggestion.
Change R8201, R8202, R8203 from 430 ohm to 1K ohm (63.10234.1DL) for soluting media board LED
11/12 82 brightness is too light issue
11/20 82 Reserved EC8203~EC8205 470p on all of MEDIA_LED# signal from EMC Neo suggestion.
11/15 49 Add 2nd 20.F1860.030 on LCD1 from ME updated connector list. 11/20 82 Add RN8205 base on HSYNC&VSYNC report
11/15 8 Reserved C802~C804,C806,C807 10uF 0603 for power team fine tune Vcore quality 11/20 61 Removed R6101 and connect USB_PWR_EN# to U6101 pin4 directly.
11/20 22 Rename PCH_GPIO12 to RTC_DET# on GPIO12.

11/15 88 89 All of VRAM(VRAM1~VRAM8) PCB footprint change to CO-LAY type (DUMMY-BGA96D075133H48) from
90 91 BGA96D0913H48 same as DW30.
B
Reserved U6102 USB POWER related circuit to separate EATA and CRT USB power in ST build. B
61 22 Reserved USB2_CRT_ON# to control U6102 USB power switch from PCH GPIO57.
11/20 18 Reserved USB_OC#0_1 connect from PCH GPIO59.
68 Change R6813, R6906 from 390 ohm to 1K ohm (63.10234.1DL) for soluting LED
11/20 82 Reserved R8211,R8212 0ohm 0805 on CRTBD1 pin37,39 to separate EATA and CRT USB power in ST build.
Dell required us to disable PCIE port of WWAN slot ,If PCIE port 1 is disabled, it will cause all PCIE port 11/22 82 Swap RN8205 pin4,3 and pin2,1 each other base on Connie swap report.
11/15 20 disabled,so change WWAN to PCIE port 3 from port1 at ST stage.
stuff EC8201,EC8202 0.1u(closed H3) between GND and GND from EMC Neo suggestion.
11/22 82 stuff EC8206 between 3D3V_S5 and GND from EMC Neo suggestion.
11/16 97 Change HHD1 HDD4 HGPU1 HGPU2 2nd from 34.4CK01.201 to 34.4CK01.401 from ME update connector list
Change R6808, R6811 from 390 ohm to 1K ohm (64.10234.1DL) for soluting LED 11/22 23 base on layout condition change 3D3V_DAC_S0 circuit. Stuff R2301 and un-stuff L2301.
11/22 82 stuff EC8203~EC8205 470p on all of MEDIA_LED# signal from EMC Neo suggestion.
11/16 28 stuff both G709T1UF and P2800 related circuit, add R2805 0ohm default un-stuff at ST stage. 11/22 23 Removed U2302 LDO for VCCVRM.
11/17 48 CO-LAY APL5916 related circuit for VCCSA LDO solution.

<Core Design>
A A
Add G9091 LDO circuit for CRT DAC power to avoid monitor noise issue.
11/18 23 Change VCCADAC power source to 3D3V_DAC_S0 from 3D3V_S0. Wistron Corporation
Stuff R2301 and un-stuff L2301. 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Title
11/18 28 Add R2805 0hm between THERM_SYS_SHDN#_OTZ and THERM_SYS_SHDN#.
Add R2812 0ohm between THERM_SYS_SHDN# and U2805 pin3.
Change History
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
11/22 29 change R2920,R2921 to 22ohm from 0ohm and stuff EC2901,EC2902 22p from EMC Neo updated. 11/24 57 Add 2nd(22.10339.261)on ESATA1 from Karl updated.
Change U6101 to dual USB power switch from single for Layout limitation and placement. 11/24 28 un-stuff VGA P2800 related circuit from Niki confirmed.
11/22 61 Reserved USB2_CRT_ON# to control U6102 USB power switch from PCH GPIO57.
Reserved USB_OC#0_1 connect from PCH GPIO59. 11/24 64 rename C6401,C6402,C6403 to EC6401,EC6402,EC6403
D 11/22 49 stuff C4908 0.1uF from EMC Neo suggestion. D
11/24 22 Dummy R2206
X02
11/22 57 Change TR5701 to 69.10103.041 and un-stuff R5718,R5719 from EMC Neo Suggestion.
11/25 28 Dummy R2817 R2818 C2816
11/22 49 Change TR4902 CM choke to 69.10103.041 and un-stuff R4908,R4909 from EMC Neo Suggestion.
11/25 69 Add 3rd(83.00110.R70) on FPOWERLED1,HDDLED1,WLANLED1 from Anya provide

Swap TR4901 pin4,3 and pin2,1 each other base on Connie swap report.
11/22 49 Change TR4901 CM choke to 69.10103.041 and un-stuff R4911,R4912 from EMC Neo Suggestion.
11/25 69 Add 3rd(83.00192.J70) on TPLOCKLED1 and TPLOCKLED2 from Anya provide.
11/22 75 Change TR7501 CM choke to 69.10103.041 and un-stuff R7501,R7502 from EMC Neo Suggestion. 11/25 69 Add 3rd(83.01108.070) on CHARGERLED1 from Anya provide.
11/22 58 stuff EC5801~EC5804 470pF from EMC Neo suggestion.

11/26 43 92 Change PC9217 PC4319 to 0.1u 50V
11/22 9 39 stuff EC901, EC3903, EC4501, EC4909, EC4907 0.1uF from EMC Neo suggestion.
45 49
11/29 83 Change C8353 C8354 to 15PF ,R8320 stuff from vendor suggestion.
C 11/22 49 Change RN4901 to 100ohm 4p from 8p for improve layout place. C
11/29 36 Stuff D3602

X02
11/22 48 Updated VCCSA_LDO circuit from Power team Brian updated.
11/22 83 84 85 Change L8301 L8401 L8402 to 0 ohm resistor (63.00000.00L) 11/30 68 Change 2nd source to 83.00322.070 from 83.00110.J70
11/22 60 stuff R6007 10M. 11/30 85 Change L8502 L8503 to 0 ohm
11/30 92 Stuff PR9237 DY PR9321

11/23 49 57 75 SWAPTR4901 TR4902 TR5701 TR7501 pin1&4 and pin2&3 each other base on Connie swap report.
12/01 8 Change C837,C826 to 22uF from 10uF and default stuff from Power Brian updated.
11/23 60 Change U6101 1st(74.02182.071);2nd(74.00546.A7D);3rd(74.02062.079) from Sourcer Harrison suggestion. 12/01 8 Change C801~C807 and C817 10uF stuff at QC CONFIG from power Brian updated.
11/23 64 Add C6402 0.1uF,C6403 180pF and stuff C6401 47pF from RF fine tune result. 12/21 ALL Change 0402 pad(ZZ.00PAD.M11): R1404 R1405 R1503 R1504 R1703 R1704 R1705 R1807 R2301 R2306
R2307 R2308 R2404 R2405 R2735 R2737 R2758 R2759 R2760 R2762 R3614 R3710 R5114 R5801
R5802 R5803 R5804 R8210 R8323 R8511 R8512
11/23 57 49 75 Change R5718,R5719,R4908,R4909,4911,R4912,R7501,R7502 to 0ohm 0603 from 0402.
B B
12/21 82 Change 0603 pad(ZZ.00PAD.M21): R8206 R8207
12/21 17 20 Change resistor pad(ZZ.0R04P.ZZZ): RN1704 RN2010 RN2011 RN2012 RN2013 RN2014 RN2015 RN2016
stuff EC9739,EC9737,EC9735 47pF from RF fine tune result.
11/23 56 97 stuff EC5601 180pF from RF fine tune result.
Stuff EC9738 0.22uF closed EC9739 from RF fine tune result.
12/21 83 84 85 Change L8301, L8401,L8402,L8502,L8503 to 0R0603 pad(ZZ.00PAD.M21)
11/23 97 stuff ECEC9729,EC9730 470pF from EMC Neo suggestion. Change to Parallel resistor
12/21 ALL R1501 ,R1502; R2739 ,R2774;R8202 ,R8203;R8501 ,R8502;R8506 ,R8507;R2123 ,R2124
A00
11/23 45 Change PR4501 to 75K from 45.3K for 1.05V OCP set to 20A from Brian. 12/21 82 RN8205 change to R8201, R8202
12/21 93 PR9237 rename to PR9337

11/23 82 Removed R8211,R8212 and connect 5V_USB2_S3 to CRTBD1 pin 37 directly.
12/21 56 61 68 Delete 77.C1071.21L(TC6101), delete 83.01108.070(CHARGERLED) , delete 62.10065.121(HDD1)

11/23 61 Removed C6105,C6103.
11/23 69 70 Change AFTP 80 81 to AFTP 83 84; change AFTP 83 to AFTP82; change AFTP 82 to AFTP85.
A <Core Design> A
11/24 20 Add 2nd(82.30020.G71);3rd(82.30020.G61) on X2001 from Sourcer Dick updated. Wistron Corporation
Title
11/24 69 Add 2nd(20.K0613.004)on KBLIT1 from Karl updated.
Change History
A3
QUEEN 15 A00
5 4 3 2 1
5 4 3 2 1
12/22 27 R2724 change to 47K resistor for XBulid 12/28 27 Change R2756, R2763, R2766 to short pad
12/22 27 R2301 change to 0 resistor for CRT debug 12/28 36 Stuff Q3603
1.Change PR4032,PR4034,PR4037 to ZZ.00PAD.M11 12/28 28 86 Cancel VGA Thermal sensor P2800 ciruit
12/22 40 2.Stuff PQ4003,PQ4004
D 3.Change PR4047 to 174K(64.17435.6DL) D
4.Change PR4035 to 300K(64.30035.6DL) 12/28 27 28 82 Change to VGA_THRM to USB3_PWR_ON
5.Change PR4036 t0 76.8K(64.76825.6DL)
6.Change PR4031 to 150K(64.15035.6DL) 12/28 23 Change R2301 to short pad
1.FPOWERLED1 rename to FPLED1

2.HDDLED1 rename to HDLED1 12/29 51 Change HDMI resistor to short pad
3.CHARGERLED1 renamtpe to CHLED1
12/23 68 4.WLANLED1 rename to WLED1
12/29 49,57,75 Delete USB DUMMY resistor for no-lay
5.TPLOCKLED2 rename to TPLED2
6.TPLOCKLED1 rename to TPLED1
7.PWRBTN1 rename to PWRBT1 12/29 32 Change USB 0 resistor to short pad for no-lay
8.PWRBTN2 rename to PWRBT2
12/29 5 Reserve EC502 ,EC504 for EMI suggestion,add DUMMY EC505 for EMI
Delete PR4323,PR4324,PR4325;
12/23 43 Stuff PR4320 for all BOM ,not co-lay Ventura
12/29 82 Delete PM_SLP_S4# line, directly link to USB3_PWR_ON

Delete PR9220,PR9222,PR9223;
12/23 92 Stuff PR9217 for all BOM ,not co-lay Ventura
C C
12/23 51 Change 5V_HDMI to 5V_CRT_S0_R for HDMI power leakage 12/29 23 Add 3rd Richtek(74.09198.G7F) on U2301 at XBuild batch run config
PRN3901 rename to PN3901 12/29 68 Not use Liteon LED(83.00322.070) for package
PTC9202~04 rename to PT9202~04
PTC4301~04 rename to PT4301~04
PTC4306 rename to PT4306 12/30 5 Add DUMMY diode EC506 for BUF_CPU_RST# as EMI suggestion
12/24 All PTC4308~09 rename to PT4308~09
PTC4401~03 rename to PT4401~03 12/30 42 PC4227 change to 78.33420.5FL as 78.33423.5FL obsoleted
A00 PTC4502 rename to PT4502
PTC4602 rename to PT4602 A00 12/30 49 Change R4904 to short pad
PTC4102 rename to PT4102
PTC4104 rename to PT4104 12/31 86 Add probe point for P2800_VGA_DXN/P2800_VGA_DXP
12/24 28 Change U2802 3rdto 74.05606.A71 at X-Build batch run 01/03 68 Change TPLED1,2 1st to 83.01921.P70 ,2nd to 83.00190.S7A,3rd to 83.00191.H70;
R6813 change to 390R from 1K same as DN13 LED part.
12/24 82 Change RN8205 to 66.22036.04L from 66.22036.040at X-Build stage

B
01/03 49 Delete R4908, R4909 for USB_Camera not co-lay B
12/24 82 Reserved R8211 0603 0ohm on F8201 01/03 4~10 Add 3rd foxconn(62.10055.321) on CPU1 at X-Build batch run config
01/03 82 Add 3rd T-conn(20.F1932.040) on CRTDB1at X-Build batch run config

12/24 36 Reserved Q3603 2N702 on IMVP_PWRGD to fine tune glitch waveform when AC lose and DC lose.
01/03 97 Add 3rd LIDON(34.4CK01.501) on HHD1,HHD4,HGPU1,HGPU2 at X-Build batch run config
12/24 28 Change 3D3V_S0 to 3D3V_DAC_S0

01/04 68 Delete 83.00191.H70 for TPLED1,2 as cost high
Change to short pad: 01/04 49,57,75 Add 2nd TAI-TECH(69.10084.071) on TR4901,TR4902,TR5701,TR7501 at X-Build batch run config
12/24 45 46 93 PR4502,PR4607,PR9311,PR9312,PR9326.
DUMMY PC4501
12/27 28 If stuff P2800EA1 then must stuff R2803,R2804,C2805 but if stuff P28003B0 should be unstuff.
<Core Design>
12/27 42 PR4207,PR4213,PR4217 DUMMY field set to DC&QC option
A
Wistron Corporation A

12/28 51 Change 5V_HDMI to 5V_CRT_S0_R on RN5101 Taipei Hsien 221, Taiwan, R.O.C.
Title
Change History
12/28 28 Un-stuff U2805 G709T1UF related circuit and R2812 then stuff R2805 at XBuild Size Document Number Rev
A3
QUEEN 15 A00
5 4 3 2 1

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Discrete/UMA Schematics Document

OPTIMUS:OPTIMUS solution installed.

(Discrete/UMA co-lay) 1D05V_VTT 0D85V_S0 DCBATOUT

WKS P/N:72.41164.I0U SAMSUNG

DDR3 Revision : A00 SYSTEM DC/DC

SATA x 2 INPUTS OUTPUTS

Internal Digital MIC

LANE3 Mini Card2(WWAN) 5 CARD READER

PCI EXPRESS* - GRAPHICS

AN33 R8 4K99R2F-L-GP SM_DRAMRST# 37

JTAG & BPM

BPM#5 TP508 TPAD14-GP

R509 AR32 XDP_BPM7 1

SANDY SKT-BGA989C470395-1H180 0630 Modify:

A00 1230 EMI 62.10055.421 Removed XDP1101 connector

19 XDP_DBRESET# XDP_DBRESET# 1 2 R516

A00 1229 EMI

DDR SYSTEM MEMORY B

M_A_DQ33 SA_DQ32 SA_ODT3 M_B_DQ33 SB_DQ32 SB_ODT3

SSID = CPU CFG2

RSVD#G25 RSVD#AK32 R705

PEG AND DDR

AC26 VCC VCCIO A12

AA35 VCC VCCIO A11

V33 VCC VIDSCLK AJ30 H_CPU_SVIDCLK 42

V32 VCC VIDSOUT AJ28 H_CPU_SVIDDAT 42

0819 De-cap VCC

VAXG Output Decoupling Recommendation:

DDR3 -1.5V RAILS

PROCESSOR VCCPLL: 1.2A VCCUSA_SENSE

VCCPLL Output Decoupling Recommendation:

AT35 VSS VSS AJ22

M_B_A12 A11 CKE1 SA1_DIM1

M_B_DQ10 33 198 3D3V_S0

M_B_DQ19 53 125 1D5V_S3

M_B_DQ22 DQ21 VDD1

M_B_DQ51 177 32 0818

M_B_DQ52 164 37 De-cap

B M_B_DQ56 DQ55 VSS B

M_VREF_CA_DIMM0,M_VREF_CA_DIMM1 M_A_DQ5 6 187

M_A_DQ10 DQ9 3D3V_S0

M_A_DQ31 70 105 1D5V_S3

M_A_DQ43 DQ42 VSS

M_A_DQS#1 DQS0# VSS

SRN2K2J-1-GP 49 L_BKLT_CTRL P45 L_BKLTCTL

Digital Display Interface

gate logic IC U1801/C1802. 0628 Modify:

0908 X01 Modify: KBC CLK EMI RN1802

Reseved R1816 100K 0402 on PLT_RST#. R1818 10KR2J-3-GP USB_OC#0_1 4 7 USB_OC#10_11

SSID = PCH 4 DMI_RXN[3:0]

System Power Management

27 SUS_PW R_ACK K16 SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# F4 PM_SLP_S3# 27,36,37,47,75 RTC_AUX_S5

27 PM_PW RBTN# E20 G10 PM_SLP_A# 1

27,86 AC_PRESENT H20 G16 PM_SLP_SUS# 1

PM_RI# A10 K14 PM_SLP_LAN# 1

CEKLT: 10K 0625 Modify:

SSID = PCH 3D3V_S50705 Modify:

CLKOUTFLEX2/GPIO66 H47 2 CLK_27M_VGA 83

&CLK_PCIE_NEW# for EMC suggestion. 0717 Modify:

1 4 RTC_X1 A20 C38 LPC_AD0

TPAD14-GP TP2101 PCH_JTAG_TCK_BUF