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SequentialLogic

Problem1.Considerthefollowingdiagramofasimplesequentialcircuit:

ThecomponentslabeledCL1andCL2arecombinationalR1andR2areDregisters.Timingparametersfor
eachcomponentareasnoted.

A.Writethetimingspecifications(tS,tH,tCD,tPD,tCLK)forthesystemasawholeusingthetiming
specificationsfortheinternalcomponentsthataregiveninthefigure.

It'sagoodideatocheckifthecircuitwillworkforanyclockperiod.Wecheckthisbycheckingifthe
totalcontaminationdelayfromR1toR2islongenoughtocovertheholdtimeofR2.Inotherwords,

tH,R2<=tCD,R1+tCD,CL2
2<=1+1
2<=2

Theinequalityissatisfied,sowecandeterminethetimingspecificationsofthesystem.

Thesetuptimeandholdtimeofthesystemisdeterminedbythesetuptimeandholdtimerequiredforthe
signalIN,whichistheinputtoCL1.Thus,

tS=tPD,CL1+tS,R1=6,and
tH=tH,R1tCD,CL1=1.

Thecontaminationandpropagationdelayofthesystemisdeterminedbythecontaminationand
propagationdelayofthesignalOUT,whichistheoutputofregisterR2.Thus,

tCD=tCD,R2=2,and
tPD=tPD,R2=8.

TheclockperiodforthesystemisdeterminedbyaddingallthepropagationdelaysfromR1toR2,andthe
setuptimeforR2.

tCLK>=tPD,R1+tPD,CL2+tS,R2
tCLK>=2+5+4
tCLK>=11

B.SupposeyouhadavailableafasterversionofCL2havingapropagationdelayof3andacontamination
delayofzero.CouldyousubstitutethefasterCL2fortheoneshowninthediagram?Explain.
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We'vebeentreatingwiresasidealizedcomponentsthatintroducenodelayoftheirown.Intherealworld,wires
haveresistance,capacitanceandinductancethatwillcausedifferentfrequenciestopropagatealongthewireat
differentrates.Thismeansthatwireswilldelaythearrivalofsharprisingandfallingtransitions(whichyou'll
rememberfromFourieranalysishavesignalcomponentsatmanydifferentfrequencies).Thiseffectis
particularlybothersomeinconnectionwithclocksignalssincetheclockmayarriveatseparatepartsofthe
circuitatslightlydifferenttimes.Thisdifferenceinarrivaltimesoftheclockiscalledclockskew,whichwe'll
modelinoursimplecircuitaboveasexplicitdelaysalongeachclockpath:

C.Rewritethetimingspecificationsforthesystemasawholetakingintoaccountd1andd2.Don'tmakeany
assumptionabouttherelativesizesofthetwodelays.

Thedelayd1causesalltimingspecificationsassociatedwithregisterR1tobeshiftedlaterintimebyd1.
Likewisethedelayd2causesalltimingspecificationsassociatedwithregisterR2tobeshiftedlaterin
timebyd2.Notethatwestillusetheoriginalclocksignalasourreferenceforthesystem,sothesetup
timesfortheregistersR1andR2becomeshorterbyd1andd2,respectively,andtheholdtimesforR1
andR2becomelongerbyd1andd2.

Thetimingspecificationsofthesystem,takingd1andd2intoaccount,are:

tS=tPD,CL1+tS,R1d1=6d1
tH=tH,R1tCD,CL1+d1=1+d1
tCD=tCD,R2+d2=2+d2
tPD=tPD,R2+d2=8+d2

Finally,

tCLK>=tPD,R1+tPD,CL2+tS,R2
tCLK>=2+d1+5+4d2
tCLK>=11+d1d2

D.Therelativeclockskew(d2d1)betweentworegistersconnectedina"pipeline"wheretheoutputofthe
firstregisterisconnected,usuallythroughlogic,totheinputofthesecondregistercanalsoaffectthe
designofacircuit.Explainhowrelativeclockskewaffectsthemaximumclockfrequencyofthecircuit
shownabove.Rememberthattherelativeskewmightbepositiveornegative.

Asshowninpart(C),tCLK>=11(d2d1),rewrittentoshowtherelativeclockskewterm.

Onecanseethatastherelativeclockskewbecomespositive,themaximumclockfrequencyincreases.
Conversely,astherelativeclockskewbecomesnegative,themaximumclockfrequencydecreases.

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E.[Whyclockskewkeepsintegratedcircuitdesignersawakeatnight.]Ifd2>d1,thecircuitshownabove
willnotoperatecorrectly.Explainwhy.WillchangingthefrequencyofCLKsolvetheproblem?Whyor
whynot?

F.Suggestawayforthedesignertochangehiscircuittoguaranteecorrectoperationgivenanupperbound,
tskew>abs(d2d1),onthemaximumrelativeclockskew.Assumethatthetimingparametersofthe
registerscannotbeadjusted.

Problem2.Considerthefollowingcircuitdiagram:S0andS1:

A.Whatisthesmallestclockperiodforwhichthecircuitstilloperatescorrectly?

B.Asharpeyedstudentsuggestsoptimizingthecircuitbyremovingthepairofinvertersandconnectingthe
QoutputoftheleftregisterdirectlytotheDinputoftherightregister.Iftheclockperiodcouldbe
adjustedappropriately,wouldtheoptimizedcircuitoperatecorrectly?Ifyes,explaintheadjustmenttothe
clockperiodthatwouldbeneeded.

C.WhentheRESETsignalissetto"1"forseveralcycles,whatvaluesareloadedintotheregisters?(Give
valuesforS0andS1.)

D.AssumingtheRESETsignalhasbeensetto"0"andwillstaythatway,whatvaluewillwiththeregisters
haveafterthenextclockedgeassumingthecurrentvaluesareS0=1andS1=1?

E.NowsupposethereisskewintheCLKsignalsuchthattherisingedgeofCLKalwaysarrivesattheleft
registerexactly1nsbeforeitarrivesattherightregister.Whatisthesmallestclockperiodforwhichthe
FSMstilloperatescorrectly?

Problem3.Apossibleimplementationofasequentialcircuitwithoneinputandoneoutputisshownbelow.

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A.WhatisthesmallestvaluefortheROM'scontaminationdelaythatensuresthenecessarytiming
specificationsaremet?

B.AssumethattheROM'stCD=3ns.Whatisthesmallestclockperiodthatensuresthatthenecessary
timingspecificationsaremet.

Problem4.ThefollowingschematichastwoDregistersandtwoblocksofcombinationallogicwiththe
indicatedtimingspecifications.Assumethattheregistersandthattheclockhaszeroriseandfalltime.

A.Assumingthattheclockperiodis25ns,whatisthemaximumsetuptimefortheregistersforwhichthis
circuitwilloperatecorrectly?

B.Assumingthattheclockperiodis25ns,whatisthemaximumholdtimefortheregistersforwhichthis
circuitwilloperatecorrectly?

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Problem5.Usethefollowingcircuitinansweringthequestionsbelow.

EachoftheedgetriggeredDflipflopshasasetuptimeoftS,aholdtimeoftH,apropagationdelayoftPDand
acontaminationdelayoftCD.AssumethatINisstabletSbeforetherisingedgeofCLKandtHaftertherising
edgeofCLK.

A.InorderforthecircuitshownabovetooperatecorrectlywhatconstraintsontHandtSarenecessary?
ExpressthemintermsoftCD,tPDandtheclockperiod.

B.Whatistheminimumclockperiodatwhichthiscircuitcanbeclockedandstillbeguaranteedtowork?
ExpressyouranswerintermsoftH,tS,tCDandtPD.Assumethattimingconstraintsthatdonotdepend
ontheclockperiodaremet.

C.ForjustthisquestionsupposethereisskewintheCLKsignalsuchthattherisingedgeofCLKarrivesat
theflipfloplabeledF11nsbeforeitarrivesattheotherthreeflipflops.Assumethatholdtimesarenot
violated.Howdoesthischangetheminimumclockperiodatwhichthecircuitabovecanbeclockedand
stillbeguaranteedtowork?

D.Considerthefollowingwaveformplotforthecircuitabove.AssumethatINisstabletSbeforetherising
edgeofCLKandtHaftertherisingedgeofCLKandthattimeTismorethantPDafterthepreceding
risingedgeofCLK.

WhatisthevalueofOUTattimeT?

Problem6.Considerthefollowingtwowaveforms,oneofwhichhas1/6ththefrequencyoftheother.

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A.WriteaVerilogmodulethattakesthetopwaveformasaninputandproducesthebottomwaveformasan
output.

Problem7.Thefigurebelowshowsa4bitsynchronousbinarycounter:

I/O Description
D[3:0] 4bitdatainput
whenLDisasserted,loadD[3:0]intothecounter
LD
atthenextrisingedgeofCLK
whenENisasserted,thecounterincrementsby
EN oneatthenextrisingedgeofCLK.IfLDis
asserted,theloadtakesprecedence.
CLK clockinput
Q[3:0] 4bitcounteroutput

A.WriteaVerilogmodulethatimplementsthe4bitsynchronousbinarycounter.

B.Addanasynchronousclearinput,CLR,toyourVerilogmodule.Whenasserteditshouldimmediately(not
waitinguntilthenextclockedge)setthecounterto0.

Problem8.ThefigureandtruthtablebelowdescribeapositiveedgetriggeredJKflipflopwithactivelow
asynchronouspresetandclear.

Inputs Outputs
preset clear clk J K Q Qbar
0 X X X X 1 0
1 0 X X X 0 1
1 1 noedge X X Q Qbar

1 1 0 0 Q Qbar

1 1 1 0 1 0

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1 1 0 1 0 1

1 1 1 1 toggle

A.WriteaVerilogmodulethatimplementstheJKflipflopdescribedabove.

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