EE348 - Introduction to Logic Design

2013-2014 Spring

Hardware Description
Languages & Verilog HDL

Gkhan Koray GLTEKN

21.04.2014

Conventional Digital Design

Schematic based description

Schematic is not self explaining

Time consuming design cycle

Not easy to handle large projects

Hard to modify designs

Hard to debug
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 Conventional Digital Design Steps

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1. Determine inputs,
outputs and states

2. Build truth table

Conventional Digital Design Steps

4. Optimize function using a

method like Karnaugh map

5. Derive combinational logic

equation

6. Draw logic circuit diagram

7. Implement using
discrete logic gate
ICs(74series)
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 FPGA
Field Programmable Gate Array
An IC that includes millions of programmable logic gates.
Can be programmed using :
- Schematic logic diagram
- Hardware description languages (VHDL, Verilog)

HDLs

HDL is NOT a software programming language!

It is a Hardware Description Language

Describes a logic circuit in a textual form.

Verilog and VHDL are the two most popular HDLs.

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 The Purpose of HDLs

Simplify design representation so you can

concentrate on the overall picture

HDL allows description in language rather than

schematic, speeding up development time

Allows reuse of components (standard cells i.e.

libraries)

VHDL or Verilog?

Verilog is very C-like and liked by

electrical and computer engineers as
most learn the C language in university.

VHDL(Very High Speed Integrated

Circuit HDL) is very ADA-like and most
engineers have no experience with ADA.

Verilog is used extensively in the South-

East Asia, India and America while
VHDL is used mostly in Europe.

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 Verilog Syntax

There are about 100 keywords which are written

with lowercase letters.

i.e. if/else, and, or, input, output, wire, module

Case sensitive: Button1 is different than button1

Every line ends with a semicolon;

//Line comment, /* Block comment */

Abstraction Levels

Gate Level: Data Flow Level:

Behavioral Level:

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 Gate Level Description

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Gate Level Description

Underlying Method: Specify inputs/outputs,

gates and how they are connected to each other:

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 Verilog - Modules

Not in our scope now

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Gate Level Description - Example1

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 Three-State Gates

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Gate Level Description - Example3

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 Verilog Data Representation

1. Logic:
0 represent a logic 0 or false condition
1 represent a logic 1 or true condition
Z Output of an undriven tri-state driver High-Z value
x Models when un-initialized or unknown logic value
Initial state of registers

Output of a gate with z inputs

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Verilog Data Representation

2. Number:
Ex: 8b1111_0000
8hF0
8d
Format: <size><base_format><number>
<size> - decimal specification of bits count
<base_format> - ' followed by arithmetic base of number
d or D decimal (default if no base
format given)
h or H hexadecimal
o or O octal
b or B binary
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 Gate Level Description - Example2

A B enable

D0

D1

D2

D3

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UDP (User Defined Primitive)

// An example UDP: My NAND Gate

primitive my_NAND(F,A,B);
output F;
input A,B;
wire and_out;

and A1(and_out,A,B);
not N1(F,and_out);
endprimitive

// AND from my_NAND:

module Circuit_with_my_NAND(Out,A1,A2);
wire w1;
my_NAND (w1,A1,A2);
not (Out,w1);
endmodule
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 Data Flow Level Description
Data flow modelling is used for describing the Boolean
equations of logic circuits.
The following operators are used to describe functions:

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Data Flow Level Description - Example1

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Data Flow Level Description - Example2

A B enable

D0

D1

D2

D3

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Data Flow Level Description - Example3

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Data Flow Level Description - Example4
1bit comparator

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Data Flow Level Description - Example4

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 Behavioural Description &Always Blocks

always block executes always.

The @ symbol indicates that the block will be
triggered "at" the condition in parenthesis.
// C analogy:
while(1)
{
if(condition)
//Demonstrates the use of always block: do operation
module always_and_gate(Out,A,B); }

always @ (A,B) // if A or B changes, then execute the following:

begin
Out = A & B; Sensitivity List
end

endmodule 27

Always Block if else & case

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Behavioral Description Example1

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Behavioral Description Example2

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 wire vs reg

wire
reg
 Represents a wire.  Represents a register
 Cannot store a value. (DFF).
 Used for connection of  Can store value.
blocks and/or registers.  Use reg in sequential
 Use wire in circuits.
combinational circuits.

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Blocking vs Non-Blocking

Blocking Non-blocking

<variable> = <statement>
<variable> <= <statement>

Similar to C code
The inputs are stored once

the procedure is triggered

The next assignment waits
until the present one is
Statements are executed in
finished parallel

Used for combinational
Used for flip-flops, latches

logic and registers (sequential
circuits)

Do not mix both assignments in

one procedure
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 Blocking vs Non-Blocking

Initially assume:
A = 3; B = 5;

Finally becomes: Finally becomes:

A = 3; A = 3;
B = 3; B = 3;
C = 4; C = 6;
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Behavioral Description Example3

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Behavioral Description Example4

Clock

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Behavioral Description Example5

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 Verilog Homework
1. Design a combinational circuit whose output is equal to one if the 4
bits input have more 1s than 0s and output should be zero if the
number of 0s are more than the number of 1s. If the number of 1s
are equal to the number of zeros (2 ones, 2 zeros) than the output
should be High-Z.
a. Design the circuit and write the logic function. (20p)
b. Write a module using the data flow description of the circuit. (use vector
representation for signals that are larger than 1 bit) (20p)
c. Write a module using the behavioral description of the circuit. (20p)
2. Using Verilogger simulator (You can download evaluation version from
http://www.megafileupload.com/en/file/521307/Verilogger-setup-rar.html or
http://speedy.sh/KfHKW/Verilogger-setup.rar or
http://www.fileswap.com/dl/gNDSK8MOCh );
a. Generate a test waveform that applies 4 bits input values of all
combinations(0000 to 1111).
b. Simulate the verilog codes you have written in part1(each of the data flow
and behavioral descriptions) using the test waveform. Plot the input/output
waveforms you obtained. (20p+20p) 37

References:
1. Digital Design, Mano and Kime, 4th edition.
2. IEEE Standard Description Language Based on the
Verilog(TM) Hardware Description Language.
3. Synopsys, FPGA Compiler II/FPGA Express: Verilog HDL
Reference Manual, Version 1999.05, May 1999.
4. Smith, D. R., and P. D. Franzon, Verilog Styles for Synthesis
of Digital Systems, Prentice Hall, 2000.
5. Ciletti, Michael D., Modeling, Synthesis, and Rapid
Prototyping with the Verilog DHL, Prentice Hall, 1999.
6. http://www.wikipedia.org/

Questions ? 38

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