8.

Asynchronous Sequential Logic 8-1

Chapter 8. Asynchronous Sequential

Logic (Brief Introduction)

Introduction

✯ An asynchronous sequential circuit is a sequential circuit whose behavior de-

pends only on the order in which its input signals change and can be affected
at any instant of time.
✩ In addition to the FFs, a register may have combinational gates that con-
trol when and how new information is transferred into the register.

x1


n x z1


mz

input Combinational output

Logic

y1


k y Y1


k Y

state excitation
Delay

Figure 1: Asynchronous sequential circuit model.

 x=( 1 2
x ; x ; : : : ; xn ) : n input variables
 z=( 1 2
z ; z ; : : : ; zm ) : m output variables
 y=( 1 2y ; y ; : : : ; yk ) : k state variables (present state)
 Y=( 1 2Y ; Y ; : : : ; Yk ) : k excitation variables (next state)

☞ State transition occurs when there is an input change (no clock pulses).

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
8. Asynchronous Sequential Logic 8-2

☞ Memory (delay) elements are either latches (unclocked) or time-delay ele-

ments (instead of clocked FFs as in a synchronous sequential circuit).
☞ An asynchronous sequential circuit quite often resembles a combinational
circuit with feedback.
☞ Faster and often cheaper than synchronous ones, but more difficult to design,
verify, or test (due to possible timing problems involved in the feedback path).

✯ Steady-state condition: 8 i = 1; 2; : : : ; k; yi (t) = Yi (t)

✩ To ensure proper operation, simultaneous changes of 2 or more input

variables are usually prohibited.
✯ Fundamental-mode operation: only one input variable can change at any
time, and the time between 2 input changes must be longer than the time
it takes the circuit to reach a stable state.

Analysis Procedure
The analysis consists of obtaining a table or a diagram that describes the sequence
of internal states and outputs as a function of changes in the input variables.

1. Determine all feedback loops.

2. Designate each feedback-loop output with Yi and its corresponding input with
yi for i = 1; : : : ; k , where k is the number of feedback loops.

3. Derive the boolean functions for all Y ’s.

4. Plot the transition table from the equations.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
8. Asynchronous Sequential Logic 8-3

ysub1

x
.. Y sub1
ysub1ysub2
0 1
x

00 00 01

ysub2
. 01 11 01
11 11 10
Y sub2
10 00 10
Transition table

Excitation variables: Y1 and Y2

Secondary variables: y1 and y2

Y1 = xy1 + x y2
0 0

Y2 = xy1 + x y2

☞ The delay associated with each feedback loop is obtained from the propaga-
tion delay between each y input and its corresponding Y output.
☞ In an asynchronous sequential circuit, the internal state can change immedi-
ately after a change in the input.

✯ Total state: internal state + input value.

✯ Flow table: a transition table in which states are named by letter symbols
instead of specific binary values.
✩ The flow table also includes the output values of the circuit for each
stable state.
✯ Primitive flow table: one that has only one stable state in each row.
✩ To obtain the circuit described by a flow table, it is necessary to assign
to each state a distinct binary value, which converts the flow table into a
transition table.
✯ Race condition: when 2 or more binary state variables change value in re-
sponse to a change in an input variable.

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
8. Asynchronous Sequential Logic 8-4

✩ May cause the state variables to change in an unpredictable manner.

✯ Noncritical race: final stable state does not depend on the order in which the
state variables change.
✯ Critical race: final stable state depends on the order in which the state vari-
ables change.
✩ For proper operation, critical races must be avoided.
✩ Races may be avoided by making a proper state assignment.
✩ Races can be avoided by directing the circuit through intermediate un-
stable states with a unique state-variable change.

Design Procedure

1. Obtain a primitive flow table.

2. Reduce the flow table.
3. Assign binary state variables to obtain the transition table.
4. Assign output values to the dashes to obtain the output maps.
5. Simplify the excitation and output functions.
6. Draw the logic diagram.

We will design a gated latch circuit with 2 inputs, G (gate) and D (data), and one
output, Q. The binary value at the D input is transferred to the Q output when and
only when G = 1. When G falls to 0, the latch retains the value at the Q output,
which does not change even if D changes.
The table of total states and the corresponding primitive flow table is shown below.
Note that both inputs are not allowed to change simultaneously ( ; entries in
the table).

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
8. Asynchronous Sequential Logic 8-5

State Inputs Output Comments DG

D G Q
00 01 11 10
= a; 0
a
0 1 0 D Q a c; b; ;

b
1 1 1 D = Q b ; a; b; 1 e;

c
0 0 0 After a or d c c; 0 a; ; d;

d
1 0 0 After c d c; ; b; d; 0

e
1 0 1 After b or f e f; ; b; e; 1

f
0 0 1 After e f f; 1 a; ; e;

states to be merged
Table of Total States Primitive Flow Table

The next step is to reduce the primitive flow table, which is shown below. Then,
DG DG

00 01 11 10 00 01 11 10

a; c; d c; 0 a; 0 b; d; 0 a a; 0 a; 0 b; a; 0

b; e; f f; 1 a; b; 1 e; 1 b b; 1 a; b; 1 b; 1

following state assignment, we convert the flow table into a transition table (by
assigning a = 0 and b = 1). From the table, the simplified O/P function (Q) and
the excitation function (Y ) with respect to D, G, and y can be derived using the
K-map method. Note that the don’t-cares are assigned such that Q = Y .
0

Y = DG + G y; Q = Y:

Y
G

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005