Reg. No.

136 S 42
FOUR YEAR B.TECH. DEGREE EXAMINATION _ APRIT,, 2016.

SIXTH SEMESTER EXAMINATION

ELECTRONICS AND COMMUNICATION ENGINEERING

DIGITAI, SYSTEM DESIGN USING HDL (HDL)

(scHEME - 2013)

Time: 3 Hours Max. Marhs: 70

Question No. 1 is compulsory and it must be answered first in sequence at

one place only.
Answer any FOUR from the remaining.

Question No. 1 carries 10 marks and remaining questions carry 15 marks each.
(10x1=10)

1. (a) Define extended identifier in VHDL.

(b) Give the advantages of VHDL over high level languages.
(c) Define concussent sigiral assignment statement.
(d) What is a dataflow modeiing?
(e) What is the purpose of wait statement?
(0 List out different types of component instantiations.
(g) Give the importance of process statement.
(h) Compare std-logic and BIT data type.
(r) Write the syntax of user defined data type.
0) Define "procedure" in VHDI ).

2. (a) Explain the following with VHDL constructs (8)

(i) Entity
(ii) Architecture body
(iii) Package body declaration
(iv) Configuration d"eclaration
(b) Write a VHDL cod.e for the design of 8 x 3 encoder in data-flow model. (7)

Turn Over
3. (a) Discuss different operators in VHDL. (8)

(b) Write a VHDL code for 3 bit subtractor in dataflow model. {7)

4. (a) Give the brief explanation for the following statements (8)

(i) NuIl statement (iil Exit statement

(ii1) Assertion statement (iv) Report statement
(b) Develop VHDL cocte for the design of 4-bit shift register in structural
(7)
model.
5. (a) Design J-K flip-flop and. d.evelop VHDL code in behavioural model' (8)

(b) Write a VHDL Code for 4-bit asynchronous counter in structwal model' (7)

6. (a) I)iscuss the function usage in VHDL with one example' (8)

(b) I)evelop the test bench for T-flip'flop in YHDL' (7)

(a) (7)
7. Explain the concept of Mode FSM with example'
(8)
(b) I)esign a 4-bit ALU using \T{DL language.

136 s 42