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Digital VLSI Testing

Introduction
Lecture 1

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I t d ti to
Introduction t VLSI Testing
T ti

Q Introduction
Q T ti During
Testing D i VLSI LifeLif Cycle
C l
Q Test Generation
Q Fault Models
Q Levels of Abstraction
Q Overview of Test Technology

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I t d ti
Introduction
Q Integrated Circuits (ICs) have
grown in size and complexity 1.E+09
since the late 1950s 1.E+08
Small Scale Integration (SSI) 1.E+07

Number of Traansistors
Medium Scale Integration (MSI) 1.E+06
g Scale Integration
Large g ((LSI)) 1 E+05
1.E+05
Very Large Scale Integration 1.E+04
(VLSI)
1.E+03 VLSI
Q Moore s Law: scale of ICs
Moores 1.E+02
doubles every 18 months M LSI
S
1.E+01 S S
Growing size and complexity I I
1 E+00
1.E+00
poses many andd new testing
i
1960s 1970s 1980s 1990s 2000s
challenges

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I
Importance
t off Testing
T ti
Q Moore s Law results from decreasing feature
Moores
size (dimensions)
from 10s of m to 10s of nm for transistors and
interconnecting wires
Q Operating frequencies have increased from
100KHz to several GHz
Q Decreasing feature size increases probability
of defects during manufacturing process
A single faulty transistor or wire results in faulty IC
Testing required to guarantee fault-free products

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I
Importance
t off Testing
T ti
Q Rule
R l off T
Ten: costt to
t detect
d t t faulty
f lt IC increases
i
by an order of magnitude as we move from:
device PCB system field operation
Testing performed at all of these levels
Q Testing also used during
Manufacturing to improve yield
Failure mode analysis (FMA)
Field operation to ensure fault-free system
operation
Initiate repairs when faults are detected
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T ti During
Testing D i VLSI Life
Lif Cycle
C l
Q Testing typically consists of
Applying
pp y g set of test stimuli to
Inputs of circuit under test (CUT), and
Analyzing output responses
If incorrect (fail), CUT assumed to be faulty
If correct (p
(pass),) CUT assumed to be fault-free

Input1 Output1
Input Circuit Output
Test Under Test Response Pass/Fail
ss/
Inputn Outputm
Stimuli (CUT) Analysis

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T ti During
Testing D i VLSI Development
D l t
Q Design
D i verification
ifi ti
targets design errors Design Specification
Corrections made
prior to fabrication Design Design Verification

Q Remaining tests
Fabrication Wafer Test
target manufacturing
defects
P k i
Packaging P k
Package T t
Test
A defect is a flaw or
physical imperfection
Quality
Q y Assurance Final Testing
g
that can lead to a
fault
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Introduction (Contd.)
(Contd )
Lecture 2
D i Verification
Design V ifi ti
Q Different levels of
abstraction during design Design Specification
CAD tools used to synthesize
y
design from RTL to physical Behavioral (Architecture) Level
level
Q Simulation
Si l ti used d att various
i Register-Transfer Level
level to test for
Design errors in behavioral or Logical (Gate) Level
RTL
Design
g meetingg system
y Physical (Transistor) Level
timing requirements after
synthesis
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Yield and Reject Rate
Q We expect faulty chips due to manufacturing
d f t
defects
number of acceptable parts
yield
Called yield total number of parts fabricated

Q 2 types of yield loss


Catastrophic
p due to random defects
Parametric due to process variations
Q Undesirable results during testing
Faulty chip appears to be good (passes test)
Called reject rate reject rate number of faulty parts passing final test
total number of parts passing final test
Good chip appears to be faulty (fails test)
Due to poorly designed tests or lack of DFT 10
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El t i System
Electronic S t Manufacturing
M f t i
Q A system consists of
PCBs that consist of
VLSI devices PCB Fabrication Bare Board Test

Q PCB fabrication similar


PCB Assembly Board Test
to VLSI fabrication
Susceptible to defects Unit Assembly Unit Test

Q Assembly
A bl steps
t also
l
System Assembly System Test
susceptible to defects
Testing performed at all
stages of manufacturing
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System Level Operation
System-Level
S Normal system operation
1

Q Faults occur 0t 0t 1 t2 t3 t4 t
during system operation failures

Q Exponential failure law


Interval of normal system operation is
random number exponentially distributed
Q Reliability
Probability that system will operate normally
t
until time t P(Tn t) e
Failure rate, , is sum of individual k
i
component failure rates, i
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S t
System-Level
L l Operation
O ti
Q Mean Time Between Failures (MTBF)
1
Repair time (R) also assumed to MTBF e dt
t
Q
0
obeyy exponential
p distribution
is repair rate P(R t) e t

Q Mean Time To Repairp ((MTTR)) 1


MTTR

Q Fraction of time that system is
operatingg normallyy called system
y
MTBF
availability system availability
MTBF MTTR
High reliability systems have system
availabilities
il biliti greater
t than
th 0.9999
0 9999
Referred to as four 9s
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S t
System-Level
L l Testing
T ti
Q Testing required to ensure system availability
Q Types
yp of system-level
y testing
g
On-line testing concurrent with system
operation
p
Off-line testing while system (or portion of) is
taken out of service
Performed periodically during low-demand periods
Used for diagnosis (identification and location) of
faulty replaceable components to improve repair time

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T t Generation
Test G ti
Q A test is a sequence
q of test p
patterns,, called
test vectors, applied to the CUT whose
p
outputs are monitored and analyzed
y for the
correct response
Exhaustive
aust e test
testing
g app
applying
y gaall poss
possible
b e test
patterns to CUT
Functional testing g testing
g everyy truth table
entry for a combinational logic CUT
Neither of these are practical for large CUTs
Q Fault coverage is a quantitative measure of
quality
q y of a set of test vectors 15
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T t Generation
Test G ti
Q Fault coverage for a given set of test
number of detected faults
vectors fault coverage
total number of faults
Q 100% fault
f lt coverage may be b impossible
i ibl
due to undetectable faults
number of detected faults
f l detection
fault d efficiency
ff
total number of faults number of undetectable faults
Q Reject
j rate = 1 y yield(1 faultcoverage)
A PCB with 40 chips, each with 90% fault
coverage and 90% yield, has a reject rate
of 41.9%
Or 419,000 defective parts per million (PPM)
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T t Generation
Test G ti
Q Goal: find efficient set of test vectors with
maximum fault coverage
Q Fault simulation used to determine fault
coverage
Requires
equ es fault
au models
ode s to
oeemulate
u a e be
behavior
a o o of
defects
Q Ag
good fault model:
Is computationally efficient for simulation
Accurately reflects behavior of defects
Q No single fault model works for all possible
defects
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F lt Models
Fault M d l
Q A given fault model has k types of faults
k = 2 for most fault models
Q A given circuit has n possible fault sites
Q Multiple fault model circuit
circuit can have multiple
faults (including single faults
Number of multiple
p fault = ((k+1))n-1
Each fault site can have 1-of-k fault types or be fault-free
The -1 represents the fault-free circuit
Impractical for anything but very small circuits
Q Single fault model circuit has only 1 fault
Number of single faults = kkn
n
Good single fault coverage generally implies good
multiple fault coverage
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F lt Models
Fault M d l
Q Equivalent faults
One or more single faults that have identical
behavior for all p
possible input
p p patterns
Only one fault from a set of equivalent faults
needs to be simulated
Q Fault collapsing
Removing equivalent faults
Except for one to be simulated
Reduces total number of faults
Reduces fault simulation time
Reduces
educes test
es pa
pattern
e gegeneration
e a o time
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Introduction (Contd.)
( )
Lecture 3
St k t Faults
Stuck-at F lt Truth table for fault-free behavior
Q Any line can be and behavior of all possible stuck-at faults
x1x2x3 000 001 010 011 100 101 110 111

Stuck-at-0 (SA0) y 0 1 0 0 0 1 1 1
a SA0 0 1 0 0 0 1 0 0
Stuck-at-1 (SA1) a SA1 0 1 1 1 0 1 1 1
b SA0 0 1 0 1 0 1 0 1
# fault types: k=2 b SA1 0 0 0 0 1 1 1 1
c SA0 0 0 0 0 0 0 1 1
Q Example circuit: c SA1 1 1 0 0 1 1 1 1
d SA0 0 1 0 0 0 1 0 0
# fault sites: n=9 d SA1 0 1 0 0 1 1 1 1
e SA0
# single faults =29=18
0 1 0 1 0 1 1 1
e SA1 0 0 0 0 0 0 1 1
f SA0 0 0 0 0 0 0 1 1
x1 a f SA1 0 1 0 1 0 1 1 1
d g SA0 0 1 0 0 0 1 0 0
x2 b g g SA1 1 1 1 1 1 1 1 1
i y
h SA0 0 0 0 0 0 0 1 1
h SA1 1 1 1 1 1 1 1 1
e f h i SA0 0 0 0 0 0 0 0 0
x3 c i SA1 1 1 1 1 1 1 1 1
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Stuck at Faults
Stuck-at Truth table for fault-free behavior
Q Valid test vectors and behavior of all possible stuck-at faults
x1x2x3 000 001 010 011 100 101 110 111
F
Faulty
l circuit
i i differs
diff y 0 1 0 0 0 1 1 1
from good circuit a SA0 0 1 0 0 0 1 0 0
a SA1 0 1 1 1 0 1 1 1
Necessary vectors: b SA0 0 1 0 1 0 1 0 1
b SA1 0 0 0 0 1 1 1 1
011 detects f SA1, e SA0 c SA0 0 0 0 0 0 0 1 1
c SA1
100 detects d SA1 d SA0
1
0
1
1
0
0
0
0
1
0
1
1
1
0
1
0
Detect total of 10 faults d SA1 0 1 0 0 1 1 1 1
e SA0 0 1 0 1 0 1 1 1
001 and 110 detect e SA1 0 0 0 0 0 0 1 1
remaining 8 faults f SA0 0 0 0 0 0 0 1 1
x1 a f SA1 0 1 0 1 0 1 1 1
d g SA0 0 1 0 0 0 1 0 0
x2 b g g SA1 1 1 1 1 1 1 1 1
i y
h SA0 0 0 0 0 0 0 1 1
h SA1 1 1 1 1 1 1 1 1
e f h i SA0 0 0 0 0 0 0 0 0
x3 c i SA1 1 1 1 1 1 1 1 1
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Stuck at Faults
Stuck-at Truth table for fault-free behavior
Q 4 sets of equivalent and behavior of all possible stuck-at faults
x1x2x3 000 001 010 011 100 101 110 111
fa lts
faults y 0 1 0 0 0 1 1 1
a SA0 0 1 0 0 0 1 0 0
Q # collapsed faults = a SA1 0 1 1 1 0 1 1 1

2(PO+FO)+GI-N NI b
b
SA0
SA1
0
0
1
0
0
0
1
0
0
1
1
1
0
1
1
1
PO= # primary outputs c
c
SA0
SA1
0
1
0
1
0
0
0
0
0
1
0
1
1
1
1
1
FO= # fanout stems d
d
SA0
SA1
0
0
1
1
0
0
0
0
0
1
1
1
0
1
0
1
GI= # gate inputs e SA0 0 1 0 1 0 1 1 1
e SA1 0 0 0 0 0 0 1 1
NI= # inverters f SA0 0 0 0 0 0 0 1 1
x1 a f SA1 0 1 0 1 0 1 1 1
d g SA0 0 1 0 0 0 1 0 0
x2 b g g SA1 1 1 1 1 1 1 1 1
i y
h SA0 0 0 0 0 0 0 1 1
h SA1 1 1 1 1 1 1 1 1
e f h i SA0 0 0 0 0 0 0 0 0
x3 c i SA1 1 1 1 1 1 1 1 1
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St k t Faults
Stuck-at F lt
Q # collapsed faults = 2(PO+FO)+GI-N
NI
PO= number of primary outputs
FO= number of fanout stems
GI= total number of gate inputs
for all g
gates including
g inverters
NI= total number of inverters
Q For example
p circuit,, # collapsed
p faults = 10
PO= 1, FO= 1, GI= 7, and NI= 1
Q Fault collapsing typically reduces number of
stuck-at faults by 50% - 60%
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T
Transistor
i t Faults
F lt
VDD
A P1
2-input
B
Q Any transistor can be CMOS P2
Z
NOR
Stuck-short gate
N1 N2
Also known as stuck-short
stuck short
Stuck-open VSS
Truth table for fault-free circuit
Also known as stuck-open
stuck open and all possible transistor faults
AB 00 01 10 11
# fault types: k=2 Z 1 0 0 0
N1 stuck-open 1 0 last Z 0
Q Example circuit N1 stuck-short IDDQ 0 0 0
N2 stuck-open 1 last Z 0 0
# fault sites: n=4 N2 stuck-short IDDQ 0 0 0
# single faults =24=8 P1 stuck
stuck-open
open last Z 0 0 0
P1 stuck-short 1 0 IDDQ 0
P2 stuck-open last Z 0 0 0
P2 stuck-short 1 IDDQ 0 0
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T
Transistor
i t Faults
F lt
VDD
A P1
Q Stuck-short faults cause 2-input
CMOS
B P2
conducting path from VDD NOR Z
gate
to VSS N1 N2

Can be detect by monitoring


VSS
steady-state power supply Truth table for fault-free circuit
current IDDQ and all possible transistor faults
AB 00 01 10 11
Q Stuck-open faults cause Z 1 0 0 0
N1 stuck-open 1 0 last Z 0
output node to store last N1 stuck-short IDDQ 0 0 0
voltage level N2 stuck-open 1 last Z 0 0
N2 stuck-short IDDQ 0 0 0
Requires sequence of 2 P1 stuck
stuck-open
open last Z 0 0 0
vectors for detection P1 stuck-short 1 0 IDDQ 0
P2 stuck-open last Z 0 0 0
0010 detects N1 stuck-open P2 stuck-short 1 IDDQ 0 0
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T
Transistor
i t Faults
F lt
Q # collapsed faults = 2
2T
T -T
TS+G
GS -T
TP+G
GP
T = number of transistors
TS= number of series transistors
GS= number of groups of series transistors
TP= number of pparallel transistors
GP= number of groups of parallel transistors
Q For
o eexample
a pec circuit,
cu t, # co
collapsed
apsed faults
au ts = 6
T=4, TS= 2, GS= 1, TP= 2, & GP= 1
Q Fault collapsing typically reduces number
of transistor faults by 25% to 35%
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Sh t andd Opens
Shorts O
Q Wi
Wires can be
b
Open
Opens in wires interconnecting transistors to form
gates behave like transistor stuck-open faults
Opens in wires interconnecting gates to form
circuit behave like stuck-at faults
Opens
p are detected by
y vectors detecting
g transistor
and stuck-at faults
Short to an adjacent wire
Also known as a bridging fault

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B id i Faults
Bridging F lt AS
source
AD
destination
Q Three different models BS BD

Wired-AND/OR AS
bridging fault
AD AS AD
Dominant
Dominant-AND/OR
D i t AND/OR BS BD BS BD
Wired-AND Wired-OR
Q Detectable by IDDQ testing AS AD AS AD

AS BS 0 0 0 1 1 0 1 1 BS BD BS BD
AD BD 0 0 0 1 1 0 1 1 A dominates B B dominates A
Wired-AND 0 0 0 0 0 0 1 1 AS AD AS AD
Wired OR
Wired-OR 0 0 1 1 1 1 1 1
A dominates B 0 0 0 0 1 1 1 1 BS BD BS BD
B dominates A 0 0 1 1 0 0 1 1 A dominant-AND B A dominant-OR B
A dominant-AND
dominant AND B 0 0 0 0 1 0 1 1 AS AD AS AD
B dominant-AND A 0 0 0 1 0 0 1 1
A dominant-OR B 0 0 0 1 1 1 1 1 BS BD BS BD
B dominant-OR A 0 0 1 1 1 0 1 1 B dominant
dominant-AND
AND A B dominant
dominant-OR
OR A
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D l Faults
Delay F lt andd Crosstalk
C t lk
Q Path delay fault model considers
Path-delay
cumulative propagation delay through CUT
2 test vectors create transition along
gppath
Faulty circuit has excessive delay
Q Delays
y and gglitches can be caused by
y
crosstalk between interconnect
due to inductance and capacitive
p coupling
p g
0 0 x1
0 1 x2 3

t=00 tt=77 y
2
v2 v1
t=2
2
1 1 x3 3
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P tt
Pattern S iti it andd Coupling
Sensitivity C li Faults
F lt
Q Common in high density RAMs
Q Pattern sensitivity fault
Contents of memory cell is affected by
contents of neighboring cells
Q Coupling fault
Transition in contents of one memoryy cell
causes change in contents of another cell

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P tt
Pattern S iti it andd Coupling
Sensitivity C li Faults
F lt
Q Common in memory cells of high density RAMs
Q Pattern sensitivity fault
Contents of cell affected by contents of neighboring
cells
Q Coupling fault
Transition in one cell causes change in another cell
Q Detected with specific memory test algorithms
Background Data Sequence (BDS) used for word-
oriented memories
Notation: Test Algorithm March Test Sequence
w0 = write 0 (or all 0s) March LR (w0); (r0, w1); (r1, w0, r0, r0, w1);
r1 = read 1 (or all 1
1s)
s) w/o BDS (r1, w0); (r0, w1, r1, r1, w0); (r0)
= address up March LR (w00); (r00, w11); (r11, w00, r00, r00, w11);
= address down with BDS (r11, w00); (r00, w11, r11, r11, w00);
= address either way (r00, w01, w10, r10); (r10, w01, r01); (r01)
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Introduction (Contd.)
L t
Lecture 4
L l off Abstraction
Levels Ab t ti
Q High levels have few implementation details
needed for effective test generation
Fault models based on gate & physical levels
Q Example: two circuits for same specification
Ckt B test vectors do not detect 4 faults in Ckt A
a SA1
f(a,b,c)=m(1,7)+d(3) = abc + abc + Xabc b
ab0 0 0 1 1 1 1 0 c
SA1 f
c f = abc + abc
0 1 X SA1 Circuit A
Circuit A Test Vectors
1 SA1
1 {111,110,101,011,010,000}
abb0 0 0 1 1 1 1 0
a
c f = ab + bc
0 1 X b Circuit B
Circuit B Test Vectors f
1 1 {{111,101,010,000}
, , , }
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O
Overview
i off VLSI Test
T t Technology
T h l
Q Automatic
A t ti Test
T t Equipment
E i t (ATE)
consists of
Computer for central control and flexible
test & measurement for different products
Pin
Pi electronics
l t i & fifixtures
t to
t apply
l ttestt
patterns to pins & sample responses
Test
T t program controls
t l timing
ti i off test
t t
patterns & compares response to known
good responses

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O
Overview
i off VLSI Test
T t Technology
T h l
Q Automatic Test Pattern Generation (ATPG)
Algorithms generating sequence of test vectors
for a given circuit based on specific fault
models
Q Fault simulation
Emulates fault models in CUT and applies test
vectors to determine fault coverage
Simulation time (significant due to large number
of faults to emulate) can be reduced by
Parallel, deductive, and concurrent fault simulation
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O
Overview
i off VLSI Test
T t Technology
T h l
Q Design for Testability (DFT)
Generally incorporated in design
Goal: improve controllability and/or
observability of internal nodes of a chip
or PCB
Q Three basic approaches
Ad-hoc techniques
Scan design
Boundary Scan
Built-In Self-Test (BIST)
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D i off Testability
Design T t bilit
Q Ad-hoc DFT techniques
Add internal test points (usually multiplexers) for
Controllability
Observability
Added on a case-by-case basis
Primarily targets hard to test portions of chip

Normal system Normal system


data 0 data 0
Internal Primary
Test data input node to be Internal node to output
1 be observed 1
controlled
t ll d
Test mode select Test mode select
controllability test point observability test point
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D i for
Design f Testability
T t bilit Primary Primary
Inputs Combinational Outputs
Q Scan design Logic

Transforms flip-flops of
chip into a shift register FFs

Scan mode facilitates 1


Di
Di Qi 0 Qi
Shifting in test vectors FF 1 FF
Qi-1
Scan Clk
Clk 2
Shifting out responses
Mode
3
Q Good CAD tool support
Primary Primary
Transforming flip-flops to Inputs Combinational Outputs
Logic
shift register Scan
ATPG FFs
Data
Out
S
Scan D In
Data I 38
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D i for
Design f Testability
T t bilit
Q Boundary Scan scan design applied to
I/O buffers of chip
Used for testing interconnect on PCB
Provides access to internal DFT capabilities
IEEE standard 4
4-wire
wire Test Access Port (TAP)
TAP pin I/O Function
tri-state control Control
BS Cell TCK input Test clock
Scan Out from IC
TMS p
input Test Mode Select
Input Output BS Cell TDI input Test Data In
0 Output TDO output Test Data Out
0 1
Scan capture update Pad
1
In FF FF
Shift
Capture Update input data Input
to IC BS Cell
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D i for
Design f Testability
T t bilit
Q Built-In
Built In Self-Test
Self Test (BIST)
Incorporates test pattern generator (TPG)
and output
p response
p analyzer
y ((ORA))
internal to design
Chip can test itself
Can be used at all levels of testing
Device PCB system field operation
Primary Inputs
0 Circuit Primary Outputs
Under
TPG 1 T t
Test
Pass
BIST Mode ORA
Fail
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Concluding Remarks
Q Manynew testing challenges
presented by
Increasing size and complexity
of VLSI devices
Decreasing feature size
Q Low
power VLSI testing
QTemperature aware testing

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DFT
Lecture 5
Design
g for Testabilityy

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Design For Testability - contents
D Introduction
D Testability Analysis
D Design for Testability Basics
D Scan Cells Designs
g
D Scan Architectures
D Scan Design Rules
D Scan Design Flow
D Special-Purpose Scan Designs
D RTL Design for Testability
D Concluding Remarks
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Introduction
D History
During
D i early
l years, d
design
i and
d ttestt were separate
t
The final quality of the test was determined by keeping track of
the number of defective parts shipped to the customer
Defective parts per million (PPM) shipped was a final test
score.
This approach worked well for small-scale integrated circuit
During 1980s, fault simulation was used
Failed to improve the circuits fault coverage beyond 80%
Increased test cost and decreased test quality
lead to DFT engineering

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Introduction
D History
Various testability measures & ad hoc testability
enhancement methods
To improve the testability of a design
To ease sequential
q ATPG ((automatic test pattern
p generation))
g
Still quite difficult to reach more than 90% fault coverage
Structured DFT
To conquer
q the difficulties in controlling
g and observing
g the
internal states of sequential circuits
Scan design is the most popular structured DFT approach
Design for testability (DFT) has migration recently
From gate level to register-transfer level (RTL)

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Testability Analysis
D Testability:
A relative measure of the effort or cost of testing a logic
circuit
D Testability Analysis:
The process of assessing the testability of a logic circuit
D Testability Analysis Techniques:
Topology-based
T l b dTTestability
t bilit Analysis
A l i
SCOAP - Sandia Controllability/Observability Analysis Program
Probability-based testability analysis
Simulation-based Testability Analysis

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Testability Analysis
D C t ll bilit
Controllability
Reflects the difficulty of setting a signal line to a
required logic value from primary inputs
D Observability
Reflects the difficulty of propagating the logic
value of the signal line to primary outputs

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Probability-Based Testability Analysis

D Used to analyze the random testability of


the circuit
C0(s): probability-based 0-controllability of s
C1(s): probability-based 1-controllability of s
O(s): probability-based observability of s
D Range between 0 and 1
D C0(s) + C1(s) = 1

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Probability-based
y controllabilityy
calculation rules 0-controllability
(Primary input, output, branch)
1-controllability
(Primary input, output, branch)

Primary Input p0 p1 = 1 - p0
AND 1 (output 1-controllability) (input 1-controllabilities)
OR (input 0-controllabilities) 1 (output 0-controllability)
NOT Input 1-controllability Input 0-controllability
NAND (input 1-controllabilities) 1 (output 0-controllability)
NOR 1 ((output
p 1-controllability)
y) ((input
p 0-controllabilities))
BUFFER Input 0-controllability Input 1-controllability
XOR 1 1-controllabilty (C1(a) C0(b), C0(a) C1(b))
XNOR 1 1-controllability (C0(a) C0(b),
C0(b) C1(a) C1(b))
Branch Stem 0-controllability Stem 1-controllability

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Probability-based
P b bilit b d observability
b bilit
calculation rules Observability
(Primary output, input, stem)

Primaryy Output
p 1

AND / NAND (output observability, 1-controllabilities of other inputs)

OR / NOR (output observability, 0-controllabilities of other inputs)

NOT / BUFFER Output observability

XOR / XNOR a: (output observability, max {0-controllability of b, 1-controllability of b})


b: ((output
p observability,
y, max {{0-controllabilityy of a,, 1-controllabilityy of a})
})

Stem max {branch observabilities}

a, b: inputs of an XOR or XNOR gate

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Design for Testability Basics
D Ad hoc DFT
Effects are local and not systematic
Not methodical
Difficult to predict
D A structured DFT
Easily incorporated and budgeted
Yield the desired results
Easy to automate

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Ad Hoc Approach
D Typical ad hoc DFT techniques
IInsertt test
t t points
i t
Avoid asynchronous set/reset for storage
elements
l t
Avoid combinational feedback loops
Avoid
A id redundant
d d t logic
l i
Avoid asynchronous logic
Partition
P i i a largel circuit
i i into
i smallll blocks
bl k

EE141
Ad Hoc Approach Test Point Insertion
Logic circuit
.
Low-observability node B

.
Low-observability node A L
Low-observa
b
.
bili node
bility d C

OP1 OP2 OP3


DI
DI DI OP2 shows the
1 SI SO SI 0 SO SI SO structure of an
D Q OP_output
1
SE SE observation,
SE which is
SE . . . . composed of a
CK
Observation shift register multiplexer
(MUX) and daD
flip-flop.
Observation point insertion

EE141
Ad Hoc Approach Test Point Insertion
Logic circuit A MUX is inserted
Low-controllability nodeB between the source
Source x Destination and destination ends.
Original connection
Low-controllability node C D i normall
During
Low-controllability node A operation, TM = 0,
such that the value
CP1 CP2 CP3 from the source end
DI DI
0 DO DI drives the destination
DO
1
DO
end through the 0
CP_input SI SO
SI D
Q . SO SI SO port of the MUX.
TM TM TM

. . . During test, TM = 1
TM
CK . such that the value
Control shift register from the D flip-flop
drives the destination
end through the 1
Control point insertion port of the MUX.

EE141

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