Computer Organisation and

Architecture
 References
William Stallings, Computer Organization
and Architecture: Designing for
Performance, Eighth Edition, Pearson.
P .Chakraborty, Computer Organization and
Architecture,Jacob Publication.
Dr. M. Usha, T. S. Srikanth, Computer System
Architecture and Organization,First Edition,
Wiley-India.
Overview of Computer Architecture &
Organization
Topics to be covered:
What is a computer?
Data v/s Information
Organisation v/s Architecture
Structure v/s Function
Functions-Data processing ,movement , storage , controlling.
Computer Level Hierarchy
Classification of processor architectures : Von-Neumann and
Harvard
Detailed Architecture of Von Neumann machine
Buses : Types ,Physical Implementation ,Structures and Designing
parameters
Performance Measures of Computer Architecture
 Objectives
Know the difference between computer organization and computer
architecture.
Understand the computer as a layered system and the function of
basic computer components
Analyse the difference between different computer functions.
Be able to understand the computer level hierarchy.
Classify the processor architectures and explain the Von Neumann
Architecture.
Classify different types of buses and identify design aspects of
buses.
Identify the performance measures of Computer Architecture.
 Computer Is........
A computer:
Takes input
Processes it according to stored instructions
Produces results as output
Was taken from the Latin word Computare ,
which means calculate
 Data v/s Information
Data is raw fact. There are five types of data:
Text : alphabetic ,numeric , special symbol
Graphics :picture
Audio : any kind of sound
Video: a series of photo frame which record the
real
Animation : a series of image which is displayed
one by one to produce a movement illusion
Information :data that has been processed and
contains meaning
Analogy to differentiate Organisation
and Architecture
Task 1: Building a house
Task 2:Washing clothes in machine
Task 3: Is the gear lever in a car part of its
architecture or organization?
Whether organisation or architecture: How
does a computer work? How do I design a
computer?
Analogy to differentiate Organisation
and Architecture
To build a house you may contact an architect who will give
you the sketch of a house. And for building that design you
will contact a contractor.
Creating a design of a house can be considered as
Computer Architecture, where as building the house can be
considered as Computer Organisation.
Washing clothes involves the process of washing,rinsing
and drying .Carrying out the task is architecture. Deciding
the structural change in the washing tub is organisation.
The architecture of a car is simple; it transports you from A
to B. The gear lever belongs to the car's organization
because it implements the function of a car
 Architecture and Organisation
Computer Architecture
Logical aspects of system
implementation as seen by the
designer
Architecture is the set of attributes
visible to the programmer
instruction sets, instruction formats,
data types, addressing modes
Architecture describes what the
computer does.
deals with how to design a circuit for
such hardware.
Examples:
Does this processor have a multiply
instr.?
How does the compiler create
object code?
How best is memory handled by
the O/S?
Computer Organisation
Encompasses all physical aspects of
computer systems
Organization is how features are
implemented
circuit design, control signals, memory
types
Organization describes how it does it.
deals with how a particular hardware
works in a computer.
Examples:
Is there a hardware multiply unit
or is it done by repeated addition?
What type of non-volatile memory
is used to store the BIOS?
 Architecture and Organisation
All Intel x86 family share the same basic architecture while the IBM
System/370 family share the same basic architecture
Consistent architecture gives code compatibility, at least backwards,
thus protecting users software investment
For designing a computer, its architecture is fixed first and then its
organization is decided
Organization differs between different versions
Architecture and organization are independent; you can change the
organization of a computer without changing its architecture. For
example, a 64-bit architecture can be internally organized as a true
64-bit machine or as a 16-bit machine that uses four cycles to
handle 64-bit values.
Differences in organization but not architecture leads to families:
Different cost and performance,Run same code,Families may span
years of technological advancement
 Structure and Function
Structure is the way in which components
relate to each other
Function is the operation of individual
components as part of the structure
Computer Structure
Computer-The Main Structure
Functions of
each unit
To process data and
control the computer
operations
To keep data during
process

The mechanism which is

used to communicate
between CPU ,main
memory and I/O
To move data and
information between
computer and external
environment
 Structure The CPU
Functions of
each unit
Registers : Provides
storage internal to the
CPU
ALU:Performs the
computers data
processing functions
CU:Control the operations
of the CPU

Interconnections:Provides
mechanism for
communication among
CU,ALU and registers
 Structure-The Control Unit
Functions of each unit

Sequencing logic:Issues read

command to Control Memory
and
decides on the next instruction
to be executed .

CU registers and decoders:

Stores the current instructions
and their decoded actions
Control memory: Stores all
controlling actions required for
CPU operation.
Function
All computer functions are
comprised of four basic
operations:
Data processing
Data storage
Data movement
Control
Data Processing
Processing
The basic function of from/to
any computer is to storage
process data
Describes arithmetic
and logical operations
performed on data
Although end result
may be complex, there
are few distinct types
of data processing
Processing from
Ex: Updating the storage to I/O
account status,Printing
bank statements
 Data Storage
Long term
Logging
Data records
Short term
temp variables
e.g., buffer containing
the last key pressed
program control data
e.g., loop variables
 Data Movement
Computer must be able to communicate with
outside world
Data must be accessible to devices outside
computer
Two types:
Data movement to Peripheral:
Data must be passed between computer and
I/O devices connected to computer
Typically to simple devices
Examples:
monitors and keyboards
data acquisition
peripheral control
Data movement to remote devices(data
communications):
Data communications is data movement over a
longer range
Typically to smart devices or other computers
 Control
Something needs to monitor operation and
maintain control of data processing, data
storage, and data movement.
Automated control of computers resources
 Points to Ponder
Determine which of the previous operations applies
each of the following uses:
Router
Hard drive controller
Video capture or CD player
Hub
Bridge
Repeater
CD
Switch
Come up with additional examples for each of the
previous operations
 The Computer Level Hierarchy
In programming, we divide a problem into modules and then
design each module separately.
Each module performs a specific task and modules need only
know how to interface with other modules to make use of
them.
Computer system organization can be approached in a similar
manner.
Through the principle of abstraction, we can imagine the
machine to be built from a hierarchy of levels, in which each
level has a specific function and exists as a distinct
hypothetical Machine
We call the hypothetical computer at each level a virtual
machine.
Each levels virtual machine executes its own particular set of
instructions, calling upon machines at lower levels to carry out
the tasks when necessary
The Computer Level Hierarchy
 The Computer Level Hierarchy
Level 6: The User Level
Composed of applications
we run programs such as word processors, graphics
packages, or games.
Level 5: High-Level Language Level
The level with which we interact when we write
programs in languages such as C and Java
These languages must be translated to a language the
machine can understand. (using either a compiler or an
interpreter)
Compiled languages are translated into assembly
language and then assembled into machine code. (They
are translated to the next lower level.)
 The Computer Level Hierarchy
Level 4: Assembly Language Level
Acts upon assembly language produced from Level 5, as
well as instructions programmed directly at this level
By having separate levels, we reduce the semantic gap
between a high-level language, such as C++, and the actual
machine language

Viva Question:
Difference between compiler ,interpreter and assembler.
Which language uses compiler or interpreter :
Python , C/C++,Java
 The Computer Level Hierarchy
Level 3: System Software Level
deals with operating system instructions.
This level is responsible for multiprogramming, protecting
memory, synchronizing processes, and various other important
functions.
Often, instructions translated from assembly language to
machine language are passed through this level unmodified
Level 2: Machine Level
Consists of instructions that are particular to the architecture
of the machine
Programs written in machine language need no compilers,
interpreters, or assemblers
 The Computer Level Hierarchy
Level 1: Control Level
A control unit decodes and executes instructions and moves
data through the system.
Control units can be microprogrammed or hardwired.
A microprogram is a program written in a low-level language
that is implemented by the hardware.
Hardwired control units consist of hardware that directly
executes machine instruction

Level 0: Digital Logic Level

This level is where we find digital circuits (the chips).
Digital circuits consist of gates and wires.
These components implement the mathematical logic of all
other levels
 Taking you to the processors
world
Whats there inside a processor?
Instruction: operation
Opcode : code of the operation
Operand : data on which operation has to be
carried out
Instruction pipelining stages : Fetch ,Decode
and Execute
Imp. Viva Question : What is an instruction cycle ,
machine cycle and bus cycle(T-state)?
How to classify processor architectures?
Categorized by memory organization
Categorized by memory organization
Von-Neumann architecture(Princeton Institute for Advanced Studies)
one of the primitive architecture.
program and data are stored in the same memory, and are accessed on the same
bus.
Each instructions is fetched (read from the memory), decoded and executed.
During the decode state, any operands (if needed) are fetched from the same
memory.
Execution occurs in sequential fashion from one instruction to the next
Harvard architecture
modification over Von-Neumann architecture.
separate data paths (address and data buses) exist to access code (program) and
data (data operands).
This makes it possible to fetch instructions and data at same time (on different
buses).
Since instructions have a separate data path, next instructions can be fetched
while decoding and executing the current instructions.
 Difference between Von Neumann
and Harvard architecture
Von Neumann
named by early computer scientist john
Von Neumann .
has single storage system for storing data
and program
needs two clock cycles to complete an
instruction.
Pipelining ,not possible
This is a relatively older architecture and
was replaced by Harvard architecture.
Harvard
name is originated by Harvard Mark I a
relay based old computer.
has two separate memories for storing
data and program.
can complete an instruction in one
Pipelining, possible
Most of the modern computing
architectures are based on Harvard
architecture. But the number of stages in
the pipeline varies from system to system.
 Categorized by instruction type
CISC(Complex Instruction Set Computer)
single instruction could fetch one or more operands and do one or
more operations on those operands.
made the programming much easier as programmer had to write
less code (less number of instruction) to achieve a given task.
Reduced memory cost

RISC(Reduced Instruction Set)

simpler instructions could speed up the pipe-line and thus provide
a performance improvement.
simple instruction set implies less complex computer hardware
execution faster.

VLIW(Very Large Instruction Word)

consists of multiple ALUs in parallel
Programmers can break their code such that each ALU can be
loaded in parallel
there should not be any interdependency between the
instructions with are part of instruction word.
 Basic Von Neumann(IAS) Architecture
Main Memory:Stores both
data and
instructions(Contains 4096
storage locations of 40 bits
each)
ALU:Capable of operating on
binary data
CU:Interprets the instructions
in memory and causes them
to be executed
I/O:Operated by control Unit
Memory Location Contents
 Detailed IAS structure
Set of registers (storage in CPU)
Program Counter (PC):Used to store
the address of next instruction.
Memory Address Register
(MAR):12-bit address register gives
the address to be read or written into
MBR.
Memory Buffer Register (MBR):40-
bit register
Accumulator (AC)&Multiplier
Quotient (MQ):40-bit register for
temporary storage of operands and
results.
Instruction Register (IR) &
Instruction Buffer Register
(IBR):Fetches two instructions
simultaneously from MBR
 Bus : Common Characteristics
Bus -communication pathway connecting two or
more devices.
A shared transmission medium.
Multiple devices connect to the bus
While multiple transmissions ,only one device at a
time can be successful transmit.
A bus that connects major computer components
(processor, memory, I/O) is called system Bus.
These lines can be classified as :
Data Lines
Address Lines
Control Lines
Bus Interconnection Schemes
 Data Lines
Provides a path for moving data between system modules
,together called as DATA BUS.
No of lines being referred to as the width of the data bus.
Because each line can carry only 1 bit at a time, the no of
lines determine how many bits can be transmitted at a
time.
No. of data lines corresponds to the number of I/O
devices to be connected to processor .
If data bus is 8 bits wide and each instruction is 16 bits long
then the processor must access memory module twice
during each instr. Cycle or will require two instr. cycles
 Address Lines

Used to designate the destination of the opcode

or operand (data)

Width of the address bus determines the

maximum possible memory capacity of the
system.

Generally also used to address memory locations

and I/O ports.
 Control Lines
Used to control the access to the use of the data and address
lines.
The data and address lines are shared by all components, there
must be a means of controlling their use.
Control signals transmit both command and timing
information between system modules.
Timing signals indicate the validity of data and address info.
Operation Sending Data
Obtain the use of the bus,Transfer the data via the
bus,Possible acknowledgement
Operation Requesting Data
Obtain the use of the bus, Transfer the data request via the
bus, Wait for other module to send data, Possible
acknowledgement
 Control Lines
Typical control signals:
Memory Write :causes data on the bus to be written into address
location
Memory Read :causes data from the addressed location to be placed on
the bus.
I/O Write: causes data on the bus to be output to the addressed I/O port.
I/O Read: causes data from the addressed I/O port to be placed on the bus.
Transfer ACK: indicates that data have been accepted from or placed on
the bus.
Bus Request : Indicates that a module needs to gain control of the bus.
Bus grant : indicates that a requesting module has been granted control of
the bus.
Interrupt request : indicates that an interrupt is pending
Interrupt ACK : Acknowledge that the pending interrupt has been
recognized.
Clock : used to synchronize operations.
Reset : initialize all modules
Physical Implementations
Parallel lines on
circuit boards
(ISA or PCI)
Ribbon cables
(IDE)
 Physical Implementations
Strip connectors on
mother boards (PC104)
External cabling (USB or
Firewire)
 Bus Structures: Single Bus
Lots of devices on one bus ,only two can communicate
at a time
Physically long buses encounters Propagation delays
Long data paths mean that coordination of bus use can
adversely affect performance
Arbitration is required when multiple requests : Done
by control lines
Cannot match up with the need of high data transfer
rates of high speed devices like video controllers and
network interfaces.
Low cost and flexibility of attaching peripheral devices.
Bus Structures: Multiple Bus
 Bus Structures: Multiple Bus
Traditional Bus Architecture:
Most systems use multiple buses to overcome these problems

Processor has bus that connects as direct interface to chip, then an

expansion bus interface interfaces it to external devices (ISA)

Cache (if it exists) may act as the interface to system bus

Expansion Bus Interface:

Requires bridge to buffer (FIFO) data due to differences in bus speeds(
Sometimes I/O devices also contain buffering (FIFO))
Isolate processor-to-memory traffic from I/O traffic

Support wider variety of interfaces

Bus Structures: Multiple Bus
 Bus Structures: Multiple Bus
Mezzanine Approach(High Speed Bus architecture)
Differences in I/O speeds demands separating
devices.
Separate items that are high-speed and those
that are not
An additional high-speed bus is added to
communicate with the faster devices and also the
slower expansion bus
Advantage is that high-speed devices are brought
closer to processor
 Start Thinking!!!!

You need to design a bus structure in your

processor ,decide which parameters would
you consider in designing?
 Elements of Bus Design
While designing the bus required on the system,
following parameters can be used:
Type of bus:Dedicated or multiplexed
Physical dedication:Single or multiple buses
Method of arbitration:Centralised or distributed
Bus width:Address and data
Data transfer types:read,write,read modify
write,read after write,block
Timing :Synchronous and Asynchronous
Direction of flow of signals : Uni-directional and
bi-directional
 Type of Bus
Dedicated
Separate data & address lines
Time multiplexed
Shared lines
Address valid or data valid defined by control line
Advantage - fewer lines
Disadvantages- More complex control ,
Degradation of performance
 Method of Arbitration
Listening to the bus is not usually a problem

Talking on the bus is a problem need arbitration to allow

more than one module to control the bus at one time

Centralized bus arbitration requires hardware that will

grant the bus to one of the requesting devices. This
hardware can be part of the CPU or it can be a separate
device on the motherboard .

In decentralized arbitration there isn't an arbiter, so the

devices have to decide who goes next. This makes the
devices more complicated, but saves the expense of having
an arbiter.
For Data bus:
Bus width
a) The width of the data bus has an impact on the system
performance .
b) Wider the data bus, greater number of bits are transferred at
one time.
For address bus :
a) The width of the address bus has an impact on the system
capacity.
b) The width of the address bus also allows the range of reference
location to be greater.
 Timing
Co-ordination of events on bus
Synchronous controlled by a clock
Asynchronous timing is handled by well
defined specifications, i.e., a response is
delivered within a specified time after a request
 Synchronous Bus Timing
Events determined
by clock signals
Control Bus includes
clock line
A single 1-0 cycle is
a bus cycle
All devices can read
clock line
Usually sync on
leading/rising edge
Usually a single cycle
for an event
Asynchronous
Timing
Devices must have
certain tolerances to
provide responses to
signal stimuli
More flexible allowing
slower devices to
communicate on same
bus with faster devices.
Performance of faster
devices, however, is
limited to speed of bus
 Timing
Sr. Synchronous Bus Asynchronous Bus
No.
1 Simpler to implement Highly flexible
and test
2 All the devices are tied No fixed clock
to a fixed clock rate
3 Not applicable Mixture of slow and fast
devices can share a bus
 Data Transfer types
Read

Write

Read Modify Write

Read After Write

Block
 Direction
Address bus: Uni-directional (flow is from
processor to device)
Data bus: Bi-directional (flow can be from
processor to device or from device to
processor)
Six Passenger Aircrafts to be Compared
B 747

DC-8-50
 Performance of Aircraft: An Analogy
Key characteristics of six passenger aircraft: all figures are approximate

Range Speed Price

Aircraft Passengers
(km) (km/h) ($M)
Airbus A310 250 8 300 895 120

Boeing 747 470 6 700 980 200

Boeing 767 250 12 300 885 120

Boeing 777 375 7 450 980 180

Concorde 130 6 400 2 200 350

DC-8-50 145 14 000 875 80

 Different Views of Performance

Performance from the viewpoint of a

passenger: Speed/Ticket Fare
Performance from the viewpoint of a air-craft
designer: Cost
Performance from the viewpoint of an airline:
Throughput
Performance from the viewpoint of
FAA(Federal Aviation Administration): Safety
Cost Effectiveness: Cost/Performance
 Start Thinking!!!!

You need to design a processor ,which

performance parameters would you consider?
 Performance Measures of Computer
Architecture
Execution time=response time
Throughput = 1/execution time
Performance of a computer can be achieved : proper
match between machine capability and program
behaviour
Machine Capability: better hardware technology,
innovative architectural features ,efficiently managing
resources
Program Behaviour: compiler used, algorithm design,data
structures used, language efficiency, programmer skill
Program behaviour is difficult to predict since it heavily
depends on application and run- time condition.
 Performance factors
Increase in CPU performance, may come from factors:
Increase in clock rate, R=1/P ;where P=length of one clock cycle
By improving the IC technology which makes logic circuits work faster
By reducing the amount of processing done in one step
Improvement in processor design to lower performance parameter T(CPU
execution time)
Pipelining and superscalar operations
Compiler enhancements for lower average CPI
may rearrange the program instructions to achieve better performance
without affecting the results of computation
Better memory organization
Using Harvard Architecture
Using an appropriate instruction set : RISC or CISC
 Basic Performance Equation
Performance = 1 / Execution time is simplified to

Performance = 1 / CPU execution time

(Performance of M1) / (Performance of M2) = Speedup of M1 over M2
= (Execution time of M2) / (Execution time M1)
CPU time = Instructions * (Cycles per instruction) * (Secs per cycle)
= Instructions * CPI / (Clock rate)
T=N*CPI(S)/R
Optimum design means reducing T
N reduction: Source program is compiled with few machine instructions
S reduction: overlapping of instructions
R increase:Using high Frequency clock
Instruction count, CPI, and clock rate are not completely independent, so improving one by
a given factor may not lead to overall execution time improvement by the same factor.
 SPEC rating
Organisation: System Performance Evaluation Corporation
specified benchmark programs and reference computers in
1995 and 2000
For SPEC95:reference was SUNSPARC Station 10/40
For SPEC2000:reference was UltraSPARC10
SPEC rating=TR / TC;
TR = Running time of the Reference Computer;
TC = Running time of the Computer under test;
For all selected programs SPEC rating is calculated
individually and then the geometric mean is determined .
Higher the SPEC score, better is the performance
Numerical on System Performance
Numerical on System Performance
 Solutions to numericals

2.Ncisc/Nrisc=80 % (case 1)
Ncisc/Nrisc=66.67 % (case 2)