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Computer Organisation and


Processor Organisation and

Topics to be covered
Phases of Instruction
Control Unit Designs
Micro-instruction sequencing and execution
Applications of Micro-programming
Types of Microprogramming
Concept of Nano-programming
Study of RISC and CISC processor architectures
Basic Instruction Cycle

Basic Instruction cycle with interrupt cycle

Instruction Cycle State Diagram

A single instruction may require many steps:

Determine address of instruction Two flip-flops marked F and E
Fetch instruction identify each of these 3 cycles
Decode instruction
Determine address(es) of source operands F E Comments
Fetch operand(s) 0 0 Not used
Execute instruction 1 0 Fetch Cycle
Determine address(es) where result(s) are to be stored 0 1 Execute Cycle
Store result(s) 1 1 Interrupt Cycle
Check for interrupts
Instruction Fetch
PC contains address of next instruction
Address moved to Memory Address
Register (MAR)
Address placed on address bus
Control unit requests memory read
Result placed on data bus, copied to
Memory Buffer Register (MBR), then to IR
Meanwhile PC incremented by size of
machine code (typically one address)
Sequence of micro-instructions of fetch
CPU enters fetch cycle if F=1andE=0
C01:MAR -----PC
C02C03:MBR -----(Memory);PC=PC+1
C04:IR ------MBR
Data Fetch
IR is examined and decoded to understand where
the required operand is stored .
Control Unit accordingly enables the source and
destination resources.
Data from the source is picked and dropped down
into the executing unit .
If data is residing on a memory location ,address of
the location is calculated (indirect cyce)and data is
picked up from that location.
Indirect Cycle

Some instructions require operands, each of which requires

a memory access
With indirect addressing, an additional memory access is
required to determine final operand address
Indirect addressing may be required of more than one
operand, e.g., a source and a destination
Each time indirect addressing is used, an additional operand
fetch cycle is required.
EX:In 8086 ADD AX,[BX] requires indirect cycle
Indirect Cycle
IR is examined to determine if indirect
addressing is needed. If so, indirect
cycle is performed
Address of location from which to
fetch operand address is calculated
based on first fetch
Result (actual address of operand)
moved to MBR
Address in MBR moved to MAR
Address placed on address bus
Control unit requests memory read
Result placed on data bus, copied to
Execute Cycle
Due to wide range of instruction complexity, execute cycle may
take one of many forms.
register-to-register transfer
memory or I/O read
ALU operation
Duration is also widely varied
CPU enters execute cycle if F=0 and E=1
Interrupt Cycle
CPU enters interrupt cycle if F=1 and
At the end of the execution of an
instruction, interrupts are checked
Unlike execute cycle, this cycle is
simple and predictable
If no interrupt pending go to
instruction fetch
If interrupt pending
Current PC saved to allow
resumption after interrupt
Contents of PC copied to MBR
Special memory location (e.g.
stack pointer) loaded to MAR
PC loaded with address of
interrupt handling routine
MBR written to memory
Next instruction (first of
interrupt handler) can be
Phases of Instruction
Interpretation phase:
CU reads(fetches) an instruction from the memory addressed by the contents
of PC into IR.
CU inputs the contents of IR and decodes it.
CU recognizes instruction type ,obtains the necessary operands and routes
them to appropriate functional units(registers or ALU).
Execution :
CU issues necessary signals to perform desired operation and routes the
results to the destination specified.
CU generates the address of the next instruction to be executed and loads it
into the PC.
Two general types of Sequencing:
1.Instruction Control Transfer
2.Program Control Transfer
Instruction Control Transfer
PC holds the address of the instruction to be executed
During fetch cycle PC is incremented to hold the address of the next
Assuming each instruction has a length of one byte, then PC is incremented
by one, that is , PC <= PC + 1;
Length of a variable length instruction needs to be specified in some bits of
the operation code field of instruction
Types: straight- line or In-line ,non-sequential
Transfer of control to non sequential instruction occurs during execution
cycle of conditions branch with specified condition satisfied or by an
unconditional branch instruction or for loop
Jump X (Unconditional branch to X) or
JZ X (Branch to X if the result of last arithmetic operation is zero)
Program Control Transfer
While program P1 is running ,CPU is under control of
Transfer of program control may occur in 2 situations
1. There is an instruction in P1 which calls a
subroutine denoted as program P2
EX: CALL X, where X denotes starting address of P2
2. While an instruction in P1 is getting fetched and
executed ,an interrupt flag gets set, where X denotes
starting address of Interrupt Service Routine (P2).After
execution of current instruction branch to location X
takes place.
Prior to transferring control to P2 ,the CPU status of
P1 is stored in stack (push and pop operation)
Program stored in memory(inside CU) that generates all the control signals required to
execute the instruction set correctly.
Consists of microinstructions.
Ex: Fetch process has a set of micro instructions which forms one micro-program.
Contains a control word and a sequencing word.
Control Word -All the control information required for one clock cycle.
Sequencing Word -Information needed to decide the next microinstruction address.
Vocabulary to write a micro-program.
Ex: Microinstruction during fetch process involves contents of PC to move to MAR.
Set of operations or a series of steps which involves the processor registers required for
fetching ,decoding and executing are referred to as Micro-operations.
Ex : PC MAR micro-instruction requires two micro-operations : Activating PC and MAR and
then transferring contents from PC to MAR.
Control Unit : Commander in the CPU
It is part of CPU:
Takes care of processing
Generate appropriate signals needed internally to the
processor and also externally(memory & I/O devices)
Types :1. Hardwired
2. Softwired (Micro-programmed)
Hardwired Control Unit
Uses a fixed control circuit to interpret
instructions and generate control
If instruction of 8 bits,decoder has
2^8 =256 lines.
For every instruction only one line out
of the decoder is active.
For ex: mov R1,R2 would have opcode 03H
,it would be decoded by decoder as
0000 0011 which would make output
line O3 of decoder active .
The cycle counter consists of a step
decoder which provides a separate
signal line for each step or time slot in a
control sequence.
The control matrix is usually an encoder
which gets inputs from all to generate
necessary control signals.
An end signal is issued after the
operation is done and it resets the step
decoder making it ready for serving the
next instruction.
More on....Hardwired CU
Design methods:
Sequence counter method: To design controller of moderate complexity
Delay element method: Depends on the use of clocked delay elements for
generating the sequence of control signals
State table method: Employs the algorithmic approach to sequential
circuit design using classical state table method
Minimizes the average number of clock cycles needed per instruction
occupies a relatively small area (typically 10%) of the CPU chip area
High efficiency in terms of operation speed as the control signals are
generated under hardware control.
minimizes cost of the circuit
Complex sequencing & micro-operation logic
Difficult to design and test
Inflexible design: cannot add new features in existing design of CU as the
instructions increase.
Large design turn around time for complex design
Difficult to add new instructions
Soft-wired (Micro-programmed)
Control Unit
Whenever an instruction is uploaded
inside IR it is further decoded.
For the decoded instruction ,there exists
some micro-instructions(a micro-
program) .
Sequence logic unit loads the address of
the micro-instruction (residing in the
Control Memory) in the CAR.
Sequence logic then issues a read
command to CM (usually a
After this the Control buffer register
generates control signals and next
address information as received from the
CM s specific address.
Soft-wired (Micro-programmed)
Sequence logic loads new address
into control address register based on
next address information from
control buffer register and ALU flags
in the next clock cycle.
Depending on ALU flags and control
buffer register
Get next micro -instruction
Add 1 to control address
Jump to new conditional branch
Load address field of control
buffer register into control
address register.
Jump to a new machine
instruction from IR
More on....Softwired CU
flexible and allows designers to incorporate new and more powerful
instructions by simply rewriting or modifying the contents of
control memory.
allows any design errors discovered during the prototyping stage to
be removed.
Control operations are implemented using software .
Design process is orderly and systematic.
Faults can be easily diagnosed in this method using diagnostic tools
by maintaining the contents of flag,registers and counters.
requires several clock cycles to execute each instruction, due to the
access time of the microprogram memory. Hence slow in operation.
Occupies a large portion (typically 55%) of the CPU chip area.
Wilkess Microprogrammed CU
Consists of two registers,address
decoder and matrix partially filled
with diodes.
Rows divided into two parts:
1st part of row: generates the
control signal
2nd part of row:generates the
address of the row which will
generate the control signal
Initially reg .I contains the address
of rows.,the decoder generates the
activation signal for the row of the
matrix when clock is active.
In the next clock,instruction from
IR is dropped down into Reg.II and
then to Reg.I to generate the
necessary control signals on
appropriate control lines.
Alternating clock pulses are used
to activate a row of the matrix and
to transfer contents from reg.II to
Difference between Hardwired and Softwired CU
Parameters Hard wired CU Soft wired CU
Control Signals Issued by hardware Issued by software
Speed of fast slow
Flexibility Not flexible to Flexible to accommodate new
accommodate new system system specifications or new
specifications or new instructions
Testing and Very difficult Easy
Design Process Complicated Orderly and systematic
Memory No ROM of size of around 2K-10K.
Chip area Uses less area Uses more area
Instruction set Small instruction set Large instruction set
size supported
Applications RISC Processors Mainframes
Micro-instruction sequencing and
Micro-programmed CU performs two tasks:
Microinstruction sequencing-fetching the
next instruction from the control memory by
determining the address of next
Micro-instruction execution-decoding the
microinstruction and generating the control
signals needed to execute the
Micro-instruction Sequencing
Design considerations of micro-instruction sequencer:
Size(length of MI):should be min. to reduce size of CM ,finally
reducing the cost.
Address generation time :should be executed in less time
resulting in better throughtput.
Sequencing Techniques:
Sequencing is done using Address generation:
Based on current microinstruction, condition flags, contents of IR
Based on both conditional and unconditional branch
Branching based on format of address information
Two address fields
Single address field
Variable format
Various techniques have been designed for this purpose, which
have three categories- single address field , two address field,
variable format.
Two Address Fields Approach
The flag bits and CBR bits are
as inputs to the branch logic.
The branch logic produces the
address selection signals for
the MUX.
As per the address selection
input ,the MUX transmits
either opcode from the IR or
one of two addresses.
Decoder decodes the contents
of CAR and produces the next
address of MI from CM.
Advantage:Simple,no address
calculation is required.
Disadvantage:Requires more
Single Address Field Approach
The flag bits and CBR bits are
as inputs to the branch logic.
The branch logic produces the
address selection signals for the
As per the address selection
input ,the MUX transmits either
opcode from the IR , address
from CBR or an incremented
value of CAR.
Decoder decodes the contents
of CAR and produces the next
address of Micro-instruction
from CM.
Disadvantage: Requires more
circuitry ie.adder
Variable Format Approach
The branch logic produces the
address selection signals for the
MUX based on flag inputs, MSB bit
of CBR and the branch control field.
It provides two different micro-
instruction formats.
If MSB of CBR=0,the remaining
bits are used to activate control
In this format ,the MUX will
either select next sequential
address or address from IR.
In the second format, MSB of
CBR=1,either a conditional or
unconditional branch is being
Micro-instruction Execution
Executing the micro operations controlled by
different signals encoded in various control
fields of the microinstruction.
Decoding and applying control signals on the
CPU data path.
Executing the intended micro operations
controlled by the signals.
Storing the output in the destination register
specified in the micro operation on the CPU
data path.
Applications of Micro-programming
Realization of Computers:
Using microprogramming technique very fast computers
with MCU can be built.
Instruction set of the processor can be changed as per the
Very complex function (such as floating point) can be
introduced using such technique .

Refers to the use of a micro program written for one machine
to be executed in other .Older machine micro programming
can be used for modern machine.
Applications of Micro-programming

Micro diagnostics :
MP can be used for detection ,isolation and repair of
system errors. These features are known as MD.
This approach allows the system to reconfigure
itself when failure is detected.

Modifying micro routines :

A number of machines provide a writable control
memory which is implemented in RAM allows the
user to add new micro program.
Types of micro-programming
(Micro-instruction Format)
Horizontal Micro-programming:
Wide control memory word
High degree of parallel operations possible
Little encoding of control information
Types of micro-programming
(Micro-instruction Format)
Vertical Micro-programming:
Width can be much narrower
Control signals encoded into function codes need to be
More complex, more complicated to program, less flexibility
More difficult to modify
Concept of nano-programming
Concept of nano-programming
First used in Qm-1 computer designed by Nanodata corp.
In most of the processors based on the micro programmed control unit,
an instruction fetched from memory is interpreted by a micro-program.
In some machines however the microinstruction do not directly issue the
signals that controls the hardware .Memory called Nano control
Memory nCM directly controls the hardware.
In such cases there is a hierarchy of control memories with 2 levels, a
higher level is called as Micro-control memory , whose contents are
micro-instructions and the lower level nCM that stores nano-instruction.
Preparing a second control memory to hold nano-instruction is called
nano-programming. The nano-programming concept is employed in the
Motorola 680x0 microprocessor series.
Disadvantage is loss of speed due to extra memory access & more
complex control unit design.
Multiplication of two numbers
residing in memory
Architecture 1:
MULT 2:3, 5:2 where MULT is what is known as a
"complex instruction.
Architecture 2:
LOAD A, 2:3
LOAD B, 5:2
STORE 2:3, A
where "LOAD," which moves data from the
memory bank to a register,
"PROD," which finds the product of two operands
located within the registers,
"STORE," which moves data from a register to the
memory banks.
Compare both the architectures and specify their
pros and cons?
Hints:Compiler, length of the code,memory space,
more load on hardware or software,retaining
values ,pipelining
Comparing architecture 1 and 2
Architecture 1:CISC:Complex Instruction Set Computer
The compiler has to do very little work to translate a high-level language statement into
Because the length of the code is relatively short, very little RAM is required to store
Emphasis on hardware.
After a CISC-style "MULT" command is executed, the processor automatically erases the
registers. If one of the operands needs to be used for another computation, the processor
must re-load the data from the memory bank into a register.
The performance equation is given by:Execution time= Instruction count x CPI x Clock period
Since instruction count (N) is less and CPI is high. Pipelining is not that efficient.
Architecture 2:RISC:Reduced Instruction Set Computer
The compiler must perform more work to convert a high-level language statement into code
of this form.
Because there are more lines of code, more RAM is needed to store the assembly level
Emphasis on software.
In RISC, the operand will remain in the register until another value is loaded in its place.
The performance equation is given by:Execution time= Instruction count x CPI x Clock period
Since instruction count (N) is high and CPI is less. So pipelining can be done efficiently.
Architectural distinction between
RISC architecture uses separate instruction and data
caches. Their access paths are also different. CISC processor
uses a unified cache for both data and instructions; hence
uses the same path.
Mostly the RISC processors are hardwired controlled
whereas the CISC processors are micro-progammed
control. Hence control memory is needed in these
Comparison of CISC and RISC
Parameters CISC RISC
Instruction size Varies Fixed
Instruction set size Big Small
Processor design Complicated Simple
Reference architecture Uses Memory-Memory or Uses Load-Store
Register-Memory architecture(also called the
architectures Register- Register
architecture )
Instruction Execution microprogram-controlled hardwired controlled
Nature of instructions Uses powerful, complex Uses simple instructions
Compiler Simple Complicated
Pipelined Pipelining is not that Highly Pipelined
Registers Uses less number of Uses large number of
registers register sets(GPRs)
Comparison of CISC and RISC
Parameters CISC RISC
Memory references Most of the instructions Memory reference is less.
refer memory (LOAD and Only LOAD, STORE
STORE incorporated in the instructions refer memory
instruction itself)
Number of cycles per The average cycles per The average cycles per
instruction instruction is high (usually instruction is less (usually
2 to 15) 1)
Memory Space Requires less memory and Requires more memory
less instruction fetch and more instruction fetch
compared to RISC
Examples Motorola 68k , PDP -11 Apple ipod (Custom
System 360,Intel ARM 7),
x86,Pentium Iphone ( ARM 11) ,
Some Nokia & Sony
Ericsson phone