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EE273 Lecture 10
Introduction to System Timing
October 28, 1998
William J. Dally
Computer Systems Laboratory
Stanford University
billd@csl.stanford.edu
Todays Assignment
Problem Set 5
SPICE capacitively coupled RC lines
Problems 8-2, 9-2, and 9-3
Reading
Sections 9.6.1 through 9.6.5
Complete before class on Monday 11/2
A Quick Overview
Timing
The Big Picture
D Q D Q
D Q
Combinational
D Q
D Q
Logic
Was it 5 or was it 6?
Encoding Events
Clock Domains
A
tdAB 0.9
0.5
B 0.1
tr
EE273, L10, Oct 28, 1998 9
Copyright (C) by William J. Dally, All Rights Reserved
delay elements
described by
nominal delay
timing uncertainty, skew
and jitter
combinational logic
Combinational
contamination delay Logic
propagation delay
clocked storage elements
align a signal to a clock D Q
signal waits to be sampled
by a clock
output is held steady until
the next clock
Conceptually simplest D Q
clocked storage element
Samples data on rising edge
of clock
data must remain valid
during an aperture time
during sampling clk
Output is held steady until
next clock
D
output is steady until a
contamination delay after
clock
output has correct value a
Q
propagation delay after
clock
EE273, L10, Oct 28, 1998 11
Copyright (C) by William J. Dally, All Rights Reserved
D Q
late Combinational
Logic
D Q
early
Aperture time
clk
tr tu ta
Synchronous Timing
A tdAB
B
D Q D Q
tcy
Synchronous Timing
Skew and Jitter
Sources of uncertainty: D Q D Q
Synchronous Timing
Example
Suppose line is 1m long D Q D Q
Pipeline Timing
D Q D Q
D Q 90deg
tr=100ps, ta=50ps
tj=10% of active delay, ts=10% of active delay, 1% of wire delay
tdCQ=200ps, tbuf=200ps, tclk_buf=600ps
D Q D Q
D Q 90deg
Next Time
Closed-loop timing