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SEMICONDUCTOR TECHNICAL DATA by IRF530/D


 
   
 
   
NChannel EnhancementMode Silicon Gate
TMOS POWER FET
This advanced TMOS power FET is designed to withstand high 14 AMPERES
energy in the avalanche and commutation modes. This new energy 100 VOLTS
efficient design also offers a draintosource diode with a fast RDS(on) = 0.140 W
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters, and PWM motor
controls. These devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating area
are critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified D
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature G

CASE 221A09
TO-220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)

Rating Symbol Value Unit
DraintoSource Voltage VDSS 100 Vdc
DraintoGate Voltage (RGS = 1.0 M) VDGR 100 Vdc
GatetoSource Voltage Continuous VGS 20 Vdc
GatetoSource Voltage Single Pulse (tp 50 mS) VGSM 25 Vdc

Drain Current Continuous ID 14 Adc

Drain Current Continuous @ 100C ID 10
Drain Current Single Pulse (tp 10 mS) IDM 49 Apk
Total Power Dissipation @ TC = 25C PD 78 Watts
Derate above 25C 0.63 W/C

Operating and Storage Temperature Range TJ, Tstg 55 to 150 C

UNCLAMPED DRAINTOSOURCE AVALANCHE CHARACTERISTICS (TJ < 150C)

Single Pulse DraintoSource Avalanche Energy STARTING TJ = 25C EAS mJ
(VDD = 75 V, VGS = 10 V, PEAK IL = 14 A, L = 1.0 mH, RG = 25 W) 98

THERMAL CHARACTERISTICS
Thermal Resistance JunctiontoCase RJC 1.60 C/W
Thermal Resistance JunctiontoAmbient RJA 62.5
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 275 C
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
EFET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

REV 1

Motorola TMOS
Motorola, Inc. 1998 Power MOSFET Transistor Device Data 1
IRF530
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
DraintoSource Breakdown Voltage V(BR)DSS Vdc
(VGS = 0 Vdc, ID = 0.25 mAdc) 100
Temperature Coefficient (Positive) 112 V/C
Zero Gate Voltage Drain Current IDSS mAdc
(VDS = 100 Vdc, VGS = 0 Vdc) 10
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C) 100
GateBody Leakage Current IGSS nAdc
(VGS = 20 Vdc, VDS = 0 Vdc) 100

ON CHARACTERISTICS(1)
Gate Threshold Voltage Cpk 2.0(3) VGS(th) Vdc
(VDS = VGS, ID = 0.25 mA) 2.0 2.9 4.0
Threshold Temperature Coefficient (Negative) 6.2 mV/C
Static DraintoSource OnResistance Cpk 2.0(3) RDS(on) Ohms
(VGS = 10 Vdc, ID = 8.0 Adc) 0.098 0.140

DraintoSource OnVoltage VDS(on) Vdc

(VGS = 10 Vdc, ID = 14 Adc)
(VGS = 10 Vdc, ID = 8.0 Adc, TJ = 125C)
Forward Transconductance (VDS = 15 Vdc, ID = 8.0 Adc) gFS 4.0 7.4 Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance Ciss 700 800 pF
Output Capacitance (VDS = 25 Vdc,
Vdc VGS = 0 Vdc,
Vdc
Coss 200 500
f = 1.0 MHz)
Transfer Capacitance Crss 65 150

SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time td(on) 9.0 30 ns
Rise Time ((VDS = 36 Vdc,
Vd , ID = 8.0
8 0 Adc,
Ad , tr 47 75
TurnOff Delay Time VGS = 10 Vdc, RG = 15 ) td(off) 33 40
Fall Time tf 34 45
Gate Charge QT 26 40 nC

((VDS = 80 Vdc,
Vd , ID = 14 Adc,
Ad , Q1 5.0
VGS = 10 Vdc) Q2 13
Q3 11
SOURCEDRAIN DIODE CHARACTERISTICS
Forward OnVoltage VSD Vdc
(IS = 14 Adc, VGS = 0 Vdc) 0.92 1.5
(IS = 14 Adc, VGS = 0 Vdc, TJ = 125C) 0.80
Reverse Recovery Time trr 103 nS

((IS = 14 Adc,
Ad , ta 78
dIS/dt = 100 A/S) tb 25
Reverse Recovery Stored Charge QRR 0.46 mC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance Ld nH
(Measured from the drain lead 0.25 from package to center of die) 3.5

Internal Source Inductance Ls

(Measured from screw on tab to source bond pad) 7.5

(1) Pulse Test: Pulse Width 300 S, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values. Cpk + Max limit Typ
3 sigma

2 Motorola TMOS Power MOSFET Transistor Device Data

 IRF530
TYPICAL ELECTRICAL CHARACTERISTICS

30 30
9V TJ = 25C VDS 10 V TJ = 55C
VGS = 10 V 8V
25 25
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

25C 100C
7V
20 20

15 15
6V

10 10

5 5V 5

0 0
0 1 2 3 4 5 6 7 8 9 10 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9
VDS, DRAINTOSOURCE VOLTAGE (VOLTS) VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics Figure 2. Transfer Characteristics

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.20 0.14
VGS = 10 V TJ = 25C
0.18 0.13
TJ = 100C
0.16
0.12
0.14
0.12 0.11
25C VGS = 10 V
0.10 0.10
15 V
0.08 0.09
0.06
55C 0.08
0.04
0.02 0.07

0.00 0.06
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current Figure 4. OnResistance versus Drain Current
and Temperature and Gate Voltage

2.0 1000
RDS(on) , DRAINTOSOURCE RESISTANCE

VGS = 10 V VGS = 0 V
1.8
ID = 8 A TJ = 125C
1.6
1.4
I DSS , LEAKAGE (nA)

100
(NORMALIZED)

1.2 100C
1.0
0.8
10
0.6
0.4
0.2
0 1
50 25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 70 80 90 100 110
TJ, JUNCTION TEMPERATURE (C) VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Figure 6. DrainToSource Leakage

Temperature Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data 3

IRF530
POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when cal-
culating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.

2200
Ciss VDS = 0 V VGS = 0 V TJ = 25C
2000
1800
C, CAPACITANCE (pF)

1600
1400
1200 Crss
1000
Ciss
800
600
400 Coss
200 Crss
0
10 5 0 5 10 15 20 25
VGS VDS
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

4 Motorola TMOS Power MOSFET Transistor Device Data

 IRF530
10 80 100

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

TJ = 25C
9 QT 72 ID = 8 A
8 VGS 64 VDD = 36 V
Q1 Q2 VGS = 10 V tr
7 56 td(off)
6

t, TIME (ns)
48
tf
5 40 10 td(on)
4 32
3 24
2 TJ = 25C 16
ID = 14 A
1 Q3 VDS 8
0 0 1
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 1 10 100
QG, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource Figure 9. Resistive Switching Time

Voltage versus Total Charge Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

14
VGS = 0 V
12 TJ = 25C
I S , SOURCE CURRENT (AMPS)

10

0
0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define able operation, the stored energy from circuit inductance dis-
the maximum simultaneous draintosource voltage and sipated in the transistor while in avalanche must be less than
drain current that a transistor can handle safely when it is for- the rated limit and adjusted for operating conditions differing
ward biased. Curves are based upon maximum peak junc- from those specified. Although industry practice is to rate in
tion temperature and a case temperature (TC) of 25C. Peak terms of energy, avalanche energy capability is not a con-
repetitive pulsed power limits are determined by using the stant. The energy rating decreases nonlinearly with an in-
thermal response data in conjunction with the procedures crease of peak current in avalanche and peak junction
discussed in AN569, Transient Thermal ResistanceGeneral
temperature.
Data and Its Use.
Although many EFETs can withstand the stress of drain
Switching between the offstate and the onstate may tra-
verse any load line provided neither rated peak current (IDM) tosource avalanche at currents up to rated pulsed current
nor rated voltage (VDSS) is exceeded and the transition time (IDM), the energy rating is specified at rated continuous cur-
(tr,tf) do not exceed 10 s. In addition the total power aver- rent (ID), in accordance with industry custom. The energy rat-
aged over a complete switching cycle must not exceed ing must be derated for temperature as shown in the
(TJ(MAX) TC)/(RJC). accompanying graph (Figure 12). Maximum energy at cur-
A Power MOSFET designated EFET can be safely used rents below rated continuous ID can safely be assumed to
in switching circuits with unclamped inductive loads. For reli- equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data 5

 IRF530
SAFE OPERATING AREA

100 110
VGS = 20 V ID = 14 A

EAS, SINGLE PULSE DRAINTOSOURCE

100
SINGLE PULSE
10 s 90
I D , DRAIN CURRENT (AMPS)

TC = 25C

AVALANCHE ENERGY (mJ)

80
10
100 s 70
1 ms 60
50
10 ms
40
1.0 dc
30
RDS(on) LIMIT 20
THERMAL LIMIT
10
PACKAGE LIMIT
0.1 0
0.1 1.0 10 100 1000 25 50 75 100 125 150
VDS, DRAINTOSOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature

1.0
D = 0.5
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE

0.2

0.1
P(pk)
0.1 0.05 RJC(t) = r(t) RJC
0.02 D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
0.01 t1 READ TIME AT t1
t2 TJ(pk) TC = P(pk) RJC(t)
SINGLE PULSE
DUTY CYCLE, D = t1/t2

0.01
1.0E05 1.0E04 1.0E03 1.0E02 1.0E01 1.0E+00
t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta tb
TIME

tp 0.25 IS

IS

Figure 14. Diode Reverse Recovery Waveform

6 Motorola TMOS Power MOSFET Transistor Device Data

 IRF530
PACKAGE DIMENSIONS

NOTES:
SEATING 1. DIMENSIONING AND TOLERANCING PER ANSI
T PLANE
Y14.5M, 1982.
C 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
T S BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
4
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
Q A 0.570 0.620 14.48 15.75
1 2 3 B 0.380 0.405 9.66 10.28
U C 0.160 0.190 4.07 4.82
H D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73
K G 0.095 0.105 2.42 2.66
Z H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
L R N 0.190 0.210 4.83 5.33
V Q 0.100 0.120 2.54 3.04
J R 0.080 0.110 2.04 2.79
G S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
D U 0.000 0.050 0.00 1.27
N V 0.045 1.15
Z 0.080 2.04

CASE 221A09
(TO220AB)
ISSUE Z

Motorola TMOS Power MOSFET Transistor Device Data 7

IRF530

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8 IRF530/D
Motorola TMOS Power MOSFET Transistor Device Data