Opamp Lecture PDF

Lecture - 1: Operational Amplifiers
Operational Amplifiers:
The operational amplifier is a direct-coupled high gain amplifier usable from 0 to over 1MH Z to which feedback is
added to control its overall response characteristic i.e. gain and bandwidth. The op-amp exhibits the gain down to
zero frequency.
Such direct coupled (dc) amplifiers do not use blocking (coupling and by pass) capacitors since these would reduce
the amplification to zero at zero frequency. Large by pass capacitors may be used but it is not possible to fabricate
large capacitors on a IC chip. The capacitors fabricated are usually less than 20 pf. Transistor, diodes and resistors
are also fabricated on the same chip.
Differential Amplifiers:
Differential amplifier is a basic building block of an op-amp. The function of a differential amplifier is to amplify the
difference between two input signals.
How the differential amplifier is developed? Let us consider two emitter-biased circuits as shown in fig. 1.
Fig. 1
The two transistors Q1 and Q2 have identical characteristics. The resistances of the circuits are equal, i.e. R E1 = R E2,
RC1 = R C2 and the magnitude of +VCC is equal to the magnitude of VEE. These voltages are measured with respect
to ground.
To make a differential amplifier, the two circuits are connected as shown in fig. 1. The two +VCC and VEE supply
terminals are made common because they are same. The two emitters are also connected and the parallel
combination of RE1 and RE2 is replaced by a resistance RE. The two input signals v1 & v2 are applied at the base of
Q1 and at the base of Q2. The output voltage is taken between two collectors. The collector resistances are equal and
therefore denoted by RC = RC1 = RC2.
Ideally, the output voltage is zero when the two inputs are equal. When v 1 is greater then v2 the output voltage with
the polarity shown appears. When v1 is less than v2, the output voltage has the opposite polarity.
The differential amplifiers are of different configurations.

The four differential amplifier configurations are following:
1. Dual input, balanced output differential amplifier.

2. Dual input, unbalanced output differential amplifier.
3. Single input balanced output differential amplifier.
4. Single input unbalanced output differential amplifier.
Fig. 2
These configurations are shown in fig. 2, and are defined by number of input signals used and the way an output
voltage is measured. If use two input signals, the configuration is said to be dual input, otherwise it is a single input
configuration. On the other hand, if the output voltage is measured between two collectors, it is referred to as a
balanced output because both the collectors are at the same dc potential w.r.t. ground. If the output is measured at
one of the collectors w.r.t. ground, the configuration is called an unbalanced output.
A multistage amplifier with a desired gain can be obtained using direct connection between successive stages of
differential amplifiers. The advantage of direct coupling is that it removes the lower cut off frequency imposed by the
coupling capacitors, and they are therefore, capable of amplifying dc as well as ac input signals.
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Lecture -1: Operational Amplifiers
Dual Input, Balanced Output Differential Amplifier:
The circuit is shown in fig. 1, v1 and v2 are the two inputs, applied to the bases of Q1 and Q2 transistors.
The output voltage is measured between the two collectors C1 and C2 , which are at same dc potentials.
D.C. Analysis:
To obtain the operating point (ICC and VCEQ) for differential amplifier dc equivalent circuit is drawn
by reducing the input voltages v1 and v2 to zero as shown in fig. 3.
Fig. 3
The internal resistances of the input signals are denoted by RS because RS1= RS2. Since both emitter
biased sections of the different amplifier are symmetrical in all respects, therefore, the operating point
for only one section need to be determined. The same values of ICQ and VCEQ can be used for second
transistor Q2.
Applying KVL to the base emitter loop of the transistor Q1.

The value of RE sets up the emitter current in transistors Q1 and Q2 for a given value of VEE. The
emitter current in Q1and Q2 are independent of collector resistance RC.
The voltage at the emitter of Q1 is approximately equal to -VBE if the voltage drop across R is
negligible. Knowing the value of IC the voltage at the collector VCis given by
VC =VCC IC RC
and VCE = VC VE
= VCC IC RC + VBE
VCE = VCC + VBE ICRC (E-2)
From the two equations VCEQ and ICQ can be determined. This dc analysis applicable for all types of
differential amplifier.
Example - 1
The following specifications are given for the dual input, balanced-output differential amplifier of fig.1:
RC = 2.2 k, RB = 4.7 k, Rin 1 = Rin 2 = 50 , +VCC = 10V, -VEE = -10 V, dc =100 and VBE =
0.715V.
Determine the operating points (ICQ and VCEQ) of the two transistors.
Solution:
The value of ICQ can be obtained from equation (E-1).

The voltage VCEQ can be obtained from equation (E-2).
The values of ICQ and VCEQ are same for both the transistors.
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Dual Input, Balanced Output Difference Amplifier:
The circuit is shown in fig. 1 v1 and v2 are the two inputs, applied to the bases of Q1 and Q2 transistors.
The output voltage is measured between the two collectors C1 and C2, which are at same dc potentials.
Fig. 1
A.C. Analysis :
In previous lecture dc analysis has been done to obtain the operatiing point of the two transistors.
To find the voltage gain Ad and the input resistance Ri of the differential amplifier, the ac equivalent
circuit is drawn using r-parameters as shown in fig. 2. The dc voltages are reduced to zero and the ac
equivalent of CE configuration is used.
Fig. 2
Since the two dc emitter currents are equal. Therefore, resistance r'e1 and r'e2 are also equal and
designated by r'e . This voltage across each collector resistance is shown 180 out of phase with respect
to the input voltages v1 and v2. This is same as in CE configuration. The polarity of the output voltage is
shown in Figure. The collector C2 is assumed to be more positive with respect to collector C1 even
though both are negative with respect to to ground.
Applying KVL in two loops 1 & 2.
Substituting current relations,
Again, assuming RS1 / b and RS2 / b are very small in comparison with RE and re' and therefore
neglecting these terms,
Solving these two equations, ie1 and ie2 can be calculated.
The output voltage VO is given by
VO = VC2 - VC1
= -RC iC2 - (-RC iC1)
= RC (iC1 - iC2)
= RC (ie1 - ie2)
Substituting ie1, & ie2 in the above expression
Thus a differential amplifier amplifies the difference between two input signals. Defining the difference
of input signals as vd = v1 v2 the voltage gain of the dual input balanced output differential amplifier
can be given by
(E-2)
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Differential Input Resistance:
Differential input resistance is defined as the equivalent resistance that would be measured at either
input terminal with the other terminal grounded. This means that the input resistance Ri1 seen from the
input signal source v1 is determined with the signal source v2 set at zero. Similarly, the input signal v1 is
set at zero to determine the input resistance Ri2 seen from the input signal source v2. Resistance
RS1 and RS2 are ignored because they are very small.
Substituting ie1,
Similarly,
The factor of 2 arises because the re' of each transistor is in series.
To get very high input impedance with differential amplifier is to use Darlington transistors. Another
ways is to use FET.
Output Resistance:
Output resistance is defined as the equivalent resistance that would be measured at output terminal with
respect to ground. Therefore, the output resistance RO1 measured between collector C1 and ground is
equal to that of the collector resistance RC. Similarly the output resistance RO2 measured at C2 with
respect to ground is equal to that of the collector resistor RC.
RO1 = RO2 = RC (E-5)
The current gain of the differential amplifier is undefined. Like CE amplifier the differential amplifier is
a small signal amplifier. It is generally used as a voltage amplifier and not as current or power amplifier.
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Example - 1
The following specifications are given for the dual input, balanced-output differential amplifier: RC =
2.2 k, RB = 4.7 k, Rin 1 = Rin 2 = 50, +VCC= 10V, -VEE = -10 V, dc =100 and VBE = 0.715V.
a. Determine the voltage gain.

b. Determine the input resistance
c. Determine the output resistance.
Solution:
(a). The parameters of the amplifiers are same as discussed in example-1 of lecture-1. The operating
point of the two transistors obtained in lecture-1 are given below
ICQ = 0.988 mA
VCEQ=8.54V
The ac emitter resistance
Therefore, substituting the known values in voltage gain equation (E-2), we obtain
b). The input resistance seen from each input source is given by (E-3) and (E-4):
(c) The output resistance seen looking back into the circuit from each of the two output terminals is
given by (E-5)
Ro1 = Ro2 = 2.2 k
Example - 2
For the dual input, balanced output differential amplifier of Example-1:
a. Determine the output voltage (vo) if vin 1 = 50mV peak to peak (pp) at 1 kHz and vin
2 = 20 mV pp at 1 kHz.
b. What is the maximum peal to peak output voltage without clipping?
Solution:
(a) In Example-1 we have determined the voltage gain of the dual input, balanced output differential
amplifier. Substituting this voltage gain (Ad = 86.96) and given values of input voltages in (E-1), we get
(b) Note that in case of dual input, balanced output difference amplifier, the output voltage vo is
measured across the collector. Therefore, to calculate the maximum peak to peak output voltage, we
need to determine the voltage drop across each collector resistor:
Substituting IC = ICQ = 0.988 mA, we get
This means that the maximum change in voltage across each collector resistor is 2.17 (ideally) or 4.34
VPP. In other words, the maximum peak to peak output voltage with out clipping is (2) (4.34) = 8.68
VPP.
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Lecture - 3: Difference Amplifiers
A dual input, balanced output difference amplifier circuit is shown in fig. 1.
Fig. 1
Inverting & Non inverting Inputs:
In differential amplifier the output voltage vO is given by
VO = Ad (v1 v2)
When v2 = 0, vO = Ad v1
& when v1 = 0, vO = - Ad v2
Therefore the input voltage v1 is called the non inventing input because a positive voltage v1 acting
alone produces a positive output voltage vO. Similarly, the positive voltage v2 acting alone produces a
negative output voltage hence v2is called inverting input. Consequently B1 is called noninverting input
terminal and B2 is called inverting input terminal.
Common mode Gain:
A common mode signal is one that drives both inputs of a differential amplifier equally. The common
mode signal is interference, static and other kinds of undesirable pickup etc.
The connecting wires on the input bases act like small antennas. If a differential amplifier is operating in
an environment with lot of electromagnetic interference, each base picks up an unwanted interference
voltage. If both the transistors were matched in all respects then the balanced output would be
theoretically zero. This is the important characteristic of a differential amplifier. It discriminates against
common mode input signals. In other words, it refuses to amplify the common mode signals.
The practical effectiveness of rejecting the common signal depends on the degree of matching between
the two CE stages forming the differential amplifier. In other words, more closely are the currents in the
input transistors, the better is the common mode signal rejection e.g. If v1 and v2 are the two input
signals, then the output of a practical op-amp cannot be described by simply
v0 = Ad (v1 v2 )
In practical differential amplifier, the output depends not only on difference signal but also upon the
common mode signal (average).
vd = (v1 vd )
and vC = (v1 + v2 )
The output voltage, therefore can be expressed as
vO = A1 v1 + A2 v2
Where A1 & A2 are the voltage amplification from input 1(2) to output under the condition that input 2
(1) is grounded.
The voltage gain for the difference signal is Ad and for the common mode signal is AC.
The ability of a differential amplifier to reject a common mode signal is expressed by its common mode
rejection ratio (CMRR). It is the ratio of differential gain Ad to the common mode gain AC.
Date sheet always specify CMRR in decibels CMRR = 20 log CMRR.
Therefore, the differential amplifier should be designed so that r is large compared with the ratio of the
common mode signal to the difference signal. If r = 1000, vC = 1mV, vd = 1 m V, then
It is equal to first term. Hence for an amplifier with r = 1000, a 1m V difference of potential between two
inputs gives the same output as 1mV signal applied with the same polarity to both inputs.
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Dual Input, Unbalanced Output Differential Amplifier:
In this case, two input signals are given however the output is measured at only one of the two-collector
w.r.t. ground as shown in fig. 2. The output is referred to as an unbalanced output because the collector
at which the output voltage is measured is at some finite dc potential with respect to ground..
Fig. 2
In other words, there is some dc voltage at the output terminal without any input signal applied. DC
analysis is exactly same as that of first case.
AC Analysis:
The output voltage gain in this case is given by
The voltage gain is half the gain of the dual input, balanced output differential amplifier. Since at the
output there is a dc error voltage, therefore, to reduce the voltage to zero, this configuration is normally
followed by a level translator circuit.
Differential amplifier with swamping resistors:
By using external resistors R'E in series with each emitter, the dependence of voltage gain on variations
of r'e can be reduced. It also increases the linearity range of the differential amplifier.
Fig. 3, shows the differential amplifier with swamping resistor R'E. The value of R'E is usually large
enough to swamp the effect of r'e.
Fig. 3
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Example-1
Consider example-1 of lecture-2. The specifications are given again for the dual input, unbalanced-
output differential amplifier: RC = 2.2 k, RB= 4.7 k, Rin1 = Rin2= 50, +VCC = 10V, -VEE= -10 V,
dc =100 and VBE= 0.715V.
Determine the voltage gain, input resistance and the output resistance.
Solution:
Since the component values remain unchanged and the biasing arrangement is same, the ICQ and
VCEQ values as well as input and output resistance values for the dual input, unbalanced output
configuration must be the same as those for the dual input, balanced output configuration.
Thus, ICQ = 0.988 mA

VCEQ = 8.54 V
Ri1 = Ri2 = 5.06 k
Ro = 2.2 k
The voltage gain of the dual input, unbalanced output differential amplifier is given by
Example-2
Repeat Example-1 for single input, balanced output differential amplifier.
Solution:
Because the same biasing arrangement and same component values are used in both configurations, the
results obtained in Example-1 for the dual input, balanced output configuration are also valid for the
single input, balanced output configuration.
That is,
ICQ= 0.988 mA
VCEQ = 8.54 V
Vd = 86.96
Ri = 5.06 k
Ro1 = Ro2 = 2.2 k
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Lecture - 4: Biasing of Differential Amplifiers
Constant Current Bias:
In the dc analysis of differential amplifier, we have seen that the emitter current IE depends upon the
value of bdc. To make operating point stable IE current should be constant irrespective value of bdc.
For constant IE, RE should be very large. This also increases the value of CMRR but if RE value is
increased to very large value, IE (quiescent operating current) decreases. To maintain same value of IE,
the emitter supply VEE must be increased. To get very high value of resistance RE and constant IE,
current, current bias is used.
Figure 5.1
Fig. 1, shows the dual input balanced output differential amplifier using a constant current bias. The
resistance RE is replace by constant current transistor Q3. The dc collector current in Q3 is established
by R1, R2, & RE.
Applying the voltage divider rule, the voltage at the base of Q3 is
Because the two halves of the differential amplifiers are symmetrical, each has half of the current IC3.
The collector current, IC3 in transistor Q3 is fixed because no signal is injected into either the emitter or
the base of Q3.
Besides supplying constant emitter current, the constant current bias also provides a very high source
resistance since the ac equivalent or the dc source is ideally an open circuit. Therefore, all the
performance equations obtained for differential amplifier using emitter bias are also valid.
As seen in IE expressions, the current depends upon VBE3. If temperature changes, VBE changes and
current IE also changes. To improve thermal stability, a diode is placed in series with resistance R1as
shown in fig. 2.
Fig. 2
This helps to hold the current IE3 constant even though the temperature changes. Applying KVL to the
base circuit of Q3.
Therefore, the current IE3 is constant and independent of temperature because of the added diode D.
Without D the current would vary with temperature because VBE3 decreases approximately by 2mV/
C. The diode has same temperature dependence and hence the two variations cancel each other and
IE3 does not vary appreciably with temperature. Since the cut in voltage VD of diode approximately
the same value as the base to emitter voltage VBE3of a transistor the above condition cannot be satisfied
with one diode. Hence two diodes are used in series for VD. In this case the common mode gain reduces
to zero.
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Some times zener diode may be used in place of diodes and resistance as
shown in fig. 3. Zeners are available over a wide range of voltages and
can have matching temperature coefficient
The voltage at the base of transistor QB is
Fig. 3
The value of R2 is selected so that I2 1.2 IZ(min) where IZ is the minimum current required to cause
the zener diode to conduct in the reverse region, that is to block the rated voltage VZ.
Current Mirror:
The circuit in which the output current is forced to equal the input current is said to be a current mirror
circuit. Thus in a current mirror circuit, the output current is a mirror image of the input current. The
current mirror circuit is shown in fig. 4.
Fig. 4
Once the current I2 is set up, the current IC3 is automatically established to be nearly equal to I2. The
current mirror is a special case of constant current bias and the current mirror bias requires of constant
current bias and therefore can be used to set up currents in differential amplifier stages. The current
mirror bias requires fewer components than constant current bias circuits.
Since Q3 and Q4 are identical transistors the current and voltage are approximately same
For satisfactory operation two identical transistors are necessary.
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Example - 1
Design a zener constant current bias circuit as

shown in fig. 5 according to the following
specifications.
(a). Emitter current -IE = 5 mA
(b). Zener diode with Vz = 4.7 V and Iz = 53
mA.
(c). ac = dc = 100, VBE = 0.715V
(d). Supply voltage - VEE = - 9 V.
Solution:
From fig. 6 using KVL we get
Fig. 5
Practically we use RE = 820 k
Practically we use R2 = 68
The designed component values are:
RE = 860
R2 = 68 Fig. 6
Example - 2
Design the dual-input balanced output differential amplifier using the diode constant current bias to meet the following
specifications.
1. supply voltage = 12 V.
2. Emitter current IE in each differential amplifier transistor = 1.5 mA.
3. Voltage gain 60.
Solution:
The voltage at the base of transistor Q3 is
Assuming that the transistor Q3 has the same

characteristics as diode D1 and D2 that is
VD = VBE3, then
Fig. 7
Practically we take RE = 240 .
Practically we take R2 = 3.6 k.
To obtain the differential gain of 60, the

required value of the collector resistor is
The following fig. 7 shows the dual input,

balanced output differential amplifier with
the designed component values as RC = 1K,
RE = 240 , and R2 = 3.6K.
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Lecture - 5: The Operational Amplifiers
The operation amplifier:
An operational amplifier is a direct coupled high gain amplifier consisting of one or more differential
(OPAMP) amplifiers and followed by a level translator and an output stage. An operational amplifier is
available as a single integrated circuit package.
The block diagram of OPAMP is shown in fig. 1.
Fig. 1
The input stage is a dual input balanced output differential amplifier. This stage provides most of the
voltage gain of the amplifier and also establishes the input resistance of the OPAMP.The intermediate
stage of OPAMP is another differential amplifier which is driven by the output of the first stage. This is
usually dual input unbalanced output.
Because direct coupling is used, the dc voltage level at the output of intermediate stage is well above
ground potential. Therefore level shifting circuit is used to shift the dc level at the output downward to
zero with respect to ground. The output stage is generally a push pull complementary amplifier. The
output stage increases the output voltage swing and raises the current supplying capability of the
OPAMP
. It also
Level Translator: provides
low
Because of the direct coupling the dc level at the emitter rises from output
stages to stage. This increase in dc level tends to shift the operating resistan
point of the succeeding stages and therefore limits the output voltage ce.
swing and may even distort the output signal.
To shift the output dc level to zero, level translator circuits are used.
An emitter follower with voltage divider is the simplest form of level
translator as shown in fig. 2.
Thus a dc voltage at the base of Q produces 0V dc at the output. It is

decided by R1 and R2. Instead of voltage divider emitter follower
either with diode current bias or current mirror bias as shown in fig.
3 may be used to get better results.
In this case, level shifter, which is common collector amplifier, shifts

the level by 0.7V. If this shift is not sufficient, the output may be taken
at the junction of two resistors in the emitter leg. Fig. 2
Fig. 3
Fig. 4, shows a complete OPAMP circuit having input different amplifiers with balanced output,
intermediate stage with unbalanced output, level shifter and an output amplifier.
Fig. 4
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Example-1:
For the cascaded differential amplifier shown in fig. 5, determine:
The collector current and collector to emitter voltage for each transistor.
The overall voltage gain.
The input resistance.
The output resistance.
Assume that for the transistors used hFE = 100 and VBE = 0.715V
Fig. 5
Solution:
(a). To determine the collector current and collector to emitter voltage of transistors Q1 and Q2, we
assume that the inverting and non-inverting inputs are grounded. The collector currents (IC IE) in
Q1 and Q2 are obtained as below:
That is, IC1 = IC2 =0.988 mA.
Now, we can calculate the voltage between collector and emitter for Q1 and Q2 using the collector
current as follows:
VC1 = VCC = -RC1 IC1 = 10 (2.2k) (0.988 mA) = 7.83 V = VC2
Since the voltage at the emitter of Q1 and Q2 is -0.715 V,
VCE1 = VCE2 = VC1 -VE1 = 7.83 + 0715 = 8.545 V
Next, we will determine the collector current in Q3 and Q4 by writing the Kirchhoff's voltage equation
for the base emitter loop of the transistor Q3:
VCC RC2 IC2 = VBE3 - R'E IC3 - RE2 (2 IE3) + VBE= 0

10 (2.2k) (0.988mA) - 0.715 - (100) (IE3) (30k) IE3 + 10=0
10 - 2.17 - 0.715 + 10 - (30.1k) IE3 = 0
Hence the voltage at the collector of Q3 and Q4 is
VC3 = VC4= VCC RC3 IC3 = 10 (1.2k) (0.569 mA)
= 9.32 V
Therefore,
VCE3 = VVCE4 = VC3 VE3 = 9.32 7.12 = 2.2 V
Thus, for Q1 and Q2:

ICQ = 0.988 mA
VCEQ = 8.545 V
and for Q3 and Q4:
ICQ = 0.569 mA
VCEQ = 2.2 V
[Note that the output terminal (VC4) is at 9.32 V and not at zero volts.]
(b). First, we calculate the ac emitter resistance r'e of each stage and then its voltage gain.
The first stage is a dual input, balanced output differential amplifier, therefore, its voltage gain is
Where
Ri2 = input resistance of the second stage
The second stage is dual input, unbalanced output differential amplifier with swamping resistor R'E, the
voltage gain of which is
Hence the overall voltage gain is
Ad= (Ad1) (Ad2) = (80.78) (4.17) = 336.85
Thus we can obtain a higher voltage gain by cascading differential amplifier stages.
(c).The input resistance of the cascaded differential amplifier is the same as the input resistance of the
first stage, that is
Ri = 2ac(re1) = (200) (25.3) = 5.06 k
(d). The output resistance of the cascaded differential amplifier is the same as the output resistance of
the last stage. Hence,
RO = RC = 1.2 k
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Example-2:
For the circuit show in fig. 6, it is given that =100, VBE =0715V. Determine
The dc conditions for each state

The overall voltage gain
The maximum peak to peak output voltage swing.
Fig. 6
Solution:
(a). The base currents of transistors are neglected and VBE drops of all transistors are assumed same.
From the dc equivalent circuit,
and
b) The overall voltage gain of the amplifier can be obtained as below:
Therefore, voltage gain of second stage
The input impedance of second stage is
The effective load resistance for first stage is
Therefore, the voltage gain of first stage is

The overall voltge gain is AV = AV1 AV2
(c). The maximum peak to peak output votage swing = Vopp = 2 (VC7 - VE7)
= 2 x (5.52 - 3.325)
= 4.39 V
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Lecture - 6: Practical Operational Amplifier
The symbolic diagram of an OPAMP is shown in fig. 1.
741c is most commonly used OPAMP available in IC package. It is an 8-pin DIP chip.
Parameters of OPAMP:
The various important parameters of OPAMP are follows:
1.Input Offset Voltage:
Input offset voltage is defined as the voltage

that must be applied between the two input
terminals of an OPAMP to null or zero the
output fig. 2, shows that two dc voltages are
applied to input terminals to make the output
zero.
Vio = Vdc1 Vdc2
Vdc1 and Vdc2 are dc voltages and

RSrepresents the source resistance. Vio is the
difference of Vdc1 and Vdc2. It may be positive
or negative. For a 741C OPAMP the maximum
value of Vio is 6mV. It means a voltage 6 mV
is required to one of the input to reduce the
output offset voltage to zero. The smaller the Fig. 2
input offset voltage the better the differential
amplifier, because its transistors are more
closely matched.
2. Input offset Current:
The input offset current Iio is the difference between the currents into inverting and non-inverting
terminals of a balanced amplifier.
Iio = | IB1 IB2 |
The Iio for the 741C is 200nA maximum. As the matching between two input terminals is improved, the
difference between IB1 and IB2 becomes smaller, i.e. the Iio value decreases further.For a precision
OPAMP 741C, Iio is 6 nA
3.Input Bias Current:
The input bias current IB is the average of the current entering the input terminals of a balanced
amplifier i.e.
IB = (IB1 + IB2 ) / 2
For 741C IB(max) = 700 nA and for precision 741C IB = 7 nA
4. Differential Input Resistance: (Ri)
Ri is the equivalent resistance that can be measured at either the inverting or non-inverting input
terminal with the other terminal grounded. For the 741C the input resistance is relatively high 2 M.
For some OPAMP it may be up to 1000 G ohm.
5. Input Capacitance: (Ci)
Ci is the equivalent capacitance that can be measured at either the inverting and noninverting terminal
with the other terminal connected to ground. A typical value of Ci is 1.4 pf for the 741C.
6. Offset Voltage Adjustment Range:
741 OPAMP have offset voltage null capability. Pins 1 and 5 are marked offset null for this purpose. It
can be done by connecting 10 K ohm pot between 1 and 5 as shown in fig. 3.
Fig. 3
By varying the potentiometer, output offset voltage (with inputs grounded) can be reduced to zero volts.
Thus the offset voltage adjustment range is the range through which the input offset voltage can be
adjusted by varying 10 K pot. For the 741C the offset voltage adjustment range is 15 mV.
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7. Input Voltage Range :
Input voltage range is the range of a common mode input signal for which a differential amplifier
remains linear. It is used to determine the degree of matching between the inverting and noninverting
input terminals. For the 741C, the range of the input common mode voltage is 13V maximum. This
means that the common mode voltage applied at both input terminals can be as high as +13V or as low
as 13V.
8. Common Mode Rejection Ratio (CMRR).
CMRR is defined as the ratio of the differential voltage gain Ad to the common mode voltage gain ACM
CMRR = Ad / ACM.
For the 741C, CMRR is 90 dB typically. The higher the value of CMRR the better is the matching
between two input terminals and the smaller is the output common mode voltage.
9. Supply voltage Rejection Ratio: (SVRR)
SVRR is the ratio of the change in the input offset voltage to the corresponding change in power supply
voltages. This is expressed in m V / V or in decibels, SVRR can be defined as
SVRR = D Vio / D V
Where D V is the change in the input supply voltage and D Vio is the corresponding change in the offset
voltage.
For the 741C, SVRR = 150 V / V.
For 741C, SVRR is measured for both supply magnitudes increasing or decreasing simultaneously, with
R3 10K. For same OPAMPS, SVRR is separately specified as positive SVRR and negative SVRR.
10. Large Signal Voltage Gain:
Since the OPAMP amplifies difference voltage between two input terminals, the voltage gain of the
amplifier is defined as
Because output signal amplitude is much large than the input signal the voltage gain is commonly called
large signal voltage gain. For 741C is voltage gain is 200,000 typically.
11. Output voltage Swing:
The ac output compliance PP is the maximum unclipped peak to peak output voltage that an OPAMP
can produce. Since the quiescent output is ideally zero, the ac output voltage can swing positive or
negative. This also indicates the values of positive and negative saturation voltages of the OPAMP. The
output voltage never exceeds these limits for a given supply voltages +VCC and VEE. For a 741C it is
13 V.
12. Output Resistance: (RO)
RO is the equivalent resistance that can be measured between the output terminal of the OPAMP and
the ground. It is 75 ohm for the 741C OPAMP.
Example - 1
Determine the output voltage in each of the following cases for the open loop differential amplifier of fig.
4:
a. vin 1 = 5 m V dc, vin 2 = -7 Vdc

b. vin 1 = 10 mV rms, vin 2= 20 mV rms
Fig. 4
Specifications of the OPAMP are given below:

A = 200,000, Ri = 2 M , R O = 75, + VCC = + 15 V, - VEE = - 15 V, and output voltage swing =
14V.
Solution:
(a). The output voltage of an OPAMP is given by
Remember that vo = 2.4 V dc with the assumption that the dc output voltage is zero when the input
signals are zero.
(b). The output voltage equation is valid for both ac and dc input signals. The output voltage is given by
Thus the theoretical value of output voltage vo = -2000 V rms. However, the OPAMP saturates at 14
V. Therefore, the actual output waveform will be clipped as shown fig. 5. This non-sinusoidal waveform
is unacceptable in amplifier applications.
Fig. 5
13. Output Short circuit Current :
In some applications, an OPAMP may drive a load resistance that is approximately zero. Even its output
impedance is 75 ohm but cannot supply large currents. Since OPAMP is low power device and so its
output current is limited. The 741C can supply a maximum short circuit output current of only 25mA.
14. Supply Current :
IS is the current drawn by the OPAMP from the supply. For the 741C OPAMP the supply current is 2.8
m A.
15. Power Consumption:
Power consumption (PC) is the amount of quiescent power (vin= 0V) that must be consumed by the
OPAMP in order to operate properly. The amount of power consumed by the 741C is 85 m W.
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16. Gain Bandwidth Product:
The gain bandwidth product is the bandwidth of the OPAMP when the open loop voltage gain is
reduced to 1. From open loop gain vs frequency graph At 1 MHz shown in. fig. 6, It can be found 1 MHz
for the 741C OPAMP frequency the gain reduces to 1. The mid band voltage gain is 100, 000 and cut off
frequency is 10Hz.
Fig. 6
17. Slew Rate:
Slew rate is defined as the maximum rate of change of output voltage per unit of time under large signal
conditions and is expressed in volts / m secs.
To understand this, consider a charging current of a capacitor shown in fig. 7.

Fig. 6
If 'i' is more, capacitor charges quickly. If 'i' is limited to Imax, then rate of change is also limited.
Slew rate indicates how rapidly the output of an OPAMP can change in response to changes in the input
frequency with input amplitude constant. The slew rate changes with change in voltage gain and is
normally specified at unity gain.
If the slope requirement is greater than the slew rate, then distortion occurs. For the 741C the slew rate
is low 0.5 V / m S. which limits its use in higher frequency applications.
18. Input Offset Voltage and Current Drift:
It is also called average temperature coefficient of input offset voltage or input offset current. The input
offset voltage drift is the ratio of the change in input offset voltage to change in temperature and
expressed in m V / C. Input offset voltage drift = ( D Vio / D T).
Similarly, input offset current drift is the ratio of the change in input offset current to the change in
temperature. Input offset current drift = ( D Iio / D T).
For 741C,
D Vio / D T = 0.5 m V / C.
D Iio/ D T = 12 pA / C.
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Lecture - 7: Parameters of an OPAMP
Example - 1
A 100 PF capacitor has a maximum charging current of 150 A. What is the slew rate?
Solution:
C = 100 PF=100 x 10-12 F

I = 150 A = 150 x 10-6 A
Slew rate is 1.5 V / s.
Example - 2
An operational amplifier has a slew rate of 2 V / s. If the peak output is 12 V, what is the power
bandwidth?
Solution:
The slew rate of an operational amplifier is
As for output free of distribution, the slews determines the maximum frequency of operation fmax for a
desired output swing.
so
So bandwidth = 26.5 kHz.
Example - 3
For the given circuit in fig. 1. Iin(off) = 20 nA. If Vin(off) = 0, what is the differential input voltage?. If A
= 105, what does the output offset voltage equal?
Fig. 1
Solutin:
Iin(off) = 20 nA
Vin(off) = 0
(i) The differential input voltage = Iin(off) x 1k = 20 nA x 1 k = 20 V
(ii) If A = 105 then the output offset voltage Vin(off) = 20 V x 105 = 2 volt
Output offset voltage = 2 volts.
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Lecture - 7: Parameters of an OPAMP
Example - 4
R1 = 100, Rf = 8.2 k, RC = 10 k. Assume that the amplifier is nulled at 25C. If Vin is 20 mV peak sine
wave at 100 Hz. Calculate Er, and Vo values at 45C for the circuit shown in fig. 2.
Fig. 2
Solution:
The change in temperature T = 45 - 25 = 20C.
Error voltage = 51.44 mV

Output voltage is 1640 mV peak ac signal which rides either on a +51.44 mV or -51.44 mV dc level.
Example - 5
Design an input offset voltage compensating network for the operational amplifier A 715 for the circuit
shown in fig. 3. Draw the complete circuit diagram.
Fig. 3
Solution:
From data sheet we get vin = 5 mV for the operational amplifier A 715.
V = | VCC | = | - VEE | = 15 V
Now,
If we select RC = 10, the value of Rb should be

Rb = (3000) RC = 30000 = 304
Since R > Rmax, let RS = 10 Rmax where Rmax = Ra / 4. Therefore,
If a 124 potentiometer is not available, we may prefer to use to the next lower value avilable, such as
104, so that the value of Ra will be larger than Rb by a factor of 10. If we select a 10 k potentiometer
a s the Ra value, Rb is 12 times larger than Ra, Thus
Ra = 10 k potentiometer
Rb = 30 k
Rc = 10.
The final circuit, which also includes the pin connections for the A 715, shown in fig. 4.
Fig. 4
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Lecture -7: Parameters of an OPAMP
The ideal OPAMP :
An ideal OPAMP would exhibit the following electrical characteristic.
1. Infinite voltage gain Ad

2. Infinite input resistance Ri, so that almost any signal source can drive it and there is no
loading of the input source.
3. Zero output resistance RO, so that output can drive an infinite number of other devices.
4. Zero output voltage when input voltage is zero.
5. Infinite bandwidth so that any frequency signal from 0 to infinite Hz can be amplified
without attenuation.
6. Infinite common mode rejection ratio so that the output common mode noise voltage is
zero.
7. Infinite slew rate, so that output voltage changes occur simultaneously with input
voltage changes.
There are practical OPAMPs that can be made to approximate some of these characters using a
negative feedback arrangement.
Equivalent Circuit of an OPAMP:
Fig. 5, shows an equivalent circuit of an OPAMP. v1 and v2are the two input voltage voltages. Ri is the
input impedance of OPAMP. Ad Vd is an equivalent Thevenin voltage source and RO is the Thevenin
equivalent impedance looking back into the terminal of an OPAMP.
Fig. 5
This equivalent circuit is useful in analyzing the basic operating principles of OPAMP and in observing
the effects of standard feedback arrangements
vO = Ad (v1 v2) = Ad vd.
This equation indicates that the output voltage vO is directly proportional to the algebraic difference
between the two input voltages. In other words the OPAMP amplifies the difference between the two
input voltages. It does not amplify the input voltages themselves. The polarity of the output voltage
depends on the polarity of the difference voltage vd.
Ideal Voltage Transfer Curve:
The graphic representation of the output equation is shown in fig. 6 in which the output voltage vO is
plotted against differential input voltage vd, keeping gain Ad constant.
Fig. 6
The output voltage cannot exceed the positive and negative saturation voltages. These saturation
voltages are specified for given values of supply voltages. This means that the output voltage is directly
proportional to the input difference voltage only until it reaches the saturation voltages and thereafter
the output voltage remains constant.
Thus curve is called an ideal voltage transfer curve, ideal because output offset voltage is assumed to be
zero. If the curve is drawn to scale, the curve would be almost vertical because of very large values of
Ad.
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Lecture - 8: Open loop OPAMP Configuration
Open loop OPAMP Configuration:
In the case of amplifiers the term open loop indicates that no connection, exists between input and
output terminals of any type. That is, the output signal is not fedback in any form as part of the input
signal.
In open loop configuration, The OPAMP functions as a high gain amplifier. There are three open loop
OPAMP configurations.
The Differential Amplifier:
Fig. 1, shows the open loop differential amplifier in which input signals vin1 and vin2 are applied to the
positive and negative input terminals.
Fig. 1
Since the OPAMP amplifies the difference the between the two input signals, this configuration is called
the differential amplifier. The OPAMP amplifies both ac and dc input signals. The source resistance
Rin1 and Rin2 are normally negligible compared to the input resistance Ri. Therefore voltage drop
across these resistances can be assumed to be zero.
Therefore
v1 = vin1 and v2 = vin2.
vo = Ad (vin1 vin2 )
where, Ad is the open loop gain.
The Inverting Amplifier:
If the input is applied to only inverting terminal and non-inverting terminal is grounded then it is called
inverting amplifier.This configuration is shown in fig. 2.
v1= 0, v2 = vin.
vo = -Ad vin
Fig. 2
The negative sign indicates that the output voltage is out of phase with respect to input 180 or is of
opposite polarity. Thus the input signal is amplified and inverted also.
The non-inverting amplifier:
In this configuration, the input voltage is applied to non-inverting terminals and inverting terminal is
ground as shown in fig. 3.
v1 = +vin v2 = 0
vo = +Ad vin
This means that the input voltage is amplified by Ad and there is no phase reversal at the output.
Fig. 3
In all there configurations any input signal slightly greater than zero drive the output to saturation level.
This is because of very high gain. Thus when operated in open-loop, the output of the OPAMP is either
negative or positive saturation or switches between positive and negative saturation levels. Therefore
open loop op-amp is not used in linear applications.
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Closed Loop Amplifier:
The gain of the OPAMP can be controlled if fedback is introduced in the circuit. That is, an output
signal is fedback to the input either directly or via another network. If the signal fedback is of opposite
or out phase by 180 with respect to the input signal, the feedback is called negative fedback.
An amplifier with negative fedback has a self-correcting ability of change in output voltage caused by
changes in environmental conditions. It is also known as degenerative fedback because it reduces the
output voltage and,in tern,reduces the voltage gain.
If the signal is fedback in phase with the input signal, the feedback is called positive feedback. In positive
feedback the feedback signal aids the input signal. It is also known as regenerative feedback. Positive
feedback is necessary in oscillator circuits.
The negative fedback stabilizes the gain, increases the bandwidth and changes, the input and output
resistances. Other benefits are reduced distortion and reduced offset output voltage. It also reduces the
effect of temperature and supply voltage variation on the output of an op-amp.
A closed loop amplifier can be represented by two blocks one for an OPAMP and other for a feedback
circuits. There are four following ways to connect these blocks. These connections are shown in fig. 4.
These connections are classified according to whether the voltage or current is feedback to the input in
series or in parallel:
Voltage series feedback

Voltage shunt feedback
Current series feedback
Current shunt feedback
Fig. 4
In all these circuits of fig. 4, the signal direction is from input to output for OPAMP and output to input
for feedback circuit. Only first two, feedback in circuits are important.
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Voltage series feedback:
It is also called non-inverting voltage feedback circuit. With this type of feedback, the input signal drives
the non-inverting input of an amplifier; a fraction of the output voltage is then fed back to the inverting
input. The op-amp is represented by its symbol including its large signal voltage gain Ad or A, and the
feedback circuit is composed of two resistors R1 and Rf. as shown in fig. 5
Fig. 5
The feedback voltage always opposes the input voltage, (or is out of phase by 180 with respect to input
voltage), hence the feedback is said to be negative.
The closed loop voltage gain is given by
The product A and B is called loop gain. The gain loop gain is very large such that AB >> 1
This shows that overall voltage gain of the circuit equals the reciprocal of B, the feedback gain. It means
that closed loop gain is no longer dependent on the gain of the op-amp, but depends on the feedback of
the voltage divider. The feedback gain B can be precisely controlled and it is independent of the
amplifier.
Physically, what is happening in the circuit? The gain is approximately constant, even though
differential voltage gain may change. Suppose A increases for some reasons (temperature change). Then
the output voltage will try to increase. This means that more voltage is fedback to the inverting input,
causing vd voltage to decrease. This almost completely offset the attempted increases in output voltage.
Similarly, if A decreases, The output voltage decreases. It reduces the feedback voltage vf and hence,
vd voltage increases. Thus the output voltage increases almost to same level.
Different Input voltage is ideally zero.
Again considering the voltage equation,
vO = Ad vd
or vd = vO / Ad
Since Ad is very large (ideally infinite)
\ vd 0.
and v1 = v2 (ideal).
This says, that the voltage at non-inverting input terminal of an op-amp is approximately equal to that
at the inverting input terminal provided that Ad is very large. This concept is useful in the analysis of
closed loop OPAMP circuits. For example, ideal closed loop voltage again can be obtained using the
results
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Lecture - 9: Closed Loop Amplifier
Input Resistance with Feedback:
fig. 1, shows a voltage series feedback with the OPAMP equivalent circuit.
Fig. 1
In this circuit Ri is the input resistance (open loop) of the OPAMP and Rif is the input resistance of the
feedback amplifier. The input resistance with feedback is defined as
Since AB is much larger than 1, which means that Rif is much larger that Ri. Thus Rif approaches
infinity and therefore, this amplifier approximates an ideal voltage amplifier.
Output Resistance with Feedback:
Output resistance is the resistance determined looking back into the feedback amplifier from the output
terminal. To find output resistance with feedback Rf, input vin is reduced to zero, an external voltage
Vo is applied as shown in fig. 2.
Fig. 2
The output resistance (Rof ) is defined as
This shows that the output resistance of the voltage series feedback amplifier is ( 1 / 1+AB ) times the
output resistance Ro of the op-amp. It is very small because (1+AB) is very large. It approaches to zero
for an ideal voltage amplifier.
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Reduced Non-linear Distortion:
The final stage of an OPAMP has non-linear distortion when the signal swings over most of the ac load
line. Large swings in current cause the r'e of a transistor to change during the cycle. In other words, the
open loop gain varies throughout the cycle of when a large signal is being applied. It is this changing
voltage gain that is a source of the non-linear distortion.
Noninverting voltage feedback reduces non-linear distortion because the feedback stabilizes the closed
loop voltage gain, making it almost independent of the changes in open loop voltage gain. As long as loop
gain, is much greater than 1, the output voltage equals 1/B times the input voltage. This implies that
output will be a more faithful reproduction of the input .
Consider, under large signal conditions, the open loop OPAMP circuit produces a distortion voltage,
designated vdist. It can be represented by connecting a source vdist in series with Avd. Without negative
feedback all the distortion voltage vdist appears at the output. But with negative feedback, a fraction of
vdist is feedback to inverting input. This is amplified and arrives at the output with inverted phase
almost completely canceling the original distortion produced by the output stage.
The first term is the amplified output voltage. The second term in the distortion that appears at the final
output. The distortion voltage is very much, reduced because AB>>1
Bandwidth with Feedback:
The bandwidth of an amplifier is defined as the band of frequencies for which the gain remains
constant. Fig. 3, shows the open loop gain vs frequency curve of 741C OPAMP. From this curve for a
gain of 2 x 105 the bandwidth is approximately 5Hz. On the other hand, the bandwidth is approximately
1MHz when the gain is unity.
Fig. 3
The frequency at which gain equals 1 is known as the unity gain bandwidth. It is the maximum
frequency the OPAMP can be used for.
Furthermore, the gain bandwidth product obtained from the open loop gain vs frequency curve is equal
to the unity gain bandwidth of the OPAMP.
Since the gain bandwidth product is constant obviously the higher the gain the smaller the bandwidth
and vice versa. If negative feedback is used gain decrease from A to A / (1+AB). Therefore the closed
loop bandwidth increases by (1+AB).
Bandwidth with feedback = (1+ A B) x (B.W. without feedback)
ff= fo (1+A B)
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Output Offset Voltage:
In an OPAMP even if the input voltage is zero an

output voltage can exist. There are three cause of
this unwanted offset voltage.
1. Input offset voltage.

2. Input bias voltage.
3. Input offset current.
Fig. 4, shows a feedback amplifier with an output

offset voltage source in series with the open loop
output AVd. The actual output offset voltage with
negative feedback is smaller. The reasoning is
similar to that given for distortion. Some of the
output offset voltage is fed back to the inverting
input. After amplification an out of phase voltage
arrives at the output canceling most of the original
output offset voltage.
When loop gain AB is much greater than 1, the

closed loop output offset voltage is much smaller Fig. 4
than the open loop output offset voltage.
Voltage Follower:
The lowest gain that can be obtained from a non-inverting amplifier with feedback is 1. When the non-
inverting amplifier gives unity gain, it is called voltage follower because the output voltage is equal to the
input voltage and in phase with the input voltage. In other words the output voltage follows the input
voltage.
To obtain voltage follower, R1 is open circuited and Rf is shorted in a negative feedback amplifier of fig.
4. The resultant circuit is shown in fig. 5.
vout = Avd= A (v1 v2)
v1 = vin
v2 =vout
v1 = v2 if A >> 1
vout = vin.
The gain of the feedback circuit (B) is 1. Therefore
Af = 1 / B = 1 Fig. 5
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Lecture - 10: Voltage Shunt Feedback
Voltage shunt Feedback:
Fig. 1, shows the voltage shunt feedback amplifier using OPAMP.
Fig. 1
The input voltage drives the inverting terminal, and the amplified as well as inverted output signal is
also applied to the inverting input via the feedback resistor Rf. This arrangement forms a negative
feedback because any increase in the output signal results in a feedback signal into the inverting input
signal causing a decrease in the output signal. The non-inverting terminal is grounded. Resistor R1 is
connected in series with the source.
The closed loop voltage gain can be obtained by, writing Kirchoff's current equation at the input node
V2.
The negative sign in equation indicates that the input and output signals are out of phase by 180.
Therefore it is called inverting amplifier. The gain can be selected by selecting Rf and R1 (even < 1).
Inverting Input at Virtual Ground:
In the fig. 1, shown earlier, the noninverting terminal is grounded and the- input signal is applied to the
inverting terminal via resistor R1. The difference input voltage vd is ideally zero, (vd= vO/ A) is the
voltage at the inverting terminals (v2) is approximately equal to that of the noninverting terminal (v1).
In other words, the inverting terminal voltage (v1) is approximately at ground potential. Therefore, it is
said to be at virtual ground.
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Input Resistance with Feedback:
To find the input resistance Miller

equivalent of the feedback resistor Rf, is
obtained, i.e. Rf is splitted into its two
Miller components as shown in fig. 2.
Therefore, input resistance with feedback
Rif is then
Fig. 2
Output Resistance with Feedback:
The output resistance with feedback Rof is

the resistance measured at the output
terminal of the feedback amplifier. The
output resistance can be obtained using
Thevenin's equivalent circuit,shown in fig.
3.
iO = ia + ib
Since RO is very small as compared to

Rf +(R1 || R2 )
Therefore,i.e. iO= ia
vO = RO iO + A vd.
vd= vi v2 = 0 - B vO
Fig. 3
Similarly, the bandwidth increases by (1+

AB) and total output offset voltage
reduces by (1+AB).
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Example - 1
(a).An inverting amplifier is implemented with R1 = 1K and Rf = 100 K. Find the percentge change in
the closed loop gain A is the open loop gain a changes from 2 x 105 V / V to 5 x 104 V/V.
(b) Repeat, but for a non-inverting amplifier with R1 = 1K at Rf = 99 K.
Solution: (a). Inverting amplifier
Here Rf = 100 K
R1 = 1K
When,
(b) Non-inverting amplifier
Here Rf = 99 K
R1 = 1K
Example - 2
An inverting amplifier shown in fig. 4 with R1 = 10 and R2 = 1M is driven by a source v1 = 0.1 V.

Find the closed loop gain A, the percentage division of A from the ideal value - R2 / R1, and the
inverting input voltage VN for the cases A = 100 V/V, 105 and 105 V/V.
Solution:
we have
3
when A = 10 ,
Fig. 4
Example - 3
Find VN, V1 and VO for the circuit shown in fig. 5.

Solution:
Applying KCL at N
or 2VN + VN = VO.
Now VO - Vi = 6 as point A and N are virtually shorted.

VO - VN = 6 V
Therefore, VO = VN + 6 V
Fig. 5
Therefore, VN = Vi = 3 V.
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Lecture - 11: Applications of Operational Amplifiers
Analog Inverter and Scale Changer:
The circuit of analog inverter is shown in fig. 1. It is same as inverting voltage amplifier.
Assuming OPAMP to be an ideal one, the differential

input voltage is zero.
i.e. vd = 0
Therefore, v1 = v2 = 0
Since input impedance is very high, therefore, input

current is zero. OPAMP do not sink any current.
iin= if
vin / R = - vO / Rf
vo = - (Rf / R) vin
If R = Rf then vO = -vin, the circuit behaves like an

inverter.
Fig. 1
If Rf / R = K (a constant) then the circuit is called
inverting amplifier or scale changer voltages.
Inverting summer:
The configuration is shown in fig. 2. With three input voltages va, vb & vc. Depending upon the value of
Rf and the input resistors Ra, Rb, Rc the circuit can be used as a summing amplifier, scaling amplifier,
or averaging amplifier.
Again, for an ideal OPAMP, v1 = v2. The
current drawn by OPAMP is zero. Thus,
applying KCL at v2 node
This means that the output voltage is

equal to the negative sum of all the inputs
times the gain of the circuit Rf/ R; hence
the circuit is called a summing amplifier.
When Rf= R then the output voltage is Fig. 2
equal to the negative sum of all inputs.
vo= -(va+ vb+ vc)
If each input voltage is amplified by a different factor in other words weighted differently at the output,
the circuit is called then scaling amplifier.
The circuit can be used as an averaging circuit, in which the output voltage is equal to the average of all
the input voltages.
In this case, Ra= Rb= Rc = R and Rf / R = 1 / n where n is the number of inputs. Here Rf / R = 1 / 3.
vo = -(va+ vb + vc) / 3
In all these applications input could be either ac or dc.
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Noninverting configuration:
If the input voltages are connected to noninverting input through resistors, then the circuit can be used
as a summing or averaging amplifier through proper selection of R1, R2, R3 and Rf. as shown in fig. 3.
To find the output voltage expression, v1 is required.
Applying superposition theorem, the voltage v1 at the
noninverting terminal is given by
Hence the output voltage is
Fig. 3
This shows that the output is equal to the average of all input voltages times the gain of the circuit (1+
Rf / R1), hence the name averaging amplifier.
If (1+Rf/ R1) is made equal to 3 then the output voltage becomes sum of all three input voltages.
vo = v a + vb+ vc
Hence, the circuit is called summing amplifier.
Example - 1
Find the gain of VO / Vi of the circuit of fig. 4.
Solution:
Current entering at the inveting terminal .
Applying KCL to node 1,
Applying KCL to node 2, Fig. 4

Thus the gain A = -8 V / VO
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Example - 2
Find a relationship between VO and V1 through V6 in the circuit of fig. 5.
Fig. 5
Solution:
Let's consider of V1 (singly) by shorting the others i.e. the circuit then looks like as shown in fig. 6.
The current flowing through the resistor R
into the i/e.
The current when passes through R, output

an operational value of
Let as now consider the case of V2 with Fig. 6

other inputs shorted, circuit looks like as
shown in fig. 7.
Now VO is given by
same thing to V4 and V6
net output V" = V2 + V4 + V6 (3)

From (2) & (3)
V' + V" = (V2 + V4 + V6 ) - (V1 + V3 + V5)

So VO = V2 + V4 + V6 - V1 - V3 - V5. Fig. 7
Example - 3
1. Show that the circuit of fig. 8 has A = VO / Vi = - K (R2 / R1) with K = 1 + R4 / R2 +

R4 / R3, and Ri = R1.
2. Specify resistance not larger than 100 K to achieve A = -200 V / V and Ri = 100 K.
Fig. 8
Solution:
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Differential Amplifier:
The basic differential amplifier is shown in fig. 1.
Fig. 1
Since there are two inputs superposition theorem can be used to find the output voltage. When Vb= 0,
then the circuit becomes inverting amplifier, hence the output due to Va only is
Vo(a) = -(Rf / R1) Va
Similarly when, Va = 0, the configuration is a inverting amplifier having a voltage divided network at
the noninverting input
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Example - 1
Find vout and iout for the circuit shown in fig. 2. The input voltage is sinusoidal with amplitude of 0.5 V.
Fig. 2
Solution:
We begin by writing the KCL equations at both the + and terminals of the op-amp.
For the negative terminal,

Therefore,
15 v- = vout
For the positive terminal,
This yields two equations in three unknowns, vout, v+ and v-. The third equation is the relationship
between v+ and v-for the ideal OPAMP,
v+ = v-
Solving these equations, we find
vout = 10 vin = 5 sint V
Since 2 k resistor forms the load of the op-amp, then the current iout is given by
Example - 2
For the different amplifier shown in fig. 3, verify that
Fig. 3
Solution:
Since the differential input voltage of OPAMP is negligible, therefore,
v1= vx
and v2 = vy
The input impedance of OPAMP is very large and, therefore, the input current of OPAMP is negligible.
Thus
And
From equation (E-1)
or
From equation (E-2)
or
The OPAMP3 is working as differential amplifier, therefore,
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Integrator:
A circuit in which the output voltage waveform is the integral of the input voltage waveform is called
integrator. Fig. 4, shows an integrator circuit using OPAMP.
Fig. 4
Here, the feedback element is a capacitor. The current drawn by OPAMP is zero and also the V2 is
virtually grounded.
Therefore, i1 = if and v2 = v1 = 0
Integrating both sides with respect to time from 0 to t, we get
The output voltage is directly proportional to the negative integral of the input voltage and inversely
proportional to the time constant RC.
If the input is a sine wave the output will be cosine wave. If the input is a square wave, the output will be
a triangular wave. For accurate integration, the time period of the input signal T must be longer than or
equal to RC.
Fig. 5, shows the output of integrator for square and sinusoidal inputs.
Fig. 5
Example - 3
Prove that the network shown in fig. 6 is a non-inverting integrator with .
Solution:
The voltage at point A is vO / 2 and it is also the voltage at

point B because different input voltage is negligible.
vB = VO / 2
Therefore, applying Node current equation at point B,
Fig. 6
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Differentator:
A circuit in which the output voltage waveform is the differentiation of input voltage is called
differentiator.as shown infig. 1.
Fig. 1
The expression for the output voltage can be obtained from the Kirchoff's current equation written at
node v2.
Thus the output vo is equal to the RC times the

negative instantaneous rate of change of the input
voltage vin with time. A cosine wave input
produces sine output. fig. 1 also shows the output
waveform for different input voltages.
The input signal will be differentiated properly if

the time period T of the input signal is larger than
or equal to Rf C.
TRf C
As the frequency changes, the gain changes. Also

at higher frequencies the circuit is highly
susceptible at high frequency noise and noise gets
amplified. Both the high frequency noise and
problem can be corrected by additing, few
components. as shown in fig. 2. Fig. 2
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Voltage to current converter:
Fig. 3, shows a voltage to current converter in which load resistor RL is floating (not connected to
ground).
The input voltage is applied to the non-inverting input terminal and the feedback voltage across R
drives the inverting input terminal. This circuit is also called a current series negative feedback,
amplifier because the feedback voltage across R depends on the output current iL and is in series with
the input difference voltage vd.
Writing the voltage equation for the input loop.
vin = vd + vf
But vd since A is very large,therefore,
vin = vf
vin = R iin
iin = v in / R.
and since input current is zero.
iL = iin = vin ./ R
The value of load resistance does not appear in

this equation. Therefore, the output current is
independent of the value of load resistance.
Thus the input voltage is converted into current,
the source must be capable of supplying this
load current. Fig. 3
Grounded Load:
If the load has to be grounded, then the above circuit cannot be used. The modified circuit is shown
in fig. 4.
Since the collector and emitter currents are equal to a close

approximation and the input impedance of OPAMP is very
high,the load current also flows through the feedback resistor R.
On account of this, there is still current feedback, which means
that the load current is stabilized.
Since vd= 0
v2 = v1 = vin
iout = (vCC vin ) / R
Thus the load current becomes nearly equal to i out. There is a

limit to the output current that the circuit can supply. The base
current in the transistor equals iout /dc. Since the op-amp
has to supply this base current iout /dc must be less than
Iout (max) of the op-amp, typically 10 to 15mA.
There is also a limit on the output voltage, as the load

resistance increases, the load voltage increases and then the
transistor goes into saturation. Since the emitter is at Vin w. r. t.
ground, the maximum load voltage is slightly less than Vin.
Fig. 4
In this circuit, because of negative feedback VBEis automatically adjusted. For instance, if the load
resistance decreases the load current tries to increase. This means that more voltage is feedback to the
inverting input, which decreases VBE just enough to almost completely nullify the attempted increase in
load current. From the output current expression it is clear that as Vin increases the load current
decreases.
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Another circuit in which load current increases as Vin increases is shown in fig. 5.
The current through the first transistor is
i = vin / R
This current produces a collector voltage of

vC = vCC i R = vCC vin
Since this voltage drives the non-inverting

input of the second op-amp. The inverting
voltage is vCC- vin to a close approximation.
This implies that the voltage across the
final R is
vCC - (vCC - vin ) = vin
and the output current .
iout = vin / R
As before, this output current must satisfy

the condition,that Iout/ dc must be less
than the Iout(max) of the OPAMP.
Furthermore, the load voltage cannot
exceed vCC- vin because of transistor
saturation, therefore Iout R must be less
than vCC- vin.This current source produces
unidirectional load current. fig. 6, shows a Fig. 5
Howland current source, that can produce
a bi-directional load current.
Fig. 6
The maximum load current is VCC/ R. In this circuit v in may

be positive or negative.
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Lecture - 14: Applications
Current to voltage converter:
The circuit shown in fig. 1, is a current to voltage converter.
Fig. 1
Due to virtual ground the current through R is zero and the input current flows through Rf. Therefore,
vout =-Rf * iin

The lower limit on current measure with this circuit is set by the bias current of the inverting input.
Example 1:
For the current to current converter shown in fig. 2, prove that
Fig. 2
Solution:
The current through R1 can be obtained from the current divider circuit.
Since, the input impedance of OPAMP is very large, the input current of OPAMP is negligible.
Thus,
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Example - 2
(a). Verify that the circuit shown in fig. 3 has input impedance.
(b). If Z is a capacitor, show that the system behaves as an inductor.

(c). Find the value of C in order to obtain a 1H inductance if R1 = R2= 1K.
Fig. 3
Solution:
Let the output of OPAMP (1) be v and the output of OPAMP (2) be vo. Since the differential input
voltage of the OPAMP is negligible, therefore, the voltage at the inverting terminal of OPAMP (1)will be
vi.
For the OPAMP (2),
or,
(b). Let the input voltage be sinusoidal of frequency ( / 2)
If Z is a capacitor, then Z = 1 / C
Let L = C R1 R2
Therefore, and the system behaves as an inductor.
(c). Given R1 = R2 = 1 K, L = 1 H
Example - 3
Show that the circuit of fig. 4 is a current divider with io = ii / ( 1 + R2 + R1) regardless of the load.
Fig. 4
Solution:
since non-inverting and inverting terminals are virtually grounded.
Therefore, V1 = VL.
Now applying KCL to node (1)

Now current is
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Example - 4
(a). For the circuit shown in fig. 5 prove that
(b). Verify that if R3 / R4 = R1 / R2, the circuit is an instrumentation amplifier with gain A = 1 + R2 /
R1.
Solution:
Here
Fig. 5
(b).
So in this condition circuits as an instrument amplifier with gain .
Example - 3
Obtain an expression of the type iO = Vi / R - VO / RO for the circuit shown in fig. 6. Hence verify that
if R4 / R3 = R2 / R1 the circuit is a V-I converter with RO = and R = R1 R5 / R2 .
Fig. 6
Solution:
Here
iO = current through the resistor.

where
So when
then,
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Filters:
A filter is a frequency selective circuit that, passes a specified band of frequencies and blocks or
attenuates signals of frequencies out side this band. Filter may be classified on a number of ways.
1. Analog or digital
2. Passive or active
3. Audio or radio frequency
Analog filters are designed to process only signals while digital filters process analog signals using digital
technique. Depending on the type of elements used in their consideration, filters may be classified as
passive or active.
Elements used in passive filters are resistors, capacitors and inductors. Active filters, on the other hand,
employ transistors or OPAMPs, in addition to the resistor and capacitors. Depending upon the elements
the frequency range is decided.
RC filters are used for audio or low frequency operation. LC filters are employed at RF or high
frequencies.
The most commonly used filters are these:
1. Low pass filters

2. High pass filter
3. Band pass filter
4. Band reject filter.
5. All pass filter
Fig. 1, shows the frequency response characteristics of the five types of filter. The ideal response is
shown by dashed line. While the solid lines indicates the practical filter response.
Fig. 1
A low pass filter has a constant gain from 0 Hz to a high cutoff frequency fH. Therefore, the bandwidth
is fH. At fH the gain is down by 3db. After that the gain decreases as frequency increases. The frequency
range 0 to fH Hz is called pass band and beyond fH is called stop band.
Similarly, a high pass filter has a constant gain from very high frequency to a low cutoff frequency fL.
below fL the gain decreases as frequency decreases. At fL the gain is down by 3db. The frequency range
fL Hz to is called pass band and bleow fL is called stop band.
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First Order Low Pass Filter:
Fig. 2, shows a first order low pass Butter-worth filter that uses an RC network for filtering, opamp is
used in non-inverting configuration, R1 and Rf decides the gain of the filter.
According to voltage divider rule, the voltage at the non-inverting terminal is:
Fig. 2
Thus the low pass filter has a nearly constant gain Af from 0 Hz to high cut off frequency fH. At fH the
gain is 0.707 Af and after fH it decreases at a constant rate with an increases in frequency. fH is called
cutoff frequency because the gain of filter at this frequency is reduced by 3dB from 0Hz.
Filter Design:
A low pass filter can be designed using the following steps:
1. Choose a value of high cutoff frequency fH.

2. Select a value of C less than or equal to 1 F.
3. Calculate the value of R using .
4. Finally, select values of R1 and RF to set the desired gain using .
Example - 1
Design a low pass filter at a cutoff frequency of 1 kH z with a pass band gain of 2.
Solution:
Given fH = 1 kHz. Let C = 0.01 F.
Therefore, R can be obtained as
A 20 k potentiometer can be used to set the resistance R.
Since the pass band gain is 2, R1 and RF must be equal. Let R1 = R2 = 10 k.
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Low pass filter with adjustable corner frequency
One advantage of active filter is that it is often quite simple to vary parameter values. As an example, a
first-order low-pass filter with adjustable corner frequency is shown in fig. 3.
Fig. 3
The voltage at the opamp inputs are given by
Setting v + = v -, we obtain the voltage, v1, as follows:
where
The second opamp acts as an inverting integrator, and
Note that we use upper case letters for the voltages since these are functions of s. K is the fraction of
V1 sent to the integrator. That is, it is the potentiometer ratio, which is a number between 0 and 1.
The transfer function is given by

The dc gain is found by setting s = 0 (i.e., j =0)
The corner frequency is at KA2 / RC. Thus, the frequency is adjustable and is proportional to K.
Without use of the opamp, we would normally have a corner frequency which is inversely propostional
to the resistor value. With a frequency proportional to K, we can use a linear taper potentiometer. The
frequency is then linearly proportional to the setting of the potentiometer.
Example - 2
Design a first order adjustable low-pass filter with a dc gain of 10 and a corner frequency adjustable
from near 0 t0 1 KHz.
Solution:
There are six unknowns in this problems (RA, RF, R1, R2, R and C) and only three equations (gain,
frequency and bias balance). This leaves three parameters open to choice. Suppose we choose the
following values:
C = 0.1 F
R = 10 K
R1 = 10K
The ratio of R2 to R1 is the dc gain, so with a given value of R1 = 10K, R2 must be 100 k. We solve
for A1 and A2 in the order to find the ratio, RF / RA.
The maximum corner frequency occurs at K = 1, so this frequency is set to 2 x 1000. Since R and C are
known, we find A2 = 6.28. Since A2 and A1 are related by the dc gain, we determine A1 / A2 = 10 and
A1 = 62.8. Now, substituting the expression for A2, we find
and since
we find RF / RA = 68. RA is chosen to achieve bias balance. The impedance attached to the non-
inverting input is 10 K || 100 K = 10 K.
Fig. 4
If we assume that RF is large compared with RA ( we can check this assumption after solving for these
resistors), the parallel combination will be close to the value of RA. We therefore can choose RA = 10
K. With this choice of RA, RFis found to be 680K and bias balance is achieved. The complete filter is
shwn in fig. 4.
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Lecture - 16: Filters and Precision Diode
Second Order Low-Pass Butterworth filter:
A stop-band response having a 40-dB/decade at the cut-off frequency is obtained with the second-order
low-pass filter. A first order low-pass filter can be converted into a second-order low-pass filter by using
an additional RC network as shown in fig. 1.
Fig. 1 Fig. 2
The gain of the second order filter is set by R1 and RF, while the high cut-ff frequency fH is determined
by R2, C2, R3and C3 as follows:
Furthermore, for a second-order low pass Butterworth response, the voltage gain magnitude is given by
where,
Except for having the different cut off frequency, the frequency response of the second order low pass
filter is identical to that of the first order type as shown in fig. 2.
Filter Design:
The design steps of the second order filter are identical to those of the first order filter as given bellow:
1. Choose a value of high cutoff frequency fH.

2. To simplify the design calculations, set R2 = R3 = R and C2 = C3 = C. Then choose a
value of C less than 1 F.
3. Calculate the value of R using .

4. Finally, because of the equal resistor (R2 = R3) and capacitor (C2 = C3) values, the pass
band voltage gain AFhas to be equal to 1.586. This gain is necessary to guarantee
Butterworth response. Therefore, RF = 0.586 R1. Hence choose a value of R1= 100 k
and calculate the value of RF.
First Order High Pass Butterworth filter:
Fig. 3, shows the circuit of first order high pass filter.This is formed by interchanging R and C in low
pass filter.
The lower cut off frequency is fL. This is the frequency at which the magnitude of the gain is 0.707 times
its pass band value. All frequencies higher than fL are pass band frequencies with the highest frequency
determined by the closed loop bandwidth of the OPAMP.
The magnitude of the gain of the filter
is
Fig. 3
If the two filters (high and low) band pass are connected in series it becomes wide band filter whose gain
frequency response is shown in fig. 4.
Fig. 4
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Precision Diodes:
If a sinusoid whose peak value is less than the threshold or cut in voltage Vd(-0.6V) is applied to the
conventional half-wave rectifier circuit, output will remain zero. In order to be able to rectify small
signals (mV), it is necessary to reduce Vd. By placing a diode in the feedback loop of an OPAMP, the cut
in voltage is divided by the open loop gain A of the amplifier. Fig. 5, shows an active diode circuit.
Fig. 5
Hence VD is virtually eliminated and the diode approaches the ideal rectifying element. If the input
Vin goes positive by at least VD/A, then the output voltage (=A vd ) exceeds VD and D conducts and
thus, provides a negative feedback. Because of the virtual connection between the two inputs vO= vin-
vd=vin- v D / A vin. Therefore, the circuit acts as voltage follower for positive signals (above
60 mV=0.6 / 1*105) when Vin swing negatively, D is OFF and no current is delivered to the external
load.
By reversing the diode, the active negative diode can be made.
Active Clippers:
By slightly modifying the circuit, an active diode ideal clipper circuit is obtained. Fig. 6, shows an active
clipper which clips the input voltage below vR.
Fig. 6
When vin < VR , then v' is positive and D conducts. Under these conditions, the OPAMP works as a
buffer and the output voltage equals the voltage at non-inverting terminal
Vout = VR.
If vin > VR, then v' is negative and D is OFF and vO = vin RL / (RL + R) Vi if R << RL Thus, output
follows input for vin > VR and vO is clamped to VRif vin < VR by about 60 mV. Fig. 7, shows the output
waveform of clipper circuit.When D is reverse biased a large differential voltage may appear between
inputs and the OPAMP must be capable to withstand this voltage.
Fig. 7
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Active Half Wave Rectifier:
The Active half wave rectifier is shown in fig. 8.
Fig. 8 Fig. 9
If vin is positive then output of the OPAMP becomes negative (the non inverting terminal is grounded).
Thus diode D2 conducts and provides a negative feedback. Because of the feedback through D2 a virtual
ground exists at the input. Thus diode D1 acts as open circuit. The output voltage under this condition is
given by
vo = v - = 0.
If vin goes negative, then output of the OPAMP becomes positive. Thus D1 is conducting and D2 is off.
Thus, the circuit behaves as an inverting amplifier. The output of the circuit is given by
The resultant output voltage will be positive. If v in is a sinusoid, the circuit performs half wave
rectification. The transfer characteristic of the half wave active rectifier is shown in fig. 9. The output
does not depend upon the diode forward voltage (vd). Thus, because of the high open loop gain of the
OPAMP, the feedback acts to cancel the diode turn-on (forward) voltage. This leads to improved
performance since the diode more closely approximates the ideal device.
Axis Shifting of the Half Wave Rrectifier:
The half wave rectified output waveform can be shifted along the vin axis. This is done by using a
reference voltage added to the input voltage of the rectifier as shown in fig. 10. This termed axis shifting.
It adds or subtracts a fixed dc voltage to the input signal. This process shifts the diode turn-on voltage
point. If a negative reference voltage, VREF, is applied to the circuit, the diode turns on when the input
voltage is still positive. This shifts the vout/ vin transfer characteristic to the right. If a positive reference
voltage is applied, the vout/ vin transfer characteristic shifts to the left. These shifted characteristics are
shown in fig. 10.
Fig. 10 Fig. 11
The input-output voltage characteristics can also be shifted up or down. This is termed level shifting and
is accomplished by adding a second OPAMP with a reference voltage added to the negative input
terminal as shown in fig. 11.
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Active Full Wave Rectifier:
Method 1:
A full wave rectifier, or magnitude operator, produces an output which is the absolute value, or
magnitude, of the input signal waveform. One method of accomplishing full wave rectification is to use
two half wave rectifiers. One of these operates on the positive portion of the input and the second
operates on the negative portion. The outputs are summed with proper polarites. Fig. 1 illustrates one
such configuration. Note that the resistive network attached to the ouput summing opamp is composed
of resistors of higher value than those attached to the opamp that generates v1. This is necessary since
for negative vin, v2 follows the curve shown above the node labled v2. That is, as the input increases in a
negative direction, v2 increases in a positive direction. Since the input impedance to the non-inverting
terminal of the summing opamp is high, the voltage, v+ is simply one half of v2 (i.e., the two 100K
resistors form a voltage divider). The voltage at the negative summing terminal, v-, is the same as v+,
and therefore is equal to v2 / 2. Now when vin is negative, D2 is open, and the node v1 is connected to the
inverting input of the first opamp through a 5 K resistor. The inverting input is a virtual ground since
the non-inverting input is tied to ground through a resistor. The result is that the voltage divider formed
by the 100 K and 5K resistors. In order to achive a characteristic resembling that shown in the
figure, this voltage divider must have a small ratio, on the order of 1 to 20.
Fig. 1
Method 2:
The method of full wave rectification discussed above requires three separate amplifiers. One simpler
circuit or active full wave rectifier, which makes use of only two OPAMPs, is shown in fig. 2. It rectifies
the input with a gain of R / R1, controllable by one resistor R1.
Fig. 2
When v in is positive then v' = negative, D1 is ON and D2 is virtual ground at the input to (l). Because
D2 is non-conducting, and since there is no current in the R which is connected to the non-inverting
input to (2), therefore, V1 =0.
Hence, the system consists of two OPAMP in cascade with the gain of A1 equal to (-R / R1) and the gain
of A2 equal to (-R / R) = -1.
The resultant at voltage output is
vo = (R / R1 ) vin > 0 (for vin > 0 voltage output of (1) )
Consider now next half cycle when v in is negative. The v' is positive D1 is OFF and D2 is ON. Because
of the virtually ground at the input to (2) V2 = V1 = V
Since the input terminals of (2) are at the same (ground) potential, the current coming to the inverting
terminal of (1) is as indicated in fig. 2.
The output voltage is vo = i R + v where i = v / 2R (because input impedance of OPAMP is very high).
The sign of vo is again positive because vin is negative in this half cycle. Therefore, outputs during two
half cycles are same; and full wave rectified output voltage is obtained also shown in fig. 2.
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Clampers:
Fig. 3, shows an active positive clamper circuit.
Fig. 3
The first negative half cycle produces a positive OPAMP output, which turns ON the diode. This
capacitor charges to the peak of the input with the polarity shown in fig. 3. Just beyond the negative
peak the diode turns off, the feedback loop opens, and the virtual ground is lost. Therefore,
vout = vin + VP
Since VP is being added to a sinusoidal voltage, the final output waveform is shifted positively through
VP volts. The output wave form swing from 0 to 2VP as shows in fig. 4. Again the reduction of the diode-
offset voltage allows clamping with low-level inputs.
During most of the cycle, the OPAMP operates in negative saturation. Right at the negative input peak,
the OPAMP produces a sharp positive going pulse that replaces any change lost by the clamping
capacitor between negative input peaks.
Fig. 4
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Comparators:
An analog comparator has two inputs one is usually a constant reference voltage VR and other is a time
varying signal vi and one output vO. The basic circuit of a comparator is shown in fig. 5.
When the noninverting voltage is larger than the inverting voltage the comparator produces a high
output voltage (+Vsat). When the non-inverting output is less than the inverting input the output is low
(-Vsat). Fig. 5, also shows the output of a comparator for a sinusoidal.
Fig. 5
vO = -Vsat if vi > VR
= + Vsat if v i < VR
If VR = 0, then slightest input voltage (in mV) is enough to saturate the OPAMP and the circuit acts as
zero crossing detector as shown in fig. 6. If the supply voltages are 15V, then the output compliance is
from approximate 13V to +13V. The more the open loop gain of OPAMP, the smaller the voltage
required to saturate the output. If vdrequired is very small then the characteristic is a vertical line as
shown in fig. 6.
Fig. 6
If we want to limit the output voltage of the comparator two voltages (one positive and other negative)
then a resistor R and two zener diodes are added to clamp the output of the comparator. The circuit of
such comparator is shown in fig. 7, The transfer characteristics of the circuit is also shown in fig. 7.
Fig. 7
The resistance is chosen so that the zener operates in zener region. When VR= 0 then the output changes
rapidly from one state to other very rapidly every time that the input passes through zero as shown
in fig. 8.
Fig. 8
Such a configuration is called zero crossing detector. If we want pulses at zero crossing then a
differentiator and a series diode is connected at the output. It produces single pulses at the zero crossing
point in every cycle.
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Schmitt Trigger:
If the input to a comparator contains noise, the output may be erractive when vin is near a trip point.
For instance, with a zero crossing, the output is low when vin is positive and high when vin is negative. If
the input contains a noise voltage with a peak of 1mV or more, then the comparator will detect the zero
crossing produced by the noise. Fig. 1, shows the output of zero crossing detection if the input contains
noise.
Fig. 1 Figure 19.2
This can be avoided by using a Schmitt trigger, circuit which is basically a comparator with positive
feedback. Fig. 2, shows an inverting Schmitt trigger circuit using OPAMP.
Because of the voltage divider circuit, there is a positive feedback voltage. When OPAMP is positively
saturated, a positive voltage is feedback to the non-inverting input, this positive voltage holds the output
in high stage. (vin< vf). When the output voltage is negatively saturated, a negative voltage feedback to
the inverting input, holding the output in low state.
When the output is +Vsat then reference voltage Vref is given by
If Vin is less than Vref output will remain +Vsat.
When input vin exceeds Vref = +Vsat the output switches from +Vsat to Vsat. Then the reference
voltage is given by
The output will remain Vsat as long as vin > Vref.
Fig. 3 Fig. 4
If vin < Vref i.e. vin becomes more negative than Vsat then again output switches to +Vsat and so on.
The transfer characteristic of Schmitt trigger circuit is shown in fig. 3. The output is also shown in fig.
4 for a sinusoidal wave. If the input is different than sine even then the output will be determined in a
same way.
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Positive feedback has an unusual effect on the circuit. It forces the reference voltage to have the same
polarity as the output voltage, The reference. voltage is positive when the output voltage is high (+vsat)
and negative when the output is low (vsat).
In a Schmitt trigger, the voltages at which the output switches from +vsat to vsat or vice versa are
called upper trigger point (UTP) and lower trigger point (LTP). the difference between the two trip
points is called hysteresis.
Fig. 5
The hysteresis loop can be shifted to either side of zero point by connecting a voltage source as shown
in fig. 5.
When VO= +Vsat , the reference. Voltage (UTP) is given by
When VO= -Vsat , the reference. Voltage (UTP) is given by
If VR is positive the loop is shifted to right side; if VR is negative, the loop is shifted to left side. The
hysteresis voltage Vhys remains the same.
Non-inverting Schmitt trigger:
In this case, again the feedback is given at non-inverting terminal. The inverting terminal is grounded
and the input voltage is connected to non-inverting input. Fig. 6, shows an non-inverting schmitt trigger
circuit.
Fig. 6
To analyze the circuit behaviour, let us assume the output is negatively saturated. Then the feedback
voltage is also negative (-Vsat). Then the feedback voltage is also negative. This feedback voltage will
hold the output in negative saturation until the input voltage becomes positive enough to make voltage
positive.
When vin becomes positive and its magnitude is greater than (R2 / R1) Vsat, then the output switches to
+Vsat. Therefore, the UTP at which the output switches to +Vsat, is given by
Simillarly, when the output is in positive saturation, feedback voltage is positive. To switch output states,
the input voltage has to become negative enough to make. When it happens, the output changes to the
negative state from positive saturation to negative saturation voltage negative.
When vin becomes negative and its magnitude is greater than R2 / R1 vsat, then the output switches to -
vsat. Therefore,
The difference of UTP and LTP gives the hysteresis of the Schmitt trigger.
In non inverting Schmitt trigger circuit, the is defined as
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Example - 1
Design a voltage level detector with noise immunity that indicates when an input signal crosses the
nominal threshold of 2.5 V. The output is to switch from high to low when the signal crosses the
threshold in the positive direction, and vice versa. Noise level expected is 0.2 VPP, maximum. Assume
the output levels are VH = 10 V and VL = 0V.
Solution:
For the triggering action required an inverting configuration is required. Let the hysteresis voltage be
20% larger that the maximum pp noise voltage, that is, Vhys = 0.24V.
Thus, the upper and lower trigger level voltages are -2.5 0.12, or
UTP = 2.38 V and LTP = -2.62 V
Since the output levels are VH and VL instead of +Vsat and Vsat, therefore, hysteresis voltage is given
by
or
and
The reference voltage V R can be obtained from the expression of LTP.
Given that VL = 0, and LTP= -262, we obtain
VR = (1 + R2 / R1) LTP = (1 + 1 / 40.7) (-2.62) = - 2.68 V
We can select any values for R2 and R1 that satisfy the ratio of 40.7. It is a good practice to have more
than 100 k for the sum of R1 and R2 and 1 k to 3k for the pull up resistor on the output. The
circuit shown in fig. 7 shows a possible final design. The potentiometer serves as a fine adjustment for
VR, while the voltage follower makes VR to appear as an almost ideal voltage source.
Fig. 7
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Lecture - 19: Schmitt Trigger and Relaxation Oscillator
Example - 1
The Schmitt trigger circuit of fig. 1 uses 6V zener diodes with VD = 0.7 V. if the threshold voltage V1 is
zero and the hysteresis is VH = 0.2V. Calculate R1 / R2 and VR.
Fig. 1
Solution:
The normal output voltage of Schmitt trigger circuit will be either +VO or VO,
Where, VO = VZ + VD
= 6.7 V
Let the output voltage be +VO. The voltage V1 can be obtained from the voltage divider circuit
consisting of R1 and R2.
When vin > V1 then vo = -VO

Therefore, upper trigger point voltage will be given by,
Similarly, the lower trigger point voltage will be given by,
Therefore, the hysteresis voltage is

Since, the threshold voltage v1 is zero,
Therefore,
Relaxation Oscillator:
With positive feedback it is also possible to build relaxation oscillator which produces rectangular wave.
The circuit is shown in fig. 2.
Fig. 2
In this circuit a fraction R2/ (R1 +R2) = b of the output is feedback to the non-inverting input terminal.
The operation of the circuit can be explained as follows:
Assume that the output voltage is +Vsat. The capacitor will charge exponentially toward +Vsat. The
feedback voltage is +bVsat. When capacitor voltage exceeds +bVsat the output switches from +Vsat to -
Vsat. The feedback voltage becomes -Vsat and the output will remain Vsat. Now the capacitor charges
in the reverse direction. When capacitor voltage decreases below bVsat (more negative than bVsat )
the output again switches to +Vsat.This process continues and it produces a square wave. Under steady
state conditions, the output voltage and capacitor voltage are shown in fig. 2. The frequency of the
output can be obtained as follows:
The capacitor charges from - Vsat to + Vsat during time period T/2. The capacitor charging voltage
expression is given by
This square wave generator is useful in the frequency range of 10Hz to 10KHz. At higher frequencies,
the slew rate of the OPAMP limits the slope of the output square wave.
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The duty cycle of the output wave can be changed replacing the resistance R by another circuit
consisting of variable resistance and two diodes D1 and D2 as shown in fig. 3.
Fig. 3 Fig. 4
When the output is positive then D2 conducts and D1 is OFF. The total feedback resistance becomes
Rb+R and charging voltage is reduced by VD. During the interval when the output is negative then
D1 conducts and D2 is OFF. The charging resistance becomes R+Ra. The total charging and reverse
charging period is decided by total resistance (2 R + Ra + Rb) = constant. Therefore frequency will
remain constant but duty cycle changes. The capacitor voltage and output voltage of the oscillator are
shown in fig. 4.
The duty cycle is given by
By varying Ra and Rb the duty cycle can be charged keeping frequency constant.
Example - 2
Characterize the astable mulitvibrator shown in fig. 5. Establish the frequency range.
Fig. 5
Solution:
By observing the way the output section is connected, we conclude that the output voltage oscillates
between VL = - 5V and VH = + 5V.
To calculate the oscillation frequency range, two extreme values for R1 and R2 are used. Thus, when the
wiper of the potentiometer is at its leftmost position, R1 = 120 k and R2 = 10 k. At the other extreme,
R1 = 20 k and R2 =110 k.
Substituting the values of R1 and R2 in the expression of T, we obtain the two extreme values of T, i.e.,
Tmin and Tmax
Therefore,
fmin = 285 Hz and fmax = 4.6 kHz
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Triangular Wave Generator:
In the relaxation oscillator discussed in the previous lecture, capacitor voltage VC has a near triangular
wave shape but the sides of the triangles are exponentials rather than straight line. To linear size the
triangles, it is required that C be charged with a constant current rather that the exponential current
through R. The improved circuit is shown in fig. 1.
Figure 21.1
In this circuit an OPAMP integrator is used to supply a constant current to C so that the output is
linear. Because of inversion through the integrator, this voltage is fedback to the non-inverting terminal
of the comparator rather than to the inverting terminal. The inverter behaves as a non-inverting schmitt
trigger. The voltage vR is used to shift the dc level of the triangular wave and voltage vs is used to
change the slopes of the triangular wave form is shown in fig. 2.
Fig. 2
To find the maximum value of the triangular waveform assume that the square wave voltage vOis at its
negative value = -Vsat. With a negative input, the output v (t) of the integrator is an increasing ramp.
The voltage at the non-inverting comparator input v1 is given by
When v1 rises to VR, the comparator changes state from - Vsat to +Vsat and v(t) starts decreasing
linearly similarly, when v1 falls below vR the comparator output changes from +vsat to -vsat. Hence the
minimum value of triangular vminoccurs for v1 = vR. Hence the peak value Vmax of the triangular
waveform occurs for v1 = VR.
Therefore,
The peak to peak swing is given by
The average output voltage is given by .

If VR = 0, the waveform extends between -Vsat (R2 / R1 ) and +Vsat (R2 /R1).
The sweep times T1 and T2 for Vs = 0 can be calculated as follows:
The capacitor charging current is given by
where, vc = -vout is the capacitor voltage.
For vout = -Vsat, . Therefore,
When the output voltage of first OPAMP is +Vsat, then, the voltage v1 is given by
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As triangular voltage increases the voltage v1 also increases. At t = T1, when the voltage vout becomes
Vmax, the voltage v1 becomes equal to VR and switching takes place. Therefore,
Similarly, when output voltage is +Vsat, the voltage v1 is given by
As triangular voltage decreases the voltage v1 also decreases. At t = T2, when the voltage vout becomes
Vmin, the voltage v1 becomes equal to VR and switching takes place. Therefore,
Therefore,
Solving the above equations, we get
The frequency f is independent of VO, maximum frequency is limited either by slew rate or its
maximum output current which determines the charging rate of C. Slowest speed is limited by the bias
current of OPAMP.
If unequal sweep intervals T1 T2 are desired, then VS can be changed. The positive sweep speed is
given by (Vsat + VS) / RC and the negative sweep speed is given by (Vsat -VS)/ RC. The peak-to-peak
triangular amplitude is unaffected by the voltage VS.
Therefore,
Similarly, when the output voltage of first OPAMP is Vsat, then
Therfore,
Therefore,
The oscillation frequency is given by
and the duty cycle is given by
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Example-1:
1. Consider the pulse generator shown in fig. 3. In the quiescent state (before a trigger pulse is
applied), find V2, VO and V1.
2. At t = 0, a narrow, positive triggering pulse v whose magnitude exceeds VR is applied. At t = 0+,
find VO and V1.
3. Verify that the pulse width T = RC ln (2 VO) / VR.
Fig. 3
Solution:
(a). Before a trigger pulse is applied, the circuit is in stable stage with the output at vO = +VO ( VZ +
0.7). The capacitor C is charged with the polarity shown in fig. 3.
Thus, v1 0.7V
and v2 = -VR
(b). At t = 0, a narrow positive triggering pulse of higher magnitude is applied. The capacitor C voltage
can not charge instantaneously. Therefore, v2 becomes positive and greater than v1 ( 0.7 V). The
comparator output changes.
Thus, vO= - (VZ + 0.7V) = -VO
Since capacitor C voltage can not change instantaneously, therefore,
v1 = 2 VO
(c). The input trigger pulse is of very short duration therefore, after the short duration pulse the voltage
v2 returns to (-VR). But the output remains VO because v1 is at 2VO.
The capacitor now starts charging exponentially with a time constant t = RC through R towards VO,
because diode is reverse biased.
VC = (-VO VO) ( 1 e-t / RC ) - VO

The voltage at point v1 is, thus, given by
V1 = - VO vc
= - VO + 2 VO (1 e-t / RC ) - VO
= - 2 VO e-t / RC t / RC
When v1 voltage becomes more than VR, the comparator output switches back to +VO. Let at t = T, the
voltage v1becomes VR
The capacitor now starts charging towards +VO through R until vc reaches +VO and v1 becomes 0.7 V.
The waveforms at different points are shown in fig. 4.
Fig. 4
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Lecture - 21: Oscillators
Oscillators:
An oscillator may be described as a source of alternating voltage. It is different than amplifier.
An amplifier delivers an output signal whose waveform corresponds to the input signal but whose power
level is higher. The additional power content in the output signal is supplied by the DC power source
used to bias the active device.
The amplifier can therefore be described as an energy converter, it accepts energy from the DC power
supply and converts it to energy at the signal frequency. The process of energy conversion is controlled
by the input signal, Thus if there is no input signal, no energy conversion takes place and there is no
output signal.
The oscillator, on the other hand, requires no external signal to initiate or maintain the energy
conversion process. Instead an output signals is produced as long as source of DC power is
connected. Fig. 1, shows the block diagram of an amplifier and an oscillator.
Fig. 1
Oscillators may be classified in terms of their output waveform, frequency range, components, or circuit
configuration.
If the output waveform is sinusoidal, it is called harmonic oscillator otherwise it is called relaxation
oscillator, which include square, triangular and saw tooth waveforms.
Oscillators employ both active and passive components. The active components provide energy
conversion mechanism. Typical active devices are transistor, FET etc.
Passive components normally determine the frequency of oscillation. They also influence stability, which
is a measure of the change in output frequency (drift) with time, temperature or other factors. Passive
devices may include resistors, inductors, capacitors, transformers, and resonant crystals.
Capacitors used in oscillators circuits should be of high quality. Because of low losses and excellent
stability, silver mica or ceramic capacitors are generally preferred.
An elementary sinusoidal oscillator is shown in fig. 2. The inductor and capacitors are reactive elements
i.e. they are capable of storing energy. The capacitor stores energy in its electric field.Whenever there is
voltage across its plates,and the inductor stores energy in its magnetic field whenever current flows
through it. Both C and L are assumed to be loss less. Energy can be introduced into the circuit by
charging the capacitor with a voltage V as shown in fig. 2. As long as the switch S is open, C cannot
discharge and so i=0 and V=0.
Fig. 2
Now S is closed at t = to, This means V rises from 0 to V, Just before closing inductor current was zero
and inductor current cannot be changed instantaneously. Current increases from zero value sinusoidally
and is given by
The capacitor losses its charge and energy is simply transferred from capacitor to inductor magnetic
field. The total energy is still same. At t = t1, all the charge has been removed from the capacitor plates
and voltage reduces to zero and at current reaches to its maximum value. The current for t> t1 charges
C in the opposite direction and current decreases. Thus LC oscillation takes places. Both voltage and
current are sinusoidal though no sinusoidal input was applied. The frequency of oscillation
is
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The circuit discussed is not a practical oscillator because even if loss less components were available, one
could not extract energy with out introducing an equivalent resistance. This would result in damped
oscillations as shown in fig. 3.
Fig. 3
These oscillations decay to zero as soon as the energy in the tank is consumed. If we remove too much
power from the circuit, the energy may be completely consumed before the first cycle of oscillations can
take place yielding the over damped response.
It is possible to supply energy to the tank to make up for all losses (coil losses plus energy removed),
thereby maintaining oscillations of constant amplitude.
Since energy lost may be related to a positive resistance, it follows that the circuit would gain energy if
an equivalent negative resistance were available. The negative resistance, supplies whatever energy the
circuit lose due to positive resistance. Certain devices exhibit negative resistance characteristics, an
increasing current for a decreasing voltage. The energy supplied by the negative resistance to the circuit,
actually comes from DC source that is necessary to bias the device in its negative resistance region.
Another technique for producing oscillation is to use positive feedback considers an amplifier with an
input signal vinand output vO as shown in fig. 4.
Fig. 4
The amplifier is inverting amplifier and may be transistorized, or FET or OPAMP. The output is 180
out of phase with input signal vO= -A vin.(A is negative)
Now a feedback circuit is added. The output voltage is fed to the feed back circuit. The output of the
feedback circuit is again 180 phase shifted and also gets attenuated. Thus the output from the feedback
network is in phase with input signal vin and it can also be made equal to input signal.
If this is so, Vf can be connected directly and externally applied signal can be removed and the circuit
will continue to generate an output signal. The amplifier still has an input but the input is derived from
the output amplifier. The output essentially feeds on itself and is continuously regenerated. This is
positive feedback. The over all amplification from vin to vf is 1 and the total phase shift is zero. Thus the
loop gain A is equal to unity.
When this criterion is satisfied then the closed loop gain is infinite. i.e. an output is produced without
any external input.
vO = A verror
= A (v in + v f )
= A (vin + vO)
or (1-A )vO = A vin
or
When A = 1, vO / vin=
The criterion A = 1 is satisfied only at one frequency.This is known as backhausen criterion.
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The frequency at which a sinusoidal oscillator will operate is the frequency for which the total phase
shift introduced, as the signal proceeds form the input terminals, through the amplifier and feed back
network and back again to the input is precisely zero or an integral multiple of 2p. Thus the frequency
of oscillation is determined by the condition that the loop phase shift is zero.
Oscillation will not be sustained, if at the oscillator frequency, A <1 or A >1. Fig. 5, show the output
for two different contions A < 1 and A >1.
Fig. 5
If A is less than unity then A vin is less than vin, and the output signal will die out, when the
externally applied source is removed. If A>1 then A b vinis greater than vin and the output voltage
builds up gradually. If A = 1, only then output voltage is sine wave under steady state conditions.
In a practical oscillator, it is not necessary to supply a signal to start the oscillations. Instead, oscillations
are self-starting and begin as soon as power is applied. This is possible because of electrical noise present
in all passive components.
Therefore, as soon as the power is applied, there is already some energy in the circuit at fo, the
frequency for which the circuit is designed to oscillate. This energy is very small and is mixed with all
the other frequency components also present, but it is there. Only at this frequency the loop gain is
slightly greater than unity and the loop phase shift is zero. At all other frequency the Barkhausen
criterion is not satisfied. The magnitude of the frequency component fo is made slightly higher each time
it goes around the loop. Soon the fo component is much larger than all other components and ultimately
its amplitude is limited by the circuits own non-lineareties (reduction of gain at high current levels,
saturation or cut off). Thus the loop gain reduces to unity and steady stage is reached. If it does not, then
the clipping may occur.
Practically, A is made slightly greater than unity. So that due to disturbance the output does not
change but if A = 1 and due to some reasons if A decreases slightly than the oscillation may die out
and oscillator stop functioning. In conclusion, all practical oscillations involve:
An active device to supply loop gain or negative resistance.

A frequency selective network to determine the frequency of oscillation.
Some type of non-linearity to limit amplitude of oscillations.
Example - 1
The gain of certain amplifier as a function of frequency is A (j) = -16 x 106 / j. A feedback path
connected around it has (j ) = 103 / (20 x 103 + j )2. Will the system oscillate? If so, at what
frequency ?
Solution:
The loop gain is
To determine, if the system will oscillate, we will first determine the frequency, if any, at which the
phase angle of equals to 0 or a multiple of 360. Using phasor algebra, we have
This expression will equal -360 if ,
Thus, the phase shift around the loop is -360 at = 2000 rad/s. We must now check to see if the gain
magnitude |A | = 1 at = 2 x 103. The gain magnitude is
Substituting = 2 x 103, we find
Thus, the Barkhausen criterion is satisfied at = 2 x 103 rad/s and oscillation occurs at that frequency
(2 x 103 / 2 = 318 .3 Hz).
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Lecture - 22: Harmonic Oscillators
According to Barkhausen criterion, a feedback type oscillator, having A as loop gain, works if A is
made slightly greater than unity. As discussed in previous lectures, all practical oscillations involve:
An active device to supply loop gain or negative resistance.

A frequency selective network to determine the frequency of oscillation.
Some type of non-linearity to limit amplitude of oscillations.
Harmonic Oscillator:
One feedback type harmonic oscillator circuit is shown in fig. 1.
Fig. 1 Fig. 2
The dc equivalent circuit is shown in fig. 2. The dc operating point is set by selecting VCC, RB and RE.
The ac equivalent circuit is also shown in fig. 3.
Fig. 3
The transformer provides 180 phase shift to ensure positive feedback so that at the desired frequency of
oscillation, the total phase shift from vin to vx is made equal to 0 and magnitudes are made equal by
properly selecting the turns ratio. RE also controls and stabilizes the gain through negative feedback.
C2 and the transformers equivalent inductance make up a resonant circuit that determines the
frequency of oscillation.
C1 is used to block dc (Otherwise the base would be directly tied to VCC) through the low dc resistance
of transformer primary. C1 has negligible reactance at the frequency of oscillation, therefore it is not
apart of the frequency-determining network, the same applies to C2.
In this circuit, there is an active device suitably biased to provide necessary gain. Since the active device
produces loop phase shift 180 (from base to collector), a transformer in the feedback loop provides an
additional 180 to yield to a loop phase shift of 0. The feedback factor is equivalent to the transformer's
turns ratio. There is also a turned circuit, to determine the frequency of oscillation.
The load is in parallel with C2 and the transformer. If the load is resistive, which is usually the case, the
Q of the tuned circuit and the loop gain are both affected, this must be taken into account when
determining the minimum gain required for oscillation. If the load has a capacitive component, then the
value of C2 should be reduced accordingly.
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The RC Phase Shift Oscillator:
At low frequencies (around 100 KHz or less), resistors are usually employed to determine the frequency
oscillation. Various circuits are used in the feedback circuit including ladder network.
Fig. 4
A block diagram of a ladder type RC phase shift oscillation is shown in fig. 4. It consists of three resistor
R and C capacitors. If the phase shift through the amplifier is 180, then oscillation may occur at the
frequency where the RC network produces an additional 180 phase shift.
To find the frequency of oscillation, let us neglect the loading of the phase shift network. Writing the KV
equations,
For phase shift equal to 180o between Vx and VO, imaginary term of Vx / VO must be zero.
Therefore,
This is the frequency of oscillation. Substituting this frequency in Vx / VO expression.
In order to ensure the oscillation, initially |A| >1 and under study state A =1. This means the gain of
the amplifier should be initially greater than 29 (so that A >1) and under steady stat conditions it
reduces to 29.
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This oscillator can be realized using FET amplifier as shown in fig. 5. The feedback circuit is same as
discussed above.
Fig. 5 Fig. 6
The input impedance of FET is very high so that there is no loading of the feedback circuit. In this
circuit, the feedback is voltage series feedback.
Vx =VGS +VS or VGS = Vx - V
The same circuit can be realizing using OPAMP. The circuit is shown in fig. 6. The input impedance is
very high and there is no overloading of feedback circuit. The OPAMP is connected in an inverting
configuration and drives three cascaded RC sections. The inverting amplifier causes a 180 phase shift
in the signal passing through it. RC network is used in the feedback to provide additional 180 phase
shift. Therefore, the total phase shift in the signal, of a particular frequency, around the loop will equal
360 and oscillation will occur at that frequency. The gain necessary to overcome the loss in the RC
network and bring the loop gain up to 1 is supplied by the amplifier. The gain is given by
Note that input resistor to the inverting amplifier is also the last resistor of the RC feedback network.
Example -1:
Design a RC phase shift oscillator that will oscillate at 100 Hz.
Solution:
An RC phase shift oscillator using OPAMP is shown in fig. 7. OPAMP is used as an inverting amplifier
and provides 180 phase shift. RC network is used in the feedback to provide additional 180 phase shift.
Fig. 7
For an RC phase shift oscillator the frequency is given by
Let C = 0.5 F. Then

Therefore, Rf= 29 R = 29 (1300) = 37.7 k.
The completed circuit is shown in fig. 7. Rf is made adjustable so the loop gain can be set precisely to 1.
Example - 2
For the network shown in fig. 8 prove that
This network is used with an OPAMP to form an oscillator. Show that the frequency of oscillation is f =1
/2RC and the gain must exceed 3.
Solution:
To find the frequency of oscillation, let us neglect the loading of the phase shift network. Writing the KV
equations,
From equation (E-3),
Fig. 8
Substituting I1 in equation (E-4),.
Solving this equation we get,
Therefore, from equation (E-1),

Putting , we get,
For phase shift equal to 180 between vf and vo, imaginary term of vf / vo must be zero. Therefore,
This is the frquency of oscillation. Substituting this frequency in vf / vo expression, we get,
This shows that 0 phase shift from vo to vf can be obtained if
and the gain of the feedback circuit becomes 1/3. Therefore, oscillation takes place if the gain of the
amplifier exceeds 3.
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Transistor Phase Shift Oscillator:
At low frequencies (around 100 kHz or less), resistors and capacitors are usually employed to determine
the frequency of oscillation. Fig. 1 shows transistorized phase shift oscillator circuit employing RC
network. If the phase shift through the common emitter amplifier is 180, then the oscillation may occur
at the frequency where the RC network produces an additional 180 phase shift.
Since a transistor is used as the active element, the output across R of the feedback network is shunted
by the relatively low input resistance of the transistor, because input diode is a forward biased diode
Fig. 1
Hence, instead of employing voltage series feedback, voltage shunt feedback is used for a transistor
phase shift oscillator. The load resistance RL is also connected via coupling capacitor. The equivalent
circuit using h-parameter is shown in fig. 2.
Fig. 2
For the circuit, the load resistance RL may be lumped with RC and the effective load resistance becomes
R'L(= RC || RL). The two h-parameters of the CE transistor amplifier, hoe and hre are neglected.
The capacitor C offers some impedance at the frequency of oscillation and, therefore, it is kept as it is,
while the coupling capacitor behaves like ac short. The input resistance of the transistor is Rihie.
Therefore the resistance R3 is selected such that R=R3+Ri=R3+hie. This choice makes the three R C
selections alike and simplifies the calculation. The effect of biasing resistor R1 , R2, & REon the circuit
operation is neglected.
Since this is a voltage shunt feedback, therefore instead of finding VR /VO, we should find the current
gain of the feedback loop.
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The simplified equivalent circuit is shown in fig. 3.
Fig. 3
Applying KVL,
Since I3 and Ib must be in phase to satisfy Barkhausen criterion, therefore

Also initially I3 > Ib, therefore, for oscillation to start,
Therefore, the two conditions must be satisfied for oscillation to start and sustain.
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Wien Bridge Oscillator:
The Wien Bridge oscillator is a standard oscillator circuit for low to moderate frequencies, in the range
5Hz to about 1MHz. It is mainly used in audio frequency generators.
The Wien Bridge oscillator uses a feedback circuit called a lead

lag network as shown in fig. 1.
At very low frequencies, the series capacitor looks open to the

input signal and there is no output signal. At very high
frequencies the shunt capacitor looks shorted, and there is no
output. In between these extremes, the output voltage reaches a
maximum value. The frequency at which the output is maximized
is called the resonant frequency. At this frequency, the feedback
fraction reaches a maximum value of 1/3.
At very low frequencies, the phase angle is positive, and the

circuit acts like a lead network. On the other hand, at very high
frequencies, the phase angle is negative, and the circuit acts like
a lag network. In between, there is a resonant frequency f r at
which the phase angle equals 0.
Fig. 1
The output of the lag lead network is

The gain of the feedback circuit is given by
The phase angle between Vout and Vinis given by

These equations shows that maximum value of gain occurs at XC = R, and phase angle also becomes 0.
This represents the resonant frequency of load lag network. Fig. 2, shows the gain and phase vs
frequency.
Fig. 2
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How Wien Bridge Oscillator Works:
Fig. 3, shows a Wien Bridge oscillator. The operational amplifier is used in a non-inverting
configuration, and the lead-lag network provides the feedback. Resistors Rf and R1 determine the
amplifier gain and are selected to make the loop gain equal to 1. If the feedback circuit parameters are
chosen properly, there will be some frequency at which there is zero phase shift in the signal fed back to
non inverting terminal. Because the amplifier is non inverting, it also contributes zero phase shift, so the
total phase shift around the loop is 0 at that frequency, as required for oscillation.
The oscillator uses positive and negative feedback. The positive feedback helps the oscillations to build
up when the power is turn on. After the output signal reaches the desired level the negative feedback
reduces the loop gain is 1. The positive feedback is through the lead lag network to the non-inverting
input. Negative feedback is through the voltage divider to the inverting input.
Fig. 3
At power up, the tungsten lamp has a low resistance, and therefore, negative feedback is less. For this,
reason, the loop gain AB is greater than 1, and oscillations can build up at the resonant frequency fr. As
the oscillations build up, the tungsten lamp heats up slightly and its resistance increases. At the desired
output level the tungsten lamp has a resistance R'. At this point
Since the lead lag network has a gain (=B) of 1/3, the loop gain AB equals unity and than the output
amplitude levels off and becomes constant. The frequency of oscillation can be adjusted by selecting R
and C as
The amplifier must have a closed loop cut off frequency well above the resonant frequency, fr.
Fig. 4
Fig. 4, shows another way to represent Wein Bridge oscillator. The lead lag network is the left side of the
bridge and the voltage divider is the right side. This ac bridge is called a Wein Bridge. The error voltage
is the output of the Wein Bridge. When the bridge approaches balance, the error voltage approaches
zero.
Example -1:
Design a Wien-bridge oscillator that oscillates at 25 kHz.
Solution:
Let C1 = C2 = 0.001 F. Then, the frequency of oscillation is given by,
or,
Let R1 = 10 K. Then,
or, Rf = 20K
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Lecture - 25: Tuned Oscillators
Tuned Oscillator:
A variety of oscillator circuits can be built using LC tuned circuits. A general form of tuned oscillator
circuit is shown infig. 1. It is assumed that the active device used in the oscillator has very high input
resistance such as FET, or an operational amplifier.
Fig. 1 Fig. 2
Fig. 2 shows linear equivalent circuit of fig. 1 using an amplifier with an open circuit gain Av and
output resistance RO. It is clear from the topology of the circuit that it is voltage series feedback type
circuit.
The loop gain of the circuit A can be obtained by considering the circuit to be a feedback amplifier
with output taken from terminals 2 and 3 and with input terminals 1 and 3. The load impedance
ZL consists of Z2 in parallel with the series combination of Z1 and Z3. The gain of the the amplifier
without feedback will be given by
The feedback circuit gain is given by
Therefore, the loop gain is given by

If the impedances are pure reactances (either inductive or capacitive), then Z1 = jX1, Z2= jX2 and Z3=
jX3. Then
For the loop gain to be real (zero phase shift around the loop),
X1 + X2 + X3 = 0
and
Therefore, the circuit will oscillate at the resonant frequency of the series combination of X1, X2 and X3.
Since A must be positive and at leat unity in magnitude, then X1 and X2 must have the same sign
(Av is positive).In other words, they must be the same kind of reactance, either both inductive or both
capacitive.
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The Colpitts Oscillator:
Wein bridge oscillator is not suited to high frequencies (above 1MHz). The main problem is the phase
shift through the amplifier.
The alternative is an LC oscillator, a circuit that can be used for frequencies between 1MHz and
500MHz. The frequency range is beyond the frequency limit of most OPAMPs. With an amplifier and
LC tank circuit, we can feedback a signal with the right amplitude and phase is feedback to sustain
oscillations. Fig. 3, shows the circuit of colpitts oscillator.
Fig. 3 Fig. 4
The voltage divider bias sets up a quiescent operating point. The circuit then has a low frequency
voltage gain of rc / r'e where rc is the ac resistance seen by the selector. Because of the base and collector
lag networks, the high frequency voltage gain is less then rc / r'e.
Fig. 4, shows a simplified ac equivalent circuit. The circulating or loop current in the tank flows through
C1 in series with C2. The voltage output equals the voltage across C1. The feedback voltage vf appears
across C2. This feedback voltage drives the base and sustains the oscillations developed across the tank
circuit provided there is enough voltage gain at the oscillation frequency. Since the emitter is at ac
ground the circuit is a CE connection.
Most LC oscillators use tank circuit with a Q greater than 10. The Q of the feedback circuit is given by
Because of this, the approximate resonant frequency is
This is accurate and better than 1% when Q is greater than 1%. The capacitance C is the equivalent
capacitance the circulation current passes through. In the Colpitts tank the circulating current flows
through C1 in series with C2.
Therefore C = C1 C2 / (C1 +C2)
The required starting condition for any oscillator is A > 1 at the resonant frequency or A > 1/ . The
voltage gain A in the expression is the gain at the oscillation frequency. The feedback gain is given by
= vf / vout XC1 / XC2

Because same current flow through C1 and C2, therefore
= C1/ C2; A > 1/ v; A> C1 / C2
This is a crude approximation because it ignores the impedance looking into the base. An exact analysis
would take the base impedance into account because it is in parallel with C2 .
With small , the value of A is only slightly larger than 1/. and the operation is approximately close A.
When the power is switched on, the oscillations build up, and the signal swings over more and more of
ac load line. With this increased signal swing, the operation changes from small signal to large signal. As
this happen, the voltage gain decreases slightly. With light feedback the value of A can decreases to 1
without excessive clapping.
With heavy feedback, the large feedback signal drives the base into saturation and cut off. This charges
capacitor C3producing negative dc clamping at the base and changing the operation from class A to
class C. The negative damping automatically adjusts the value of A to 1.
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Example - 1
Design a Colpitts oscillator that will oscillate at 100 kHz.
Solution:
Let us choose R1 = Rf = 5 k and C = 0.001 F. From the frequency expression,
The quality factor (Q) of the LC circuit is given by:
Hartley Oscillator:
Fig. 5, shows Hartley oscillator when the LC tank is resonant, the circulating current flows through
L1 in series with L2. Thus, the equivalent inductance is L = L1 + L2.
Fig. 5
In the oscillator, the feedback voltage is developed by the inductive voltage divider, L1 & L2. Since the
output voltage appears across L1 and the feedback voltage across L2, the feedback fraction is
= V / Vout = XL2 / XL1 = L2 / L1
As usual, the loading effect of the base is ignored. For oscillations to start, the voltage gain must be
greater than 1/ . The frequency of oscillation is given by
Similarly, an opamp based Hartley oscillator circuit is shown in fig. 6.
Fig. 6
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Crystal Oscillator:
Some crystals found in nature exhibit the piezoelectric effect i.e. when an ac voltage is applied across
them, they vibrate at the frequency of the applied voltage. Conversely, if they are mechanically pressed,
they generate an ac voltage. The main substances that produce this piezoelectric effect are Quartz,
Rochelle salts, and Tourmaline.
Rochelle salts have greatest piezoelectric activity, for a given ac voltage, they vibrate more than quartz
or tourmaline. Mechanically, they are the weakest they break easily. They are used in microphones,
phonograph pickups, headsets and loudspeakers.
Tourmaline shows the least piezoelectric activity but is a strongest of the three. It is also the most
expensive and used at very high frequencies.
Quartz is a compromise between the piezoelectric activity of Rochelle salts and the strength of
tourmaline. It is inexpensive and easily available in nature. It is most widely used for RF oscillators and
filters.
The natural shape of a quartz crystal is a hexagonal prism with pyramids at the ends. To get a useable
crystal out of this it is sliced in a rectangular slap form of thickness t. The number of slabs we can get
from a natural crystal depends on the size of the slabs and the angle of cut.
Fig. 1
For use in electronic circuits, the slab is mounted between two metal plates, as shown in fig. 1. In this
circuit the amount of crystal vibration depends upon the frequency of applied voltage. By changing the
frequency, one can find resonant frequencies at which the crystal vibrations reach a maximum. Since
the energy for the vibrations must be supplied by the ac source, the ac current is maximized at each
resonant frequency. Most of the time, the crystal is cut and mounted to vibrate best at one of its
resonant frequencies, usually the fundamental or lowest frequency. Higher resonant frequencies, called
overtones, are almost exact multiplies of the fundamental frequency e.g. a crystal with a fundamental
frequency of 1 MHz has a overtones of 2 MHz, 3 MHz and so on. The formula for the fundamental
frequency of a crystal is
f = K / t.
where K is a constant that depends on the cut and other factors, t is the thickness of crystal, f is inversely
proportional to thickness t. The thinner the crystal, the more fragile it becomes and the more likely it is
to break because of vibrations. Quartz crystals may have fundamental frequency up to 10 MHz. To get
higher frequencies, a crystal is mounted to vibrate on overtones; we can reach frequencies up to 100
MHz.
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AC Equivalent Circuit:
When the mounted crystal is not vibrating, it is equivalent to a capacitance Cm, because it has two metal
plates separated by dielectric, Cm is known as mounting capacitance.
Fig. 2
When the crystal is vibrating, it acts like a tuned circuit. Fig. 2, shows the ac equivalent circuit of a
crystal vibrating at or near its fundamental frequency. Typical values are L is henrys, C in fractions of a
Pico farad, R in hundreds of ohms and Cm in Pico farads
Ls = 3Hz, Cs = 0.05 pf, Rs = 2K, Cm = 10 pf.
The Q of the circuit is very very high. Compared with L-C tank circuit. For the given values, Q comes
out to be 3000. Because of very high Q, a crystal leads to oscillators with very stable frequency values.
The series resonant frequency fS of a crystal is the sonant frequency of the LCR branch. At this
frequency, the branch current reaches a maximum value because Ls resonant with CS.
Above fS, the crystal behaves inductively. The parallel resonant frequency is the frequency at which the
circulating or loop current reaches a maximum value. Since this loop current must flow through the
series combination of CS and Cm, the equivalent Cloop is
Since Cloop > CS, therefore, fp > fS.

Since Cm > CS, therefore, Cm || CS is slightly lesser than
CS. Therefore fP is slightly greater than fS. Because of the
other circuit capacitances that appear across Cm the
actual frequency will lie between fS and fP. fS and fP are
the upper and lower limits of frequency. The impedance
of the crystal oscillator can be plotted as a function of
frequency as shown in fig. 3.
At frequency fS, the circuit behaves like resistive circuit.

At fP the impedance reaches to maximum, beyond fP, the
circuit is highly capacitive.
The frequency of an oscillator tends to change slightly

with time. The drift is produced by temperature, aging and
other causes. In a crystal oscillator the frequency drift
6
with time is very small, typically less than 1 part in 10 per
day. They can be used in electronic wristwatches. If the
10 Fig. 3
drift is 1 part in 10 , a clock with this drift will take 30
years to gain or lose 1 sec.
Crystals can be manufactured with values of fs as low as 10 kHz; at these frequencies the crystal is
relatively thick. On the high frequency side, fs can be as high as 1- MHz; here the crystal is very thin.
The temperature coefficient of crystals is usually small and can be made zero. When extreme
temperature stability is required, the crystal may be housed in an oven to maintain it at a constant
temperature. The high Q of the crystal also contributes to the relatively drift free oscillation of crystal
oscillators.
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Example - 1
The parameters of the equivalent circuit of a crystal are given below:
L = 0.4 H, CS = 0.06 pF, R = 5 k, Cm = 1.0 pF.
Determine the series and parallel resonant frequencies of the crystal.
Solution:
With reference to fig. 2, the admittance of the crystal Y is given by
where,
and
The resonant frequencies are obtained by putting B = 0. Thus,
Consider the term CS R2 / LS = CS R / [L R]. In a crystal, the time constant (L / R) is very much greater
than CS R. Thus the ratio is very much less than 1. For the values given, this ratio is of the order of10-6.
Neglecting this term in comparison with 2, we get two roots as
where, s and p are the series and parallel resonant frequencies respectively. Substituting the values,
we get
s = 6.45 M Hz. and p = 6.64 MHz
Crystal Oscillators:
Fig. 4, shows a colpitts crystal oscillator.
Fi. 4
The capacitive voltage divider produces the feedback voltage for the base of transistor. The crystal acts
like an inductor that resonates with C1 and C2. The oscillation frequency is between the series and
parallel resonant frequencies.
Example-2:
If the crystal of example-1 is used in the oscillator circuit as shown fig. 5, determine the values of R for
the circuit to oscillate.
Fig. 5
Solution:
The equivalent circuit of crystal (discussed earlier) shows that it has a parallel resonant fr frequency
(p) at which the impedance becomes maximum. The amplified signal output of the circuit is applied
across the potential divider consisting of R and the crystal circuit. At the resonant frequency the
impedance of crystal becomes maximum (magnitude R) and thus the loop gain will be greater than or
equal to unity. At frequencies away from p the loop gain becomes less than unity. The loop base shift is
also zero around p. Thus both the conditions required for sustained oscillations are satisfied and the
circuit oscillates.
The value of G of the crystal at =p is given by
Thus the resistor R should be less than 5x106 .
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Lecture - 27: Voltage Regulators
Voltage Regulators:
An ideal power supply maintains a constant voltage at its output terminals under all operating
conditions. The output voltage of a practical power supply changes with load generally dropping as load
current increases as shown in fig. 1.
Fig. 1
The terminal voltage when full load current is drawn is called full load voltage (VFL). The no load
voltage is the terminal voltage when zero current is drawn from the supply, that is, the open circuit
terminal voltage.
Power supply performance is measured in terms of percent voltage regulation, which indicates its ability
to maintain a constant voltage. It is defined as
The Thevenin's equivalent of a power supply is shown in fig. 2. The Thevenin voltage is the no-load
voltage VNL and the Thevenin resistance is called the output resistance Ro. Let the full load current be
IFL. Therefore, the full load resistance RFL is given by
Fig. 2
From the equivalent circuit, we have

and the voltage regulation is given by
It is clear that the ideal power supply has zero outut resistance.
Example-1
A power supply having output resistance 1.5 supplies a full load current of 500mA to a 50 load.
Determine:
1. percent voltage regulation of the supply

2. no load output voltage.
Solution:
(a). Full load output voltage VFL = (500mA ) (50) = 25V.
Therefore,
(b). The no load voltage
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Lecture - 27: Voltage Regulators
Voltage Regulators:
An unregulated power supply consists of a transformer (step down), a rectifier and a filter. These power
supplies are not good for some applications where constant voltage is required irrespective of external
disturbances. The main disturbances are:
1. As the load current varies, the output voltage also varies because of its poor regulation.
2. The dc output voltage varies directly with ac input supply. The input voltage may vary
over a wide range thus dc voltage also changes.
3. The dc output voltage varies with the temperature if semiconductor devices are used.
An electronic voltage regulator is essentially a controller used along with unregulated power supply to
stabilize the output dc voltage against three major disturbances
a. Load current (IL)

b. Supply voltage (Vi)
c. Temperature (T)
Fig. 3, shows the basic block diagram of voltage regulator. where
Vi = unregulated dc voltage.
Vo = regulated dc voltage.
Fig. 3
Since the output dc voltage VLo depends on the input unregulated dc voltage Vi, load current IL and
the temperature t, then the change Vo in output voltage of a power supply can be expressed as follows
VO = VO(Vi, IL, T)
Take partial derivative of VO, we get,
SV gives variation in output voltage only due to unregulated dc voltage. RO gives the output voltage
variation only due to load current. ST gives the variation in output voltage only due to temperature.
The smaller the value of the three coefficients, the better the regulations of power supply. The input
voltage variation is either due to input supply fluctuations or presence of ripples due to inadequate
filtering.
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Lecture - 27: Voltage Regulator
Voltage Regulator:
A voltage regulator is a device designed to maintain the output voltage of power supply nearly constant.
It can be regarded as a closed loop system because it monitors the output voltage and generates the
control signal to increase or decrease the supply voltage as necessary to compensate for any change in
the output voltage. Thus the purpose of voltage regulator is to eliminate any output voltage variation
that might occur because of changes in load, changes in supply voltage or changes in temperature.
Zener Voltage Regulator:
The regulated power supply may use zener diode as the voltage controlling device as shown in fig. 4. The
output voltage is determined by the reverse breakdown voltage of the zener diode. This is nearly
constant for a wide range of currents. The load voltage can be maintained constant by controlling the
current through zener.
Fig. 4
The zener diode regulator has limitations of range. The load current range for which regulation is
maintained, is the difference between maximum allowable zener current and minimum current required
for the zener to operate in breakdown region. For example, if zener diode requires a minimum current
of 10 mA and is limited to a maximum of 1A (to prevent excessive dissipation), the range is 1 - 0.01 =
0.99A. If the load current variation exceeds 0.99A, regulation may be lost.
Emitter Follower Regulator:
To obtain better voltage regulation in shunt regulator, the zener diode can be connected to the base
circuit of a power transistor as shown in fig. 5. This amplifies the zener current range. It is also known
as emitter follower regulation.
Fig. 5
This configuration reduces the current flow in the diode. The power transistor used in this configuration
is known as pass transistor. The purpose of CL is to ensure that the variations in one of the regulated
power supply loads will not be fed to other loads. That is, the capacitor effectively shorts out high-
frequency variations.
Because of the current amplifying property of the transistor, the current in the zenor dioide is small.
Hence there is little voltage drop across the diode resistance, and the zener approximates an ideal
constant voltage source.
Operation of the circuit:
The current through resistor R is the sum of zener current IZ and the transistor base current IB ( = IL /
).
IL = IZ + IB
The output voltage across RL resistance is given by
VO = VZ VBE
Where VBE 0.7 V
Therefore, VO= constant.
The emitter current is same as load current. The current IR is assumed to be constant for a given supply
voltage. Therefore, if IL increases, it needs more base currents, to increase base current Iz decreases.
The difference in this regulator with zener regulator is that in later case the zener current decreases
(increase) by same amount by which the load current increases (decreases). Thus the current range is
less, while in the shunt regulators, if IL increases by IL then IB should increase by IL / or IZ should
decrease by IL / . Therefore the current range control is more for the same rating zener.
The simplified circuit of the shunt regulator is shown in fig. 6.

Fig. 6
In a power supply the power regulation is basically, because of its high internal impedance. In the
circuit discussed, the unregulated supply has resistance RS of the order of 100 ohm. The use of emitter
follower is to reduce the output resistance and it becomes approximately.
RO = ( Rz + hie ) / (1 + hfe)
Where RZ represents the dynamic zener resistance. The voltage stabilization ratio SV is approximately
SV = Vo / VI = Rz / (Rz + R)
SV can be improved by increasing R. This increases VCE and power dissipated in the transistor. Other
disadvantages of the circuit are.
1. No provision for varying the output voltage since it is almost equal to the zener voltage.
2. Change in VBEand Vz due to temperature variations appear at the output since the
transistor is connected in series with load, it is called series regulator and transistor is
allow series pass transistor.

Design of Series Voltage Regulator:
Fig. 1 shows the basic circuit of a series voltage regulator. The operation of this regulator has been discussed in
previous lecture. It consists of series (pass) transistor to control the output voltage.
Fig. 1
The circuit can be designed taking two extreme operating conditions,
1. VS max, IZ max, I load min /

2. VS min, IZ min, I load max /
We calculate R s for both conditions and since R si is constant, we equate these two expressions as in Equation E-1.
(E-1)
A design guideline that set IZ min = 0.1 I Z max. Then we equate the expressions for Equation (E-1) to obtain,
(E-2)
Solving for IZ max, we obtain,
(E-3)
We estimate the load resistance by taking the ratio of the minimum source voltage to the maximum load current.
Since R load is large and in parallel, it can be ignored. This is the worst case since it represents the smallest load and
therefore the maximum load current.
(E-4)
The output filter capacitor size can be estimated according to the permissible output voltage variation and ripple
voltage frequency and is given by
(E-5)
Since the voltage gain of an EF amplifier is unity, the output voltage of teh regulated power supply is,
Vload=VZ - VBE (E-6)
The percent regulation of the power supply is given by
(E-7)
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Example 1 (Design)
Design an 11.3V regulated power supply shown in fig. 1 for a load current that varies between 400 mA and 500 mA.
Assume an input of 120 V rms at 60 HZ into a 3:1 center - tapped transformer. Use a 12 V Zener with RZ = 2. The
transistor has VBE = 0.7 V and = 100. Set C so vs= 30%.
Solution:
The design consists of choosing the values for Rsand for CF. First VS max is obtained multiplying the rms voltage by 2.
VS max = 2 x 120 = 170 V
The transformer output on either side of the center tap is one-sixth of the input, so VS maxis 28.3V.
Since vs= 30%,

Therefore, VS min= (0.7)(VS max) = 30%
Given that ILoad max = 500 mA
and ILoad min= 400 mA
VZ= 12 V
The maximum Zener current can be obtained from equation (E-3) derived in previous lecture,
Notice that the transistor keeps the value of IZ max quite small since appears in the denominator.
The source resistance RS can be calculated from equation (E-1) of previous lecture,
Note that
The capacitor size is estimated from equation (E-5) of previous lecture:
Equation (E-7) can be used to evaluate the percent of regulation at the load.
Example 2:
For the circuit of fig. 2, determine the following:
a. Nominal output voltage

b. Value of R1
c. Load current range
d. Maximum transistor power dissipation
e. Value of RS and its power dissipation
The relevant information is as follows:
Vi = constant 8 V; D: 6.3 V, 200 mW; requires 5mA minimum current
Q: VEB= 0.2 V, hFE = 49, ICBO 0
Fig. 2
Solution:
a. The nominal output voltage is the sum of the transistor's VEB and the Zener voltage:
V O = 0.2 + 6.3 = 6.5 V
b. R1 must supply 5mA to the Zener:
c. The maximum allowable Zener current is
P / V =0.2 / 6.3 = 31.8 mA
The load current range is the difference between minimum and maximum current through the shunt path provided by
the transistor. At junction A, we can write
I B = IZ I 1 ;
I1 is a constant 5 mA; therefore
-3 -3
IB =IZ I1 = (5 x 10 ) (5 x 10 ) = 0
-3 -3
IB =IZ I1 = (31.8 x 10 ) (5 x 10 ) = 26.8 mA
The transistor's emitter current is (hFE + 1) (IB). IB ranges from a minimum of around zero to a maximum of 26.8 mA;
-3
therefore the load current range is (hFE + 1) (26.8 x 10 ) = 1.34 A. The Zener alone could provide a maximum range
of 26.8mA.
d. The maximum transistor power dissipation occurs when the current is maximum. Using I E IC, we have
PD = VO IZ = 6.5 (1.34) =8.7 W
e. RS must pass 1.34 A to supply current to the transistor and RL:
The power dissipated by RS is
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Series Regulators:
Voltage regulators may be classified as series regulators or shunt regulators. Improvements in performance of
voltage regulators are possible using the series regulator. Fig. 3 shows a functional block diagram of the series type
voltage regulator.
Fig. 3
The control element is a device which is in series with load and supply and its operating state adjusts as necessary to
maintain a constant voltage Vo. A measuring circuit produces a feedback voltage proportional to Vo and this voltage is
compared with a reference voltage. The output of the comparator circuit is the control signal that adjusts the
operating state of the control element. If Vo decreases, due to increased in load, then the comparator produces a
output that causes to control element to increase the output voltage.
The amplifier is of the differential input type; one input is V s, while the other is Vr, a constant reference voltage. The
reference may be a Zener diode or a dry cell. The amplifier output is proportional to the difference between its two
inputs; this difference is called the error signal and may be expressed as follows:
e = VS -Vr
The amplifier multiplies the error by a constant K, yielding an appropriate signal to the control element. The function
of the signal is to increase or decrease the effective resistance of the control element, depending on whether V O is
too high or too low, respectively.
For example, if VO should increase, the error voltage e' also increases. The amplifier's output therefore increase; this
causes the resistance of the control element to increase, therefore reducing the load current and load voltage. Note
that the original increase in VO caused the circuit to act in such a manner as to decrease V O . It is because of this
negative feedback that we are able to achieve control over the load voltage.
A circuit that operates on the above principle is shown in fig. 4. R3, R4, and R5 make up the sampling network. The
current through the sampling network must be sufficiently large that, whatever current the base of Q 2 draws, the
loading on the voltage divider is negligible and VO remains an accurate sample to VO.
Fig. 4
It is possible to simply eliminate R3 and R5 and leave only R4, but there is the danger that in setting the potentiometer
one will go to either extreme, in which case the transistor may be damaged. None of the transistor is critical; R 4 is
variable to allow setting of the output voltage.
The sample voltage Vs is applied to the base of Q2, while the reference voltage Vr, which is provided by Zener diode
D1, is applied to the emitter. R2 sets the Zener current; in addition to ensuring that the Zener operates in the
breakdown region, the Zener's temperature coefficient, which is both voltage- and current-dependent, may be
controlled by an appropriate selection of current through R2. This way the Zener's temperature coefficient (usually
positive) may be used to cancel the transistor's VBE temperature dependence (usually negative).
The error voltage is Vs -Vr, or simply VBE. Q2 yields an output current (IC2) which is proportional to this error. At
junction A the following expression may be written
IC2 + IB1 = I1
If I1 is constant, changes in IC2 yield equal but opposite changes in IB1; that is, if IC2 rises, IB1 drops. Changes in IB1are
amplified by Q1 to yield corresponding changes in IE1 and IO. As the current through it changes, Q1 appears as a
variable resistor whose resistance depends on the control current I B1. If IB1 drops, the resistance of Q1 increases,
allowing less current to flow through the load.
It is important to note that is type of corrective action is effective only as long as I 1 remains reasonably constant. This
is to ensure that IB1 changes mainly in response to variations in IC2 (which are due to the error signal). If I1 is not
constant, it is possible for IB1 (and hence IO and VO) to change in response to I1 variations which do not reflect
conditions in the load circuit.
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Example 1
The following data apply to a voltage regulator circuit

shown in fig. 1
Unregulated input: Vi = 15 to 20V
Desired output: VO = 10V
Load current requirements: IO = 0 to 0.1 A
Zener diode voltage = 6.8V
hFE min = 15
hFE max = 50
Both transistors are the silicon planer type with

negligible ICBO. Determine
1. Extreme values of RL
2. Maximum value of IB1
3. Suitable value for R1
4. Extreme values of I1
5. Value of R2 if D1 requires a minimum
of 5 mA
6. Worst-case power dissipation for
Q1 under normal operating conditions Fig. 1
7. Worst-case power dissipation for
Q2 under normal operating conditions
Solution
(a). Since RL = VO / IO, we can write
The maximum load current is zero; therefore the load resistance is anywhere from 100 to an open
circuit.
(b). The base current of Q1 is IE1 (hFE1 + 1), where IE1 is the sum of load current IO, current through
the sampling network, and current through R2. Usually IO is the largest component involved; therefore
(c). R1 should supply the maximum current required by the base of Q1. This is 6.66 mA; however, it is a
good practice to increase it by about 50 percent to provide a safety margin. We therefore select R1 on
the basis that its current must never drop below 10 mA:
(d). The extreme values of I1 are determined using the extreme values of Vi:
(e).
(f). Worst-case power dissipation for Q1 occurs when both the voltage and current are maximum.
Normally the collector-base junction dissipates the most power, since its voltage is much greater than
VBE; however, the total transistor dissipation involves both junctions. This can be approximated as
follows:
Voltage across Q1: VCE1 = Vi VO

Current through Q1: IC1 IE1 IO
PE1 (Vi VO) (IO)
PD1 (20 10) (0.1) = 1 W
(g). Q2 does not handle large currents as Q1 does; therefore its power dissipation is relatively low:
PD2 = (VCE2) (IC2)
Both VA and Vr are relatively constant; therefore VCE2 is also constant:
VCE2 = VA Vr = VO + VEB1 Vr
VCE2 = 10 + 0.6 6.8 = 3.8 V
The maximum value of IC2 is approximately equal to I1 = 21.4 mA; we, therefore, have
PD2 VCE2 IC2

PD2 4(21.4 x 10-3) = 81.5 mW
Note that the current through R1 in this example does not remain constant; in fact, it can vary between
10 and 21.4 mA, a total range of 11.4 mA. The regulator would perform much better if I1 were
regulated.
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Example 2
Determine R1 and extreme values of I1 in the

circuit of Example-1, if Q 1 is replaced with the
compound connection of fig. 2. Assume both
transistors have a minimum hFE of 15 and
negligible cutoff currents.
Solution:
The current through R1 should be selected

about 50 percent higher than the maximum
current required by the base of Q12. For worst-
case design, the minimum hFE of 15 is used,
yielding a composite hFE 15 (15) = 225 for
both Q11 and Q12. This yields
Fig. 2
We now select I2 0.65 mA; R1 is calculated as follows:
where,
The extreme values of I1 occurs when Vi is at its extremes. The minimum I1 is 0.65mA (as indicated
above), while the maximum is
The variation in I1 is 1.5 - 0.65 = 0.85mA.
Example - 3
In the regulator shown in fig. 3 R1 = 50K, R2 = 43.75K and VZ = 6.3V. If the 15 V output drops 0.1
V, find the change in VBE2 that results.
Fig. 3
Solution:
When VO = 15 V,
Therefore, VBE2 = V2 - VZ = 7 V - 6.3 V = 0.7 V. When VO = 15 V - 0.1 V = 14.9 V, V2 becomes
Therefore,
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Operational Amplifier Voltage Regulator:
Fig. 4, shows how an operational amplifier is used in a series voltage regulator. Resistor R1 and R2 form
avoltage divider that feeds a voltage proportional to VO back to the inverting input: V- = VO R2 / (R1 +
R2)). The zener voltage VZ on the noninverting input is greater than V-, so the amplifier output is
positive and is proportionate to VZ -V-. If VOdecreases, V- decreases, and amplifier ouput increases.
The greater voltage applied tothe base of the pass transistor causes it to conduct more heavily, and
VO increases. Similarly, an increase in VO causes V- to increase, VZ - V1 to decreases, and the amplifier
output to decrease. The pass transistor conducts less heavily and VO decreases.
Fig. 4
The operational amplifier in fig. 4 can be regarded as a noninverting configuration with input VZ and
gain
Therefore, neglecting the base to emitter drop of the pass transistor, the regulated output voltage is
R3 is chosen to ensure that sufficient reverse current flows through the zener diode to keep it in
breakdown.
Example - 4
Design a series voltage regulator using an opertional amplifer and a 6V zener diode to maintain a
regulated output of 18V. Assume that the unregulated input varies between 20V and 30V and that the
current through the zener diode must be at least 20 mA to keep it in its breakdown region.
Solution:
From the output voltage expression 18 V = ( 1 + R1 / R2) 6 V.

Thus, (1 + R1 / R2) = 3.
Let R1 = 20K, Then,
The current through R3 is

Since the current into the noninverting input is negligibly small, the current in R3 is the same as the
current in the zener dode. This current must be at least 20 mA, so the smallest possible value of V2(20
V):
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Series regulator with Current Pre-regulator
The circuit of fig. 1 is an improved version of series voltage regulator discussed in previous lecture.
Besides Q1 being replaced with a current regulator circuit. The function of D2, R6, R7, and Q3 is to
establish and maintain a constant I1.
Fig. 1
The circuit works this way :- I1 is the collector current of Q3, and hence it is also approximately equal to
IE3. The voltage at the base of Q3 relative to V1 is held at a constant level by D2; current through R6 is
selected to keep D2 in breakdown and to yield the proper temperature coefficient. Should I1 rise,
IE3 will also rise, increasing the voltage across R1. This reduces VEB3, which in turn reduces IE3 and
I1. Thus I1 is regulated and remains fairly constant even if there are changes in the unregulated input.
One disadvantage of this circuit is that a larger input voltage is required to supply the various voltage
drops between Vi and Vo. In this case Vi must supply Vo plus the two VEB drops of Q11 and
Q12 (which takes us to point A), plus the collector-base bias for Q3 (which takes us to the base Q3), plus
the Zener voltage for D2.
Power Supply Using IC Regulator (Three-Terminal Regulator)
Monolithic integrated circuits have greatly simplified the design of a wide variety of power supplies.
Using a single IC regulator and a few external components, we can obtain excellent regulation (on the
order of 0.01%) with good stability and reliability and with overload protection.
IC regulators are produced by a number of manufacturers. The IC regulator improves upon the
performance of the Zener diode regulator. It does this by incorporating an operational amplifier. In this
section, we present basic design considerations for IC regulators. These techniques are useful in the
design of power supplies for a variety of low power applications. We consider the internal theory of
operation of these and other three-terminal voltage regulators in the current section. These products
vary in the amount of output current. The most common range of output current is 0.75 A to 1.5 A
(depending on whether a heat sink is used).
Fig. 2
The functional block diagram of fig. 2 illustrates the method of voltage regulation using this series
regulator. The name series regulator is based on the use of a pass transistor (a power transistor) which
develops a variable voltage which is in "series" with the output voltage. The voltage across the pass
transistor is varied in such a manner as to keep the output voltage constant.
A reference voltage, VREF, which is often developed by a Zener diode, is compared with the voltage
divided output, vout. The resulting error voltage is given by
The error voltage v e is amplified through a discrete amplifier or an operational amplifier and used to
change the voltage drop across the pass transistor. This is a feedback system which generates a variable
voltage across the pass transistor in order to force the error voltage to zero. When the error voltage is
zero, we obtain the desired equation by solving equation (Equ-1) for vout .
Thermal shutdown and current-limit circuitry exists between the error amplifier and the pass
transistor. This circuitry protects the regulator in case the temperature becomes too high or an
inadvertent short circuit exists at the output of the regulator.
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The maximum power dissipated in this type of series regulator is the power dissipated in the internal
pass transistor, which is approximately (VS max - Vout) IL max. Hence, as the load current increases,
the power dissipated in the internal pass transistor increases. If ILoad exceeds 0.75 A, the IC package
should be secured to a heat sink. When this is done, ILoad can increase to about 1.5 A.
We now focus our attention on the 78XX series of regulators. The last two digits of the IC part number
denote the output voltage of the device. Thus, for example, a 7808 IC package produces an 8V regulated
output. These packages, although internally complex, are inexpensive and easy to use.
There are a number of different voltages that can be obtained from the 78XX series 1C; they are 5, 6, 8,
8.5, 10, 12, 15, 18, and 24 V. In order to design a regulator around one of these ICs, we need only select a
transformer, diodes, and filter. The physical configuration is shown in fig. 3(a). The ground lead and the
metal tab are connected together. This permits direct attachment to a heat sink for cooling purposes. A
typical circuit application is shown in fig. 3(c).
(a) (b)
(c)
Fig. 3
The specification sheet for this IC indicates that there must be a common ground between the input and
output, and the minimum voltage at the IC input must be above the regulated output. In order to assure
this last condition, it is necessary to filter the output from the rectifier. The CF in fig. 3(b) performs this
filtering when combined with the input resistance to the IC. We use an n:1 step down transformer, with
the secondary winding center-tapped, to drive a full-wave rectifier.
The minimum and maximum input voltages for the 78XX family of regulators are shown in Table-1.
Type Min Max

7805 7 25
7806 8 25
7808 10.5 25
7885 10.5 25
7810 12.5 28
7812 14.5 30
7815 17.5 30
7818 21 33
7824 27 38
Table - 1
We use Table -1 to select the turns ratio, n, for a 78XX regulator. As a design guide, we will take the
average of Vmaxand Vmin of the particular IC regulator to calculate n. For example, using a 7805
regulator, we obtain
The center tap provides division by 2 so the peak voltage out of the rectifier is 115 2 / 2n = 16.
Therefore, n = 5. This is a conservative method of selecting the transformer ratio.
The filter capacitor, CF, is chosen to maintain the voltage input range to the regulator as specified in
Table 8.1.
The output capacitor, CLoad, aids in isolating the effect of the transients that may appear on the
regulated supply line. CLoad should be a high quality tantalum capacitor with a capacitance of 1.0 F.
It should be connected close to the 78XX regulator using short leads in order to improve the stability
performance.
This family of regulators can also be used for battery powered systems. Fig. 3(c) shows a battery
powered application. The value of CF is chosen in the same manner as for the standard filter.
The 79XX series regulator is identical to the 78XX series except that it provides negative regulated
voltages instead of positive.
Example-1
Design an IC circuit regulator to generate a 12 V output into a load whose current varies from 100 mA
to 500 mA. The input is 115 V rms at 60 HZ.
Solution:
We use the circuit of fig. 3(b) with a 7812 regulator. The center-tapped transformer and full-wave
rectifier must produce a minimum voltage of at least 14.5 V and a maximum voltage of no more than
30V. This information is obtained from Table 8.1. The input peak voltage is 115 2 or 163 V. The center-
tapped secondary divides this by 2 to yield 81.5V. Let us choose the mid-point between 14.5 and 30, or
22.25 V to select the transformer ratio. This yields a transformer ratio of 81.5 / 22.25 or 3.68.
Since Vs min= 14.5 V (from Table 8.1) and Vs max= 22.3 V, we have
We have used the fact that
V = 22.3 14.5 = 7.8 V
and
Rload (worst case) = 29
The value of C load is determined by the types of variations that occur in the load. A typical selection for
this application is a 1.0 F high quality tantalum capacitor.
GOTO >> 1 || 2 || Home

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Lecture - 1: Operational Amplifiers

The differential amplifiers are of different configurations.

1. Dual input, balanced output differential amplifier.

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Applying KVL to the base emitter loop of the transistor Q1.

VCE = VCC + VBE ICRC (E-2)

The value of ICQ can be obtained from equation (E-1).

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Applying KVL in two loops 1 & 2.

Substituting current relations,

The output voltage VO is given by

= -RC iC2 - (-RC iC1)

Substituting ie1, & ie2 in the above expression

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The factor of 2 arises because the re' of each transistor is in series.

RO1 = RO2 = RC (E-5)

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a. Determine the voltage gain.

The ac emitter resistance

Ro1 = Ro2 = 2.2 k

For the dual input, balanced output differential amplifier of Example-1:

Substituting IC = ICQ = 0.988 mA, we get

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Inverting & Non inverting Inputs:

In differential amplifier the output voltage vO is given by

Common mode Gain:

The output voltage, therefore can be expressed as

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The output voltage gain in this case is given by

Differential amplifier with swamping resistors:

Thus, ICQ = 0.988 mA

Repeat Example-1 for single input, balanced output differential amplifier.

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The voltage at the base of transistor QB is

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Design a zener constant current bias circuit as

From fig. 6 using KVL we get

The voltage at the base of transistor Q3 is

Assuming that the transistor Q3 has the same

To obtain the differential gain of 60, the

The following fig. 7 shows the dual input,

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The block diagram of OPAMP is shown in fig. 1.

Thus a dc voltage at the base of Q produces 0V dc at the output. It is

In this case, level shifter, which is common collector amplifier, shifts

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For the cascaded differential amplifier shown in fig. 5, determine:

That is, IC1 = IC2 =0.988 mA.

VC1 = VCC = -RC1 IC1 = 10 (2.2k) (0.988 mA) = 7.83 V = VC2

Since the voltage at the emitter of Q1 and Q2 is -0.715 V,

VCE1 = VCE2 = VC1 -VE1 = 7.83 + 0715 = 8.545 V

VCC RC2 IC2 = VBE3 - R'E IC3 - RE2 (2 IE3) + VBE= 0

VC3 = VC4= VCC RC3 IC3 = 10 (1.2k) (0.569 mA)

VCE3 = VVCE4 = VC3 VE3 = 9.32 7.12 = 2.2 V

Thus, for Q1 and Q2:

Ri2 = input resistance of the second stage

Ad= (Ad1) (Ad2) = (80.78) (4.17) = 336.85

Ri = 2ac(re1) = (200) (25.3) = 5.06 k

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The dc conditions for each state

From the dc equivalent circuit,

b) The overall voltage gain of the amplifier can be obtained as below: