DRM064

Single Phase On-Line
UPS Using MC9S12E128
Designer Reference Manual
HCS12
Microcontrollers
DRM064
Rev. 0
09/2004
freescale.com
Single Phase On-Line UPS Using MC9S12E128
Designer Reference Manual
by: Ivan Feno, Pavel Grasblum and Petr Stekl

Freescale Semiconductor Czech System Laboratories
Roznov pod Radhostem, Czech Republic
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Revision Page
Date Description
Level Number(s)
09/2004 0 Initial release N/A
Freescale Semiconductor 3
4 Freescale Semiconductor
Contents
Chapter 1
Introduction
1.1 Application Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2 The UPS Topologies and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2.1 Passive Standby UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.2.2 Line-Interactive UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2.3 On-Line UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3 MC9S12E128 Advantages and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 2
System Description
2.1 System Concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 System Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chapter 3
UPS Control
3.1 Control Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.1 Battery Charger Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.2 Power Factor Correction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.3 dc/dc Step-Up Converter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1.4 Output Inverter Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1.5 PI and PID Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.6 Phase-Locked Loop (PLL) Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Chapter 4
Hardware Design
4.1 System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2 Battery Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.1 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.2 Battery Charger Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2.3 Flyback Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.2.4 Design of Flyback Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.2.5 Voltage and Current Sensing, Current Limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2.6 Main Line Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2.7 Battery Charger Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3 Auxiliary Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.3.1 Auxiliary SMPS Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4 dc/dc Step-Up Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.4.1 dc/dc Converter Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.4.2 dc/dc Converter Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.5 Power Factor Correction and Output Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Contents
4.5.1 PFC Booster Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.5.2 PFC Booster Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.5.3 Output Inverter Operational Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.5.4 Output Inverter Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Chapter 5
Software Design
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2.1 Software Variables and Defined Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2.2 Process PLL Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2.3 Process RMS Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2.4 Process Mains Line Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2.5 Process Ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2.6 Process Sine Wave Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2.7 Process Button Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2.8 Process LED Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2.9 Process Application State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2.10 Process PFC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.2.11 Process Sine Wave Reference (PFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.2.12 Process dc Bus Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.2.13 Process dc/dc Step-Up Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.2.14 Process Inverter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.2.15 Process Battery Charge Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3 Main Software Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3.1 Initialization of Peripherals and Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3.2 Periodic Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.3.3 Event Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.4 Interrupt Time Execution and MCU Load Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.4 Software Constant Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.4.1 PI and PID Controller Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Chapter 6
Tests and Measurements
6.1 Test Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.2 Load Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.1 Overall Efficiency at Linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.2 Overall Efficiency at Non-linear Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.3 Output Frequency Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.4 Output Voltage THD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.5 Power Factor Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.6 Response on Step Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Chapter 7
System Set-Up and Operation
7.1 Hardware Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.1.1 Setting of Mains Line System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.2 Software Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.2.1 Application Software Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.2.2 Application PC Master Software Control Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.2.3 Application Build. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.2.4 Programming the MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.3 Application Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.3.1 On-line Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.3.2 Battery Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.3.3 Remote Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Appendix A. Schematics
A.1 Schematics of Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
A.2 Schematics of User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
A.3 Schematics of Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
A.4 Parts List of UPS Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
A.5 Parts List of User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
A.6 Parts List of Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Appendix B. References
Appendix C. Glossary
Contents
Figures
1-1 Passive Standby UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1-2 Line-Interactive UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1-3 On-Line UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2-1 System Concept of UPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2-2 UPS Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2-3 Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2-4 User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2-5 MC9S12E128 Controller Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2-6 Overall View of the UPS Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3-1 Battery Charger Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3-2 PFC Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3-3 Hysteresis Control of Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3-4 Push-Pull Converter PWM Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3-5 dc/dc Step-Up Converter Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3-6 Sine Wave Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3-7 Inverter Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3-8 Simulated PID Controller Response on Input Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3-9 Quality Control of Non-Linear Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3-10 Calculation of Phase Difference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4-1 System Concept of UPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4-2 UPS Power Stage Block Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4-3 Battery Charger Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4-4 Battery Charger Transformer Winding Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4-5 3-Stage Charging Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4-6 Auxiliary SMPSs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4-7 Isolated Flyback Converter for Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4-8 Flyback Power Transformer Layout of Windings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4-9 dc/dc Converter Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4-10 dc/dc Converter Simulation Model Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4-11 Simulated Magnetizing Voltage and Magnetic Charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4-12 Simulated Primary Winding Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4-13 Simulated Secondary Winding Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4-14 Simulated Drain-to-Source and Gate-to-Source MOSFETs Voltages. . . . . . . . . . . . . . . . . . 55
4-15 dc/dc Power Transformer Layout of Windings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4-16 Inverter MOSFET Power Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4-17 Rectifier Diode Voltage and Current Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4-18 Secondary Voltage and Rectified Current Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4-19 PFC Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4-20 PFC Current Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4-21 Output Inverter Power Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4-22 Inverter IGBT Gate Drive Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5-1 Main Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figures
5-2 Application State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5-3 Background Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5-4 Structure of PMF Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5-5 Structure of ATD Conversion Complete Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5-6 TIM0 CH4 Input Capture Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5-7 Structure of TIM0 CH5 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5-8 Structure of TIM0 CH6 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5-9 CPU Load of UPS Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6-1 Non-Linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6-2 Overall Efficiency at Linear Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6-3 Output Voltage and Current at Linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6-4 Overall Efficiency at Non-linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6-5 Output Voltage and Current at Non-linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6-6 Output Frequency in Synchronized Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6-7 Output Frequency in Free-running Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6-8 Output Voltage and Current at Non-linear Load Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6-9 Output Voltage and Current at Non-linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6-10 Power Factor Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6-11 Load Step from 20% to 100% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6-12 Load Step from 20% to 100% Detail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6-13 Load Step from 100% to 20% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6-14 Load Step from 100% to 20% Detail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7-1 UPS Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7-2 UPS Input and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7-3 UPS Serial Ports and External Battery Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7-4 Execute Make Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7-5 UPS User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7-6 UPS Project in FreeMaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7-7 Block Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7-8 Auxiliary Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7-9 Battery Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7-10 Control Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7-11 dc/dc Step-Up Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7-12 Analog Sensing Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7-13 PFC and Inverter IGBT Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7-14 PFC and Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7-15 PFC Current Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7-16 UPS User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Tables
2-1 On-Line UPS Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4-1 Battery Charger Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4-2 Input Design Parameters of Flyback Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4-3 Required Parameters of Flyback Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4-4 Measured Values on the Sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4-5 dc/dc Converter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4-6 dc/dc Transformer Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4-7 Digital PFC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4-8 PFC Inductor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4-9 Design Parameters for Core P/N: T175-8/90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4-10 dc-bus Capacitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4-11 Output Inverter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4-12 MKP 338 4 X2 Capacitor Reference Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4-13 Output Filter Inductor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4-14 Design Parameters for Core P/N: T175-8/90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5-1 Software Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5-2 Execution Time of Periodic Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5-3 Size of UPS Application Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6-1 Summary of Measured Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
A-1 Parts List of UPS Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
A-2 Parts List of User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
A-3 Parts List of Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Freescale Semiconductor Freescale Semiconductor Internal Use Only 11
Draft For Review - September 30, 2004

Tables
12 Freescale Semiconductor Internal Use Only Freescale Semiconductor
Draft For Review - September 30, 2004

Chapter 1
Introduction
1.1 Application Outline

This reference design describes the design of a single phase on-line uninterruptable power supply (UPS).
UPSs are used to protect sensitive electrical equipment such as computers, workstations, servers, and
other power-sensitive systems.
This reference design focuses on the digital control of key parts of the UPS system. It includes control of
a power factor correction (PFC), a dc/dc step-up converter, a battery charger, and an output inverter. The
dc/dc converter and the output inverter are fully digitally controlled. The PFC and the battery charger are
implemented by a mixed approach, where an MCU controls the signals for PFC current and battery
current demands. The digital control is based on Freescale Semiconductors MC9S12E128
microcontroller, which is intended for UPS applications.
The reference design incorporates both hardware and software parts of the system including hardware
schematics.
1.2 UPS Topologies and Features

UPSs are divided into several categories according to their features, which come from the hardware
topologies used. The three basic categories are:
Passive standby UPS
Line-interactive UPS
On-line UPS
The category of the UPS defines the basic behaviors of the UPS, mainly the quality of the output voltage
and the capability to eliminate different failures on the power line (power sags, surge, under voltage, over
voltage, noise, frequency variation, and so on).
NOTE
Although specific tools, suppliers, and methods are mentioned in this
document, Freescale Semiconductor does not recommend or endorse any
particular methodology, tool, or vendor.
Introduction
1.2.1 Passive Standby UPS Topology

The common topology of the passive standby UPS is depicted in Figure 1-1.
LINE FILTER
BATTERY
CHARGER
AC AC SWITCH
~ = = ~
DC DC
INVERTER
+ - Normal operation
Backup operation
BATTERY
Figure 1-1. Passive Standby UPS Topology
During normal operation, while the mains line (the power cord for the ac line) is available, the load is
directly connected to the mains. The battery is charged by the charger, if necessary. If a power failure
occurs, the switch switches to the opposite position, and the load is powered from the batteries. An
inverter converts the battery dc voltage level to an ac mains level. The inverter generates a square wave
output.
The advantage of passive standby topology is its low cost and high efficiency. The disadvantage is limited
protection against power failures. Because the load is connected to the mains line through the filter only,
the load is saved against short sags and surges.
UPS Topologies and Features
1.2.2 Line-Interactive UPS Topology

The improved topology, called line-interactive, is showed in Figure 1-2. The functionality of the
line-interactive UPS is similar to passive standby topology. During normal operation, the load is
connected directly to the mains line (the power cord to the ac line). Besides the input filter, there is a
transformer with taps connected between the mains line and the load. The transformer usually has three
taps. It ensures that the output voltage can be increased or decreased relative to the mains line by
typically 10 to 15%.
The features of the line-interactive topology are similar to passive standby UPSs. The cost is still quite
low and efficiency is high. The protection against power failures is improved by the possibility of keeping
the output voltage within limits during under voltage or over voltage using the tap transformer.
BYPASS
LINE FILTER AVR
BATTERY
CHARGER
AC AC SWITCH
~ = = ~
DC DC
INVERTER
Backup operation
BATTERY
Figure 1-2. Line-Interactive UPS Topology
Introduction
1.2.3 On-Line UPS Topology

Another topology, called on-line, is shown in Figure 1-3. This topology is also called double conversion.
This name arises from the operating principle of an on-line UPS. When the UPS works in normal operation
mode, while the mains line (or the power cord for the ac line) is available, the input voltage is rectified to
the dc bus. The power factor correction ensures a sinusoidal current in phase with the input voltage. Then
the UPS behaves as a resistive load. The output inverter converts the dc bus voltage back to a pure
sinusoidal voltage.
The dc/dc converter is connected to the dc bus and converts the battery voltage to the dc bus level. The
converter is activated during a power failure, and delivers the energy stored in the batteries to the dc bus.
The dc bus voltage is again converted to a pure sine voltage.
A battery charger is used to charge the batteries. The charger can be powered from the mains line or from
the dc bus.
BYPASS
RECTIFIER PFC
IN
DC
OUT
BATTERY
= ~
CHARGER AC
AC DC INVERTER
~ = = =
DC DC
DC-DC
CONVERTER
Backup operation
BATTERY
Figure 1-3. On-Line UPS Topology
As can be seen, the complexity of the on-line UPS is much greater than the other two topologies
described in this section. This means that the cost is higher, and the efficiency is lower due to double
conversion.
However, the on-line UPS brings a much higher quality of delivered energy. The UPS generates a pure
sine wave output with tight limits (typically 2%). Besides the power failures eliminated by previous
topologies, the on-line UPS avoids all the failures relating to frequency disturbance, such as frequency
variation, harmonic distortion, line noise, or other shape distortions.
MC9S12E128 Advantages and Features
1.3 MC9S12E128 Advantages and Features

The MC9S12E Family is a 112-/80-pin low-cost 16-bit MCU family very suitable for UPS, SMPS, and
motor control applications. All members of the MC9S12E Family contain on-chip peripherals including a
16-bit central processing unit (HCS12 CPU), up to 256K bytes of Flash EEPROM, up to 16K bytes of
RAM, three asynchronous serial communications interface modules (SCI), a serial peripheral interface
(SPI), an inter-IC bus (IIC), three 4-channel 16-bit timer modules (TIM), a 6-channel 15-bit pulse-width
modulator with fault protection module (PMF), a 6-channel 8-bit pulse width modulator (PWM), a
16-channel 10-bit analog-to-digital converter (ATD), and two 1-channel 8-bit digital-to-analog converters
(DAC).
The basic features of the key peripherals dedicated for UPS applications are listed below:
Two 1-channel digital-to-analog converters (DAC) with 8-bit resolution
Analog-to-digital converter (ATD)
16-channel module with 10-bit resolution
External conversion trigger capability
Three 4-channel timers (TIM)
Programmable input capture or output compare channels
Simple PWM mode
Counter modulo reset
External event counting
Gated time accumulation
6 PWM channels (PWM)
Programmable period and duty cycle
8-bit 6-channel or 16-bit 3-channel
Separate control for each pulse width and duty cycle
Center-aligned or left-aligned outputs
Programmable clock select logic with a wide range of frequencies
Fast emergency shutdown input
6-channel pulse width modulator with fault protection (PMF)
Three independent 15-bit counters with synchronous mode
Complementary channel operation
Edge and center aligned PWM signals
Programmable dead time insertion
Integral reload rates from 1 to 16
Four fault protection shut down input pins
Three current sense input pins
The MC9S12E Family is powerful enough to control on-line and line-interactive UPS topologies. The
passive standby topology can be controlled by a simpler MCU (from the HC08 Family).
Digital control has many advantages over separate analog control. Digital control is more flexible and
allows easier tuning and changing of the UPS parameters. The intercommunication and interaction
between all modules can implemented very efficiently because all modules are controlled by a single
MCU.
The UPS control area is very wide. Each topology can be implemented by different circuits. The circuits
may differ by different control requirements. This reference design shows one of the ways to implement
digital control of an on-line UPS. The design mainly focuses on low cost. A low-cost 16-bit MCU is used
with simple analog circuits. Using a mixed approach to battery charging can also be cheaper than full
digital control, depending on chosen circuit topology.
Introduction
Chapter 2
System Description
2.1 System Concept

The system concept of the UPS is shown in Figure 2-1. Input consists of a rectifier (D1, D5) and a power
factor correction (L1, D2, Q2). The power factor correction is controlled by a mixed approach. The dc-bus
voltage control loop of PFC is controlled by the MCU. The output of the voltage controller defines the
amplitude of the input current. Based on the required amplitude, the MCU generates a current reference
signal. The current reference signal inputs to an external logic, which performs current controller working
in hysteresis mode.
DC-AC
PFC
L1
D1
D2
KBU8J Q1 D3
IN - + + C1
Q2
IN
C2 + D4
Q3
GND
OUT
D5
Filter
OUT
DC-DC Converter
D6
D7 L2
Q4
T1
GND
Q5
D8 L3
Charger
(Flyback
Converter) BT1 D9
GND
GND
Figure 2-1. System Concept of UPS

Output is provided by an output inverter (Q1, Q3, D3, D4). The inverter converts the dc bus voltage back
to a sinusoidal voltage using pulse-width modulation. The output inverter is fully controlled by the MCU
and generates a pure sinusoidal waveform, free of any disturbance.
System Description
The battery BT1 supplies a load during the backup mode. There are two 12-V batteries connected in
serial. The battery voltage level 24-V is converted to 390-V by the dc/dc step-up converter (Q4, Q5,
D6-D9, L2, L3, and T1) using a push-pull topology fully controlled by the MCU.
The last part of a UPS is a battery charger. The battery charger maintains a fully charged battery. It uses
a flyback topology controlled by a mixed approach. The flyback converter is controlled by a dedicated
circuit and the required output voltage and current limit are set by the MCU. A dedicated circuit is used
due to the lower cost compared to direct MCU control. Where a different battery charger topology is used,
there is still enough MCU power to provide digital control.
Figure 2-2. UPS Power Stage

The UPS consists of four PCBs. Most components are situated on the power stage (see Figure 2-2).
These are all the power components (diodes, transistors, inductors, capacitors, relays, and so on) and
analog sensing circuits. The power stage is connected to the mains line (power cord for the ac line)
through an input line filter, realized on the next PCB (Figure 2-3).
Figure 2-3. Input Filter
System Concept
Figure 2-4 shows the user interface PCB. It includes two buttons (ON/OFF, BYPASS), four status LEDs
(on-line, on-battery, bypass, and error), and six LEDs indicating output power or remaining battery
capacity. There are also two serial RS232 ports, which can used for communication with the PC. The user
interface provides an extension of the serial ports, which are implemented on the MC9S12E128 controller
board.
Figure 2-4. User Interface
Figure 2-5. MC9S12E128 Controller Board
System Description
Figure 2-5 shows a controller board for the MC9S12E128. The MC9S12E128 controller board is designed
as a versatile development card for developing real-time software and hardware products to support a
new generation of applications in UPS, servo and motor control, and many others.
The power of the 16-bit MC9S12E128, combined with Hall-effect/quadrature encoder interface, circuitry
for automatic current profiling, over-current logic and over-voltage logic, and two isolated RS232
interfaces, makes the MC9S12E128 controller board ideal for developing and implementing many motor
controlling algorithms, UPS, SMPS, as well as for learning the architecture and instruction set of the
MC9S12E128 processor.
For more detailed information on the MC9S12E128 controller board, see [33].
An overall view of the assembled UPS is shown in Figure 2-6.
Figure 2-6. Overall View of the UPS Demo
2.2 System Specification

The UPS is designed to meet the features and parameters mentioned in Table 2-1.
System Specification
Table 2-1. On-Line UPS Specification

Features Parameters
Single Phase On-Line UPS using MC9S12E128
Architecture and Concept The UPS should be a regenerative 1-phase online type UPS with an automatic bypass
feature when self check fails or is overloaded. The UPS is controlled manually from a front
panel switch and from PC application software.
On-line: If the input power is available, the UPS supplies a load and eliminates all possible
defects on the line (online double conversion)
Battery: If the input power is not available, the UPS supplies a load from batteries. The
backup time is given by battery capacity.
Functional Modes Bypass: The UPS directly connects its output and input, so the load is directly connected to
the input line. The transition to this mode is set manually or automatically during overload or
fault
Fault: If any fault is detected, the UPS signals fault, and if it is possible, the bypass is
activated.
45 to 65 Hz Operating Frequency Range
120 V (at 25% of load) 280 V Operating Voltage Range for nominal mains 230 V
Input 85 V to 135 V Operating Voltage Range for nominal mains 110 V
Power factor at input > 0.95 at nominal voltage
Conversion efficiency > 85% at nominal output power
Number of output ports 6 in 2 segments
Output voltage selectable 110/120/200/220/230/240 V
Output power 725 750 VA at 230 V mains input voltage
Output Output power 325 350 VA at 110 V mains input voltage
Output waveform: true sine wave < 5% THD
Output frequency 50/60 Hz +/-0.3%
Output load regulation +/-2% (at steady state and linear load)
Battery 2*12 V
Battery
Battery 7.2 Ah
2x RS232 port for communication with host PC with opto-isolation implemented on
Communication
MC9S12E128 Controller Board
4 LED indicators (on-line, battery, bypass, fault)
Visual Interface battery level gauge 6 levels (<5/20/40/60/80/100%)
load level gauge 6 levels (20/40/60/80/100/>100%)
Control Interface 2x buttons for user control (on/off, bypass)
Fault
Overload
Audible warning
low battery
lasts 5 minute
Coding in C language according to ANSI C standard for software running on MCUs
Implementation
Coding in assembler if needed for software running on MCUs
System Description
Chapter 3
UPS Control
3.1 Control Techniques

Generally, a UPS consists of several different converters. So the control techniques differ with the
converter topologies used. The presented implementation of on-line UPS includes following topologies:
Battery charger: flyback converter (mixed control)
PFC: boost converter (mixed control)
dc/dc step up converter: push-pull converter (full digital control)
Output inverter: half bridge inverter (full digital control)
3.1.1 Battery Charger Control

The battery charger uses a flyback converter topology. As described in Chapter 4 Hardware Design, the
flyback converter is controlled by a dedicated circuit in order to reduce cost. The interface between the
flyback converter and the MCU incorporates one digital output, which allows the setting of two output
voltage levels, and an analog output, which sets the current limit.
Using a dedicated circuit greatly simplifies the control algorithm. The functionality of the converter itself is
ensured by the dedicated circuit. Therefore, the battery charger software focuses on the charging
algorithm, whose software block diagram is shown in Figure 3-1.
The algorithm reads the current flowing to the batteries. The current value is compared with the maximal
and float thresholds. If the value is close to the maximal value, the battery charger state is set to bulk
charging and the output voltage level is set to the higher value (PU7 set to logic 1). If the actual current
value is between the maximal and float thresholds, the battery charger is considered to be in the
absorption state. The output voltage is still kept at a high level. As soon as the current value reaches the
float threshold, the battery charger goes to the float state, and the output voltage is set to the lower level.
The current limit is set during initialization, according to the number of batteries and their capacity.
The control algorithm is called every 50 ms.
UPS Control
MC9S12E128
Output Voltage
PU7
Charging Current Limit

PWM10
yes
IBAT = Imax
no
Bulk mode
Set HV level
yes
IBAT > 0.05C
no
Absorption mode
Set HV level
Float mode
Set LV level
Battery Voltage
AN03
AN02 Battery current
Figure 3-1. Battery Charger Algorithm
Control Techniques
3.1.2 Power Factor Correction Control

The control algorithm of the PFC is depicted in Figure 3-2. The algorithm includes two control loops. The
inner control loop maintains a sinusoidal input current. The outer loop controls the dc bus voltage. The
result of the outer control loop is the desired amplitude of the input current.
MC9S12E128
PFC ENABLE
PU8
SIN REFERENCE
DA0
UREQ +
PI Controller
-
SINUS +
GENERATION
IOC04 Zero Cross

PLL LOCK
Top DC Overvoltage
FAULT1
Bottom Overvoltage
FAULT0
F AN07 Top DC Bus Voltage

I
L
T
AN08 Bottom DC Bus Voltage
E
R
Figure 3-2. PFC Control Algorithm

The current control loop is partially performed by an external circuit. This control technique is also called
indirect PFC control. The external circuit compares the actual input current with a sine wave reference.
If the actual current crosses the lower border of sine waveform, the PFC transistor is switched on. As soon
as the input current reaches the upper border, the PFC transistor is switched off. The resulting input
current can be seen in Figure 3-3. Maximal switching frequency (50 kHz) corresponds to the hysteresis
defined by resistors R664 and R675. (see Figure 4-20)
UPS Control
Hysteresis Sine
Levels Reference
Input current
Figure 3-3. Hysteresis Control of Input Current

The software part of the current loop generates the sine wave reference. The sine wave reference is
synchronized to be in phase with the input voltage. The sine wave generator is calculated every 50 s.
The sine waveform is generated directly by the D/A converter within the range of the voltage reference.
The voltage control loop is fully implemented by software. The sensed dc bus voltage is compared with
the required dc bus voltage, 390 V. The difference inputs to the PI controller. The PI controller output
directly defines the amplitude of the input current. The PI controller constants were experimentally tuned
to get an aperiodic responds to the input step. The constants are P = 100 and T I = 0.016 s. The voltage
control loop is calculated every 1 ms.
The two hardware faults are immediately able to disable the PWM outputs in case of a dc bus over
voltage. The digital output, PU8, enables/disables the external logic providing the current loop.
3.1.3 dc/dc Step-Up Converter Control

The dc/dc converter uses push-pull topology, which requires the PWM signals as shown in Figure 3-4.
These signals can be generated by one pair of PMF outputs with the following configuration:
even output is set to positive polarity
odd output is set to negative polarity
duty cycle of even output is set to X%
duty cycle of odd output is set to 100 - X%
where X is a value from 0 to 50% dead time
The required PWM patterns are shown in Figure 3-4.
PWM 4
PWM 3
Figure 3-4. Push-Pull Converter PWM Patterns
Control Techniques
The control algorithm is depicted in Figure 3-5. Both dc bus voltages pass the digital filter, and their sum
is compared with the required value of the dc bus voltage. Based on the error, the PI controller sets the
desired duty cycle of the switching transistors.
During mains line operation, the required value of the dc bus is set to 720 V (2 x 360 V). Because the dc
bus is kept by the PFC at 780 V (2 x 390 V), the dc/dc converter is automatically switched off. In case of
mains failure, the dc bus voltage will start to fall. As soon as the voltage reaches the value 720 V, the
dc/dc converter is activated. At 720 V, there is still 20 V reserve in amplitude to generate a maximum
output voltage of 240 V RMS. As soon as the operation from batteries is recognized, the required value
of the dc bus voltage is increased back to 780 V.
The PI controller maintains the constant voltage on the dc bus independent of the load until the mains is
restored or the battery is fully discharged. If the battery is discharged, the UPS output is deactivated and
UPS stays in STANDBY ON BATTERY mode. After 1 minute, the UPS is switched off.
The PI controller constants were experimentally tuned in the same way as the PFC. The constants are
P = 39 and TI = 0.0033 s. The control loop is calculated every 1 ms.
MC9S12E128
PMF3
Output Transistors
UREQ + PMF4
PI Controller
-
Top DC Overvoltage
FAULT1
Bottom DC Overvoltage
FAULT0
F AN07 Top DC Bus Voltage

+ I
L
T
AN08 Bottom DC Bus Voltage
+ E
R
Figure 3-5. dc/dc Step-Up Converter Control Algorithm
UPS Control
3.1.4 Output Inverter Control

The output inverter is implemented by two IGBT transistors in half bridge topology. The inverter is fully
digitally controlled and generates a pure sine wave voltage.
The sine waveform is generated using the pulse-width modulation technique. The sine reference is stored
in a look-up table. The table values are periodically taken from the table, and then multiplied by the
required amplitude. The resulting value gives the duty cycle of the PWM output. The pointer to the table
is incremented by a value, which corresponds to the desired output frequency. All values over one period
give sinusoidal modulated square wave output (see Figure 3-6). If such a signal passes through a LC
filter, the pure sine wave voltage is generated on the inverter output.
+DCBUS
-DCBUS
Figure 3-6. Sine Wave Modulation
The control algorithm can be seen in Figure 3-7. The main control loop comprises of the PID controller
and a feed forward control technique. The required value entering the PID controller is generated by a
sine wave generator, optionally synchronized with input voltage. The same value is added directly to the
output of the PID controller. It is called the feed forward technique, and it improves the responds of control
loop. The amplitude of the sine wave reference is corrected by RMS correction, which keeps the RMS
value of the output voltage independent of any load. The RMS correction uses the PI controller. The PI
constants were experimentally tuned, and set to P = 0 and TI = 0.00936.
The PID controller was tuned using simulation in MATLAB. The results of the simulation can be seen in
Figure 3-8 and Figure 3-9, with P = 0.6, TI = 0, TD = 0.00071 s, and N = 31. The value N represents the
filter level of D portion EQ 3-5.
The result of the PID controller, including feed forward, is scaled relative to actual dc bus voltage. Then
the exact duty cycle is set to the PMF module.
Control Techniques
Figure 3-7. Inverter Control Algorithm
Figure 3-8. Simulated PID Controller Response on Input Step
UPS Control
Figure 3-9. Quality Control of Non-Linear Load
3.1.5 PI and PID Controller

The PI controller in a continuous time domain is expressed by following equation:
1 t
u ( t ) = K e ( t ) + ----- e ( ) d (EQ 3-1)
TI 0
Similarly, the PID controller can be expressed as:

1 t d
u ( t ) = K e ( t ) + ----- e ( ) d + T D ----- e ( t ) (EQ 3-2)
TI 0 dt
In a Laplace domain it can be written as:
1
u ( s ) = K e ( s ) + -------- e ( s ) (EQ 3-3)
sT I
1
u ( s ) = K e ( s ) + -------- e ( s ) + sT D e ( s ) (EQ 3-4)
sT I
To improve the response of the PID controller to noisy signals, the derivative portion is often replaced by
a derivative portion with filter:
sT D
sTD ------------------- (EQ 3-5)
sT
1 + --------D-
N
For implementation of algorithms on MCU the equations EQ 3-3 and EQ 3-4 have to be expressed in
discrete time domain like:
u ( kh ) = P ( kh ) + I ( kh ) + D ( kh ) (EQ 3-6)
Control Techniques
where
P ( kh ) = K e ( kh ) (EQ 3-7)
Kh
I ( kh ) = I ( kh h ) + ------- e ( kh ) (EQ 3-8)
TI
TD KT D N
D ( kh ) = --------------------- D ( kh h ) --------------------- e ( kh h ) (EQ 3-9)
T D + Nh T D + Nh
e ( kh ) = w ( kh ) m ( kh ) (EQ 3-10)
and
e(kh) = Input error in step kh

w(kh) = Desired value in step kh
m(kh) = Measured value in step kh
u(k) = Controller output in step kh
P(kh) = Proportional output portion in step kh
I(kh) = Integral output portion in step kh
D(kh) = Derivative output portion in step kh
TI = Integral time constant
T, h = Sampling time
K = Controller gain
t = Time
s = Laplace variable
N = Filter constant
3.1.6 Phase-Locked Loop (PLL) Algorithm

The PLL algorithm provides synchronization with the mains line. This synchronization is necessary for the
PFC algorithm and can be optionally used for the inverter output.
The algorithm consists of two parts:
Frequency lock
Phase lock
UPS Control
The PLL algorithm measures a period from last two zero crossing signals. Because calculation of the
phase increment to the sine wave table requires a division instruction EQ 3-11, the phase over one-half
period is calculated instead:
T
Phase Increment = 32767 ----------------- (EQ 3-11)
Period
where
T = period of sine wave algorithm (50 s)

32767 = 180 in sine wave look up table
Period = measured period of main line voltage
If phase increment just corresponds to the measured period we should get a phase of 180. If there is
some difference, the phase increment must be adjusted (see Figure 3-10). Based on the sign of the phase
difference, the phase increment is incremented or decremented by the value which is equal to the phase
difference multiplied by the PLL constant.
If the phase difference falls below some limit for last 20 periods, the PLL is locked to the line frequency
and a frequency locked status bit is set.
Actual Period
Zerocrossing
Signal
Actual
Phase
0 180
Actual Phase
Increment Phase
Difference
Figure 3-10. Calculation of Phase Difference

Now the PLL is running with the same frequency as the mains line, but the phase is still different. As soon
as the frequency status bit is set, the actual phase is adjusted to 0 or 180 according to the previous
polarity of the input voltage. The polarity of the input voltage is sensed in the middle of each period.
Chapter 4
Hardware Design
4.1 System Configuration

The single phase on-line UPS reference design is 750 VA UPS representing an on-line topology. The
UPS comprises four PCBs (power stage, user interface, input filter, and controller board). The power
stage together with the MC9S12E128 controller board is shown in Figure 1-2
Figure 4-1. System Concept of UPS

The UPS reference design provides both a ready-to-use hardware and a ready-made software
development platform for an on-line UPS, under 1000 VA output power, and controlled by a single 16-bit
MCU.
The UPS power stage consists of several system blocks shown as:
Battery Charger
Auxiliary Power Supplies
Control Board Interface
dc/dc Step-Up Converter
PFC + Inverter
Hardware Design
J101
J104 J100 PSH02_02P
J102 J103
1
2
+VBAT
F101 /POWER_EN
POWER_EN
1 3
2 4
+15V_BOT
+15V_TOP
+15V_PFC
GND_BOT
GND_TOP
GND_PFC
+5V_REF
-5V_BOT
-5V_TOP
FUSE AUTO 40A
+5V_D
+5V_A
GNDA
+15V
GND
+VBAT
Battery Charger
L J105 L +VBAT
N +VBAT -VBAT
F102 +15V +15V_TOP
-VBAT
+5V_A +5V_A +5V_D
GNDA /POWER_ON +5V_A -5V_TOP
6.3A/fast GND_TOP
GND
+15V_BOT
GNDA GND GND
F100 HV_BAT_LEVEL -5V_BOT
GND_BOT
IBAT_CONTROL
+15V_PFC
2A/fast GNDA
VBAT
N J106 IBAT
+5V_REF GND_PFC
PFC+Inverter
+5V_REF
-5V_BOT
GND_BOT
+15V_BOT
GND
+5V_D
GND_PFC
+15V_PFC
GNDA
+5V_A
+15V
-5V_TOP
GND_TOP
+15V_TOP
L1
L2
N
PE MH100 PE
PE CONNECTION
PWM_TOP
PWM_BOT J107
GNDA J108
GNDA PWM10 FAN_PWM
GND PWM12
+5V_D
UNI-3 PFC_EN
GND +5V_D TIM14 RLY_IN OUT1
V_DCB_BOT
V_DCB_TOP
V_OUT_BOT
+5V_A
V_OUT_TOP
+5V_A TIM15 RLY_BYPASS OUT2 J109
DCB_NEG
+15V
DCB_POS
+15V TIM16 RLY_OUT1 N_OUT
PFC_ZC
FAULT0
FAULT1
TIM17 RLY_OUT2
I_OUT
TEMP
FAN+
V_IN
DIV1
DIV2
DA0
DA1
I_IN
J110
AD2 FAN-
AD3 1
2
AD1 PSH02_02P
AD4 UNI-3_PWM2 J111
AD5 UNI-3_PWM3
AD6 UNI-3_PWM4 1
UNI-3 PHAIS UNI-3_PWM5 2
UNI-3 PHCIS PSH02_02P
UNI-3 DCBI UNI-3 PFC_EN
UNI-3 DCBV UNI-3 SERIAL
UNI-3 BEMFZCA
UNI-3 BEMFZCC
UNI-3 BEMFZCB
UNI-3 PFC_ZC DC-DC Step Up
DA0
Fault1
Fault0
DA1 GND
GND GNDA
GNDA +VBAT DCB_POS
-VBAT +VBAT DCB_NEG
-VBAT
PWM4
PWM5
Figure 4-2. UPS Power Stage Block Schematic
4.2 Battery Charger
4.2.1 Operational Description

The battery charger is intended for charging the UPS batteries and supplying all UPS control circuits. The
battery charger provides a three-state charging algorithm fully controlled by the MCU. Its operating
parameters are listed in Table 4-1.
Battery Charger
Table 4-1. Battery Charger Parameters
Input voltage 80 to 280 V / 50 to 60 Hz
Output voltage
High voltage level 29.4 V
Low voltage level 27.4 V
Output current
Max. value 1.8 A
Absorption - float threshold 0.36 A
NOTE
The output values are set to the values recommended by the battery
manufacturer. The current limits can be set to any value by SW.
4.2.2 Battery Charger Topology

The battery charger uses a flyback topology, frequently used for its simplicity for output power below
100 W. The charger consists of a flyback converter, battery voltage and current sensing, current
limitation, and mains line voltage detection. The schematic of the battery charger is shown in
Figure 4-3.The flyback converter uses the dedicated circuit TOP249 for control, which incorporates a
MOSFET transistor and control circuit in one package. Using this dedicated circuit allows connection of
the control signals to the secondary side of the flyback converter without galvanic isolation. The second
advantage of the solution is that UPS power is independent of MCU control, and the UPS is able to run
without batteries.
TP300
D301 Vbat
D302 C302 BYW29E-200 29.4V @ Q4 ON
D303 T300 L300
B250R 220uF/450V P6KE200 27.4V @ Q4 OFF
1 13 +VBAT
47uH
+
C301 LINE_OK
R301
4.7nF 68k R302 R303
L
+
1M 9 24k
D304
R304
7 39k
-
1N4148 C303
6 5 R305
D305 R306 220uF/50V 1k8
TR02/MC145 100nF 220uF/50V
N BYV26C 1M R307
+ + 100u/50 +
620
C304 C305 C306

R309
2k4 5.05V @ 39V
VBAT
D
R310
R311 5K6
R312 C315
33k
D300 G 200 100n
1N4148 R300
L301 0.1 S
7 2 GND_TR
U300 -VBAT
47uH
L Q301
sense
sense
C
ISO300 GND_CH MMBF0201NLT1 GND
CONTROL
1 SFH615A-2
4 1
F X R329 IBAT1 IBAT2
R313
TOP249Y 27R 1K
4 5 3 GNDA
3 2 R314
HV_BAT_LEVEL
100
C316
R315 +
7.5k 100n C307 R308
47uF/10V 3K6
R331
100
R316 R317
220 33K +5V_A D309
100nF 5V1
C300
C309 C308
470nF GND_CH GND
8
1
R319 Q300 220n
1k6 MC33502 3
U301B + R318
IBAT1 6 - R320 1 BC847 8
7 2 - 100k
IBAT2 5 U301A U302
100K
+ 6
MC33502 TL431ACD
R321
4
1k6 R322
220 GND
C314 R323 R324
N/P GND_CH 1k 1k C312 D307
IBAT_CONTROL R327 R328
LINE_OK /POWER_ON
R325 R326
C311 560 68K
33K C310 10nF/100V BAV103 D
3k9
470nF 470nF C313
D308 R330
GND 10k G
BAV103
100nF/100V
4.875V @ 2.34A
IBAT GND Q302 S
MMBF0201NLT1
GND
GND_TR GND
Figure 4-3. Battery Charger Schematics

Battery Charger
4.2.3 Flyback Converter Operation

The flyback converter consists of the transformer T300, the MOSFET transistor U300 include control
circuit and the feedback circuit (R303, R305, R309, R312, Q301, ISO300, and U302).
When the MOSFET transistor (U300) is switched on, the magnetic field energy is accumulated in the
magnetic core of the transformer T300. During this time the output diodes (D301, D304) are reverse
biased. As soon as the transistor is switched off, the accumulated magnetic field energy is released
through the forward biased output diodes (D301, D304) to the output capacitors (C304, C305), and
through the output filter (L300, L301, C306) to the load.
The output voltage is sensed by the divider (R303, R305, R309, R312). The voltage from the divider is
compared with the internal reference of U302. The U302 creates the control signalthe current flowing
through the opto coupler (ISO300)which galvanically isolates the primary and secondary side of the
flyback converter.
The control signal is connected to the control pin of the control circuit (U300). According to the control
signal, the duty cycle of the MOSFET transistor (U300) is set. The MOSFET transistor is switched with a
fixed frequency of 66 kHz.
The resistor R312 can be shorted by the transistor Q301. This allows setting the output voltage to either
29.4 or 27.4 V by the MCU.
4.2.4 Design of Flyback Converter

The design of flyback converter using TOP249 is described in detail in [10], [11] and [12]. The following
input parameters were considered during the converter design:
Table 4-2. Input Design Parameters of Flyback Converter
Input voltage 80 to 280 V / 50 to 60 Hz
Max. output voltage 29.4 V
Max. output current 1.8 A
Switching frequency 66 kHz
The calculated parameters of the flyback transformer are specified in Table 4-3. The measured values on
the manufactured sample are listed in Table 4-4. To decrease leakage inductance, the interleaved
winding layout is used for the primary winding. The complete transformer winding layout is shown in
Figure 4-4.
Hardware Design
2.5kV insulation layer

L4 20T Cu f 4x0.315mm
L3 12T Cu f 3x0.56mm
L2 5T Cu f 2x0.315mm
L1 20T Cu f 4x0.315mm
14 8
L3
Core ETD29/16/10 N87 B66358-G-X187 1pcs
ETD29/16/10 N87 B66358-G500-X187 1pcs
Coil former B66359-J1014-T1 1pcs
Yoke B66359-A2000 2pcs L1 L4 L2
(EPCOS components)
1 7
Figure 4-4. Battery Charger Transformer Winding Layout
Table 4-3. Required Parameters of Flyback Transformer
Magnetizing inductance referred to the primary 328 mH + 3 0 20%
Magnetizing inductance referred to the secondary 31H + 30 20%
Total leakage inductance referred to the primary <3.5 H
Primary dc resistance <0.1
Secondary dc resistance <0.001
Test Voltage primary-to-secondary 2.5k V ac
Table 4-4. Measured Values on the Sample
L [H] L [H] ESR [Ohm] L [H] @100kHz, 1V

Pin # DCR [Ohm]
@1kHz, 1V @100kHz, 1V @100kHz, 1V pin # 9 and 13 shorted
1-6 331.2 330.5 2.142 0.095 2.88
5-7 5.2 5.22 0.061 0.018 -
9-13 29.8 29.74 0.194 0.0005 -
Battery Charger
4.2.5 Voltage and Current Sensing, Current Limitation

The battery voltage is sensed by the divider (R304, R307, and R310). The divider scales the maximum
measurable battery voltage of 39 V to the A/D converter range of 5 V. The battery current is sensed as
the voltage drops on resistor R300. The voltage drop is amplified by U301B to get 5 V at 2.4 A.
The current limitation is provided by U301A. The U301A compares the actual battery current with the limit,
which is set by the MCU. The MCU generates a PWM signal, which is filtered to the analog value.
4.2.6 Main Line Detection

The mains line detection ensures that the UPS is internally switched on (STANDBY ON LINE state) if the
mains line is available. The detection circuit detects the functionality of the flyback converter, and if the
mains line is detected, the power supplies are switched on. The detection circuit consists of rectified
diodes D307, D308, and transistor Q302.
4.2.7 Battery Charger Algorithm

There are many algorithms (constant voltage, constant current, two stage, three stage, etc.), that can be
used for charging lead acid batteries. The algorithms differ by the complexity of battery charger
implementation and by influence on the battery life.
Because the battery charger is controlled by the MCU, any battery charger algorithm can be implemented.
The UPS reference design uses the three stage charging algorithm (see Figure 4-5).
Figure 4-5. 3-Stage Charging Algorithm
Hardware Design
As the name of algorithm suggests, charging consists of three stages. The charging starts with the current
limit 0.25 of battery capacity. The battery charger works in current mode until the battery voltage reaches
the high level voltage (2.45 V/cell). This stage is called bulk charging. As soon as the battery voltage
reaches the high level, the current starts to fall, and the absorption stage begins. Once the battery current
falls under 0.05 of battery capacity, the battery charge voltage is set to the low level (2.28 V/cell). The last
stage is called the float stage.
NOTE
The voltage levels and current thresholds come from the battery
manufacturer. The values may also vary with the temperature if
temperature measurement is implemented.
4.3 Auxiliary Power Supplies

Signal circuits, control circuits, digital circuits, and driving circuits are supplied by auxiliary SMPSs
(Figure 4-6). Since the drive circuits have to be galvanically isolated from each other, a small isolated
flyback converter (Figure 4-7) is used to generate separate voltage sources for all power semiconductor
drivers.
+VBAT U202
LM2575-5
TP204 +5V_D
R212 4
1 +5V_D
33k
L202
2
470uH
1
/POWER_EN
R200
3
D210 + 510
+ 1N5819
C215
2
D C216 220uF/10V
22uF/50V D211
KA3528LSGT
R213 G
POWER_EN
100
Q200 S
MMBF0201NLT1
GND GND GND GND GND GND
U200
LM2575-15
TP200 +15V
4
1 +15V
L203
2
1
680uH
1
R214
R215 2.4k
3
D213 20K
+ 1N5819
2
+
12
C218
22uF/50V R216 C217 D214
1.8K 220uF/10V KA3528LSGT
2
GND GND GND GND GND

GND
TP207 TP208
U203 +5V_A Vref
L205 MC78L05ACP +5V_A L200 +5V_REF
+15V 3 VIN VO 1
10uH 10uH
+
GND
+ C221 C200
100nF C220
C219 100nF 22u/20V
22u/20V
2
GNDA GNDA GNDA
Figure 4-6. Auxiliary SMPSs
Supply voltages for the microcontroller and other digital circuits (+5V_D) are generated by U202. U200 is
used to stabilize +15V for the flyback converter, relays, dc/dc MOSFETs drivers, and cooling fans and it
is used as a down-converter for U203 in order to lower the power loss dissipated by U203. The IC supplies
5 V for op amps, comparators, and the heatsink temperature sensor. The output voltage is further filtered
and used as a reference for the signal and control circuits. In order to switch-on and switch-off all the
control and signal circuits, U200 and U202 are controllable by POWER_EN and /POWER_EN signals.
POWER_EN signal is driven by the microcontroller to control the switch-off process. /POWER_EN signal
is grounded when the ON button is depressed. All the power supplies are put into an operational state,
the micro starts to execute the program, and the POWER_EN signal is then put into the active state to
hold the supplies operational even when the button is released.
Figure 4-7 shows the isolated flyback converter schematic that provides the inverter and PFC drivers with
a power supply. MOSFET Q201 is driven by UC3843 in a classic current-mode configuration without the
feedback loop. The supply is designed to deliver constant power to the output while access power is
dissipated in zener diodes D202-D203, D206-D207, and D209 in case of drivers-in-standby. Respective
zener diodes are used specifically to split the secondary voltage to 5-V and 15-V levels.
C201
R201 TP201
+15V_TOP
220
T1 100pF D201 +15V_TOP
12
LL4448 TP209
D202 GND_TOP
+ C202
8z. 220uF/25V BZV55/15V
+15V 1 11
C204 8 +
D203 GND_TOP TP210
C203 -5V_TOP
L201 BZV55/5V1
47nF 100uF/10V
330u 5z. 8z.
7
R202 GND -5V_TOP
2
D204 6 C205
R203 15k R205 TP202
R204 +15V_BOT
U201 D D1
15k
1 8 MMBD914LT1
220 6z. 100pF D205
220
+15V_BOT
R206 COMP VREF
8.2k 2 VFB VCC 7 R207 5
1
3 6 G
ISENSE OUT Q201 TP211
+ C206 4 5 33 LL4448 D206
RT/CT GND S NTF3055 C208 TR01/MC145 + C207 GND_BOT
330uF BZV55/15V
UC3843 220uF/25V
R209
2
R208 C209 100pF

8.2k 1k
100nF + C210 GND_BOT TP212
C211 R210 D207
C212 100uF/10V -5V_BOT
100pF 1.8 BZV55/5V1
100pF
GND GND GND GND GND GND GND LL4448 -5V_BOT

C213
R211 TP203
220 +15V_PFC
100pF D208 +15V_PFC
+ TP213
C214 D209
GND_PFC
220uF/25V BZV55/15V
GND_PFC GND_PFC
Figure 4-7. Isolated Flyback Converter for Drivers

4.3.1 Auxiliary SMPS Design Considerations

Auxiliary SMPS design (Figure 4-6) follows producer general considerations for LM2575 and 78L05
switched and linear regulators.
Because the isolated flyback converter is based on a standard UC384X IC, the design is focused on
transformer design. The transformer is used as an energy reservoir. During the switch-on the energy is
accumulated, and during the switch off the energy is delivered to the output capacitor and the load.
Respective output voltages are 2 x 20-V for HCPL315J output inverter driver - generated by L2 and L3
(+15 and 5 V are good driving margins in 800-V application), and 15-V for HCPL3150 PFC driver -
generated by L4 (single supply 15 V is sufficient for 400-V application). First, the output power is defined.
When driver circuits with HCPL315J and HCPL3150 drivers are considered, a value of 1.2 W is obtained.
When efficiency is considered, a value of 2 W is obtained. For such power, a switching frequency 300 kHz
is chosen. Lets consider a 0.5 maximum duty. It means that during half of the switching period, all energy
for the whole cycle must be accumulated in the transformer.
The average necessary input charge is given by EQ 4-1. When we consider the triangular shape of the
transformer primary current, we get EQ 4-2 for the charge taken by the transformer.
P IN
Q = I AV T = --------- T (EQ 4-1)
V IN
t ON I P
Q = i dt = ----------------
- (EQ 4-2)
2
Because the voltage is equal, the equality of these charges also provides equal energies. When we
compare both equations, we get
P IN t ON I 1P
- T = -------------------
-------- (EQ 4-3)
V IN 2
Rearranging EQ 4-3 we get EQ 4-4 for the peak primary current:

P IN T 2 3.3
I PP = 2 --------- -------- = 2 ------ ----------- = 586mA (EQ 4-4)
V IN t O N 15 1.5
The peak secondary current for a 20-V output is calculated using EQ 4-6 (all the output power is
considered), and the secondary winding inductance L2 is then given by EQ 4-7.
V IN 15
L 1 = --------- dt = ------------- 1.5 = 38H (EQ 4-5)
di 0.586
P OUT T 1.6 3.3

I 1P = 2 ------------- ---------- = 2 ------- ----------- = 293mA (EQ 4-6)
V OU T t O FF 20 1.8
V OU T 20
L 2 = ------------- dt = ------------- 1.8 = 123H (EQ 4-7)
di 0.293
Hardware Design
Lets choose a RM8 core made from N97 ferrite material, with Ae = 64mm 2 and AL = 3300 nH. Respective
winding turns are as follows:
L 38
N1 = ------P- = --------------- = 3.4 4t (EQ 4-8)
AL 3300n
L 123
N2 = ------S- = --------------- = 6.1 6t (EQ 4-9)
AL 3300n
Therefore, N1 primary to N2 secondary ratio is given as follows:

N 4
p = ------1 = --- = 0.667 (EQ 4-10)
N2 6
For supplying the PFC driver, 15-V supply voltage is necessary and the turns ratio between both
secondaries is used to calculate the number of turns for the PFC driver.
15 15
N 4 = ------ N 2 = ------ 6 = 4.5t (EQ 4-11)
20 20
Rounding the number up or down would cause large unbalanced secondary voltages. Secondary turns
are then scaled to obtain appropriate secondary-to-secondary ratio. Afterwards, primary turns are also
altered. In this case, N2 = 8t gives exact value of N 4 = 6t as follows:
15 15
N 4 = ------ N 2 = ------ 8 = 6t (EQ 4-12)
20 20
Now, the primary turns are scaled to maintain primary-to-secondary ratio:

N 1 = p N 2 = 0.667 8 = 5.34 5t (EQ 4-13)
To maintain a discontinued conduction mode, the switching frequency has to be also altered to the value
of 200 kHz. And the maximum flux has to be checked - simulation shows flux of amplitude 160 mT.
Figure 4-8 shows the layout of the windings on the transformer bobbin.

L4 6T Cu f 0.25mm 12 7

L3 8T Cu f 0.25mm L3 L2
L1 L4
L2 8T Cu f 0.25mm
L1
1 6
5T Cu f 0.25mm
Core RM8 N97 B65811-J-R97 1set

Coil former B65812-C1512-T1 1pcs
Clamp B65812-A2203 2pcs
(EPCOS components)
Figure 4-8. Flyback Power Transformer Layout of Windings
4.4 dc/dc Step-Up Converter
4.4.1 dc/dc Converter Operational Description

A dc/dc converter is intended for dc bus supply when the UPS run from batteries. Parameter
specifications are listed in Table 4-5. The converter transforms the battery voltage of 24 V to a dc bus
voltage of +400 V, 400 V. Low-cost considerations led to push-pull topology as shown in Figure 4-9. The
circuit consists of a push-pull inverter (Q500-Q503), power transformer T500, bridge rectifier (D500,
D502, D504, D505) and filter L501, L502. The rectifier directly supplies the dc bus voltage +400,400V.
Table 4-5. dc/dc Converter Specifications
Parameter Value
Input voltage nominal 24 V
Input voltage minimal 21 V
Input voltage maximal 30 V
Output voltage nominal +390 V -390 V
Output voltage minimal +350 V -350 V
Output power nominal 580 W
Output current nominal 0.74 A
Input current nominal 27 A
L501
-OUT
DCB_NEG
650u/1A
D501
680u/50V 680u/50V 680u/50V +Bat 1 2 C501
+VBAT 22n/400V
MUR180
R501
1
C502 + C503 + C504 + C505 + C512 + C513 + 1k/5W
1 2
R502
2
2
FFPF05U120STU 1k/5W
-VBAT FFPF05U120STU 1 2
680u/50V 680u/50V 680u/50V D500 D502
GND_BAT MUR180
1 2 C506
22n/400V
D504 D505 D503 L502
+OUT
DCB_POS
650u/1A
FFPF05U120STU GND FFPF05U120STU
+15V +15V
13
15
10 18
T500
TR03/MC145
L503 1 9 L500
330u 330u
R503
4
6
100R/1W
1 2
100R/1W
1
47uF R504 47uF
C509 C508 C510
2 1 1n
1 2 1 2
+
+
GND_BAT GND_BAT
2
2
100n C507 GND_BAT 100n

C511 1n C500
1
GND_BAT GND_BAT
GND_BAT
Q501 Q500 Q502 Q503
NTP45N06 NTP45N06 NTP45N06 NTP45N06
6
6
U500 MC33152D U501 MC33152D
1 NC VCC NC 8 D D D D 8 NC VCC NC 1
TP501
PWM_4 TP502
R505 R500
2 InA OutA 7 1 2 G G G G1 2 7 OutA InA 2 PWM_5
10 10
PWM4 S S S S
R506 R507 PWM5
1
1
4 InB OutB 5 1 2 1 2 5 OutB InB 4
R508 R509
10 10
10k 10k
GND GND
2
2
GND_BAT
GND_BAT GND_BAT
GND_BAT GND_BAT
Figure 4-9. dc/dc Converter Schematic

The converter performance and features are analyzed by simulation with the model shown in Figure 4-10.
Chokes and Rectifier Snubbers

Rectifier Model DC Bus
mur2100e/ON mur2100e/ON L16 R8

1 2
560u 0.3 2
C5 10p
Power Transformer Model D1 C4 D2 L13
10p R18
20n
D7 R21
4700 2 4700 2
L7 R3
R20 L9 L10 1
1 2 1000
2 mur2100e/ON R5
10u 0.5 20n 20n C9 R22 C7
L5 10p 50m
9.98m 1 1 2k V4
K K1 22n R28
K_Linear 390 524meg
COUPLING = 1
1
0
1 2 1 2 2
2 1 390
30.8u 30.8u
2 L6 R29
L3 L1 L2 L4 2 2 R23 C8 V5 524meg
L15 9.98m
26.7n 26.7n L11 L12
15n 2k
L8 R4 C10 22n R6
1 20n 20n 10p
1 2 50m
1 2 D8 R19
1 1 2 10u 0.5 2
R16 R17
L21 L18 1 1 L14
1000
2n 2n 4700 4700 20n
mur2100e/ON
Inverter Model 2u V1 2u D3 C6 D4
23.2 C3 10p L17 R9
2 1 1
1 2
560u 0.3
R1 R2 10p mur2100e/ON mur2100e/ON
5m R14 R7 R15 5m
20m
100 100
Implementation = 1 R10 M1 M3 C1 C2 M2 M4 R12 Implementation = 2
Current Sensing
1n 1n
20
V2 20 V3
S S K K2 D1N4149
R11 NTP45N06 NTP45N06 NTP45N06 NTP45N06 R13 D12
K_Linear
COUPLING = 1
0 20 20 0
L20 R25 R27
1 2 D6
0 1 1.6m 3 220
D1N4149
L19 C11 D9
5p R24
80u D1N4149 22
80m R26 C12
1k
2 10n
D10
D1N4149
D11 0
D1N4149
Figure 4-10. dc/dc Converter Simulation Model Schematic

Hardware Design
The inverter is supplied by a set of a low-ESR capacitors, C502-C505 and C512-C513, to lower the
battery bus ripple current and hence the EMI signature of the converter input. Inverter MOSFETs
Q500-Q503 are driven by MC33152 drivers. MOSFETs drain voltage ringing is damped by RC cells
R504-C507 and R503-C508. Because of the voltage source character of the inverter, the rectifier has to
be a current type, which is why smoothing chokes L501 and L502 are used. Over voltage spikes across
the rectifier diodes, due to the diodes reverse-recovery and transformer leakage, are clamped by RCD
snubbers consisting of a R501- C501- D501 for the positive side, and R502 - C506 - D503 for the negative
side.
4.4.2 dc/dc Converter Design Considerations
4.4.2.1 Power Transformer

The first task in power transformer design is to choose an appropriate transformer core. Based on
manufacturer power-handling-capability core tables the core size is selected. Subsequently, the
maximum core flux density travel B must be determined from the core manufacturer data sheet, and then
an approximate number of turns can be calculated. Since the number of turns is usually an integer, the
number is rounded and the real flux density travel is calculated. If B is below a maximum limit with
respect to the switching frequency (core material dependent), winding turns and the cross-sectional areas
are calculated for all respective windings.
For 580W output, an ETD44 core is selected. Now, the integral of the Faraday induction law EQ 4-14
gives the relation for the magnetic charge put into the core EQ 4-15:
d d dB
u i = ------- = N ------ = N S ------- (EQ 4-14)
dt dt dt
where
ui = induced voltage
= linkage flux in the core
N = number of turns
= flux in the core
= flux density in the core
u i dt = N S B (EQ 4-15)

where
= flux density travel

S = core cross-sectional area
Initially, the magnetic charge has to be calculated. Since the induced voltage during an active part of the
converter operational cycle is constant and it equals the input voltage, the magnetic charge in the core is
given by EQ 4-16.

u i dt = V IN T (EQ 4-16)
where
VIN = input voltage

= switching duty cycle
T = switching period (f = 50kHz)
6
u i dt = 24 0.45 20 10 = 216 Vs (EQ 4-17)

Simulation results can also be used to obtain the magnetic charge. Figure 4-11 shows simulated
magnetizing voltage and magnetic charge. Magnetic charge is obtained by the time integral of the
magnetizing voltage. Peak-to-peak reading of the magnetic charge is 218 V.
Rearranging EQ 4-15, the number of primary turns can be calculated:
u dt 6
i 216 10
N1 = --------------- = ----------------------------------
- = 3.12 t (EQ 4-18)
S B 173 106 0.4
40V 100u
1 2
20V 0
0V -100u
-20V -200u
>>
-40V -300u
15us 20us 25us 30us 35us 40us 45us
1 V(L1:1,L1:2) 2 S(V(L1:1,L1:2))
Time
Figure 4-11. Simulated Magnetizing Voltage and Magnetic Charge
Hardware Design
Lets choose 3 turns. However, the flux density travel B has to be checked:
u dt 6
i 216 10
B = -------------- = -----------------------------
- = 416 mT (EQ 4-19)
S N 1 173 106 3
From EPCOS Siferit N97 specification (FAL0625-W @60C), the core power loss is 10 W, indicating a
good core utilization. However, forced convection should be considered. The negative loss temperature
coefficient of the N97 material is advantageous since it contributes to a temperature stability of the core
(FAL0624-N).
Now, the number of turns of the secondaries can be calculated. For primary to secondary ratio and a
forward type of converter, equation EQ 4-20 is valid:
V OU T
p = ----------------------------------
- (EQ 4-20)
V IN MA X
For efficiency = 0.93 and maximum duty (MAX) = 0.98, EQ 4-20 yields
V OUT 350
p = ----------------------------------- = ------------------------------------ = 18.47 (EQ 4-21)
V IN MAX 21 0.93 0.97
Primary to secondary ratio is rounded to 18, and the secondary winding number of turns yields
N 2 = p N 1 = 18 3 = 54t (EQ 4-22)
Once the winding turns are determined, the cross sectional area of a winding can be calculated. For the
ETD44 core, winding current density can be selected in the range 5-10A/mm 2. Let J = 8A/mm2. Primary
cross-sectional area is given by EQ 4-23
I 19.1 2
S 1 = ----1 = ---------- = 2.39 mm (EQ 4-23)
J 8
where
1 = nominal primary winding current obtained by integrating the square of the simulated
winding current (Figure 4-12).
60A 915m
1 2
40A 910m
20A 905m
0A 900m
>>
-20A 895m
2.2965ms 2.3000ms 2.3040ms 2.3080ms 2.3120ms 2.3160ms 2.3200ms 2.3240ms 2.3280ms
1 -I(R1) 2 S(I(R1)*I(R1))
Time
Figure 4-12. Simulated Primary Winding Current

Secondary cross-sectional area is given by EQ 4-24:
I 0.74 2
S 2 = ---2- = ---------- = 0.093 mm (EQ 4-24)
J 8
where
2 = nominal secondary winding current obtained by integrating the square of the simulated
winding current (Figure 4-13).
Hardware Design
1.5A 1.300m
1 2
1.0A 1.296m
0.5A 1.292m
-0.0A 1.288m
-0.5A 1.284m
-1.0A 1.280m
>>
-1.5A 1.276m
1 -I(R3) 2 S(I(R3)*I(R3))
Time
Figure 4-13. Simulated Secondary Winding Current

For a 50kHz switching frequency the skin effect depth is given by EQ 4-25:
0.066 0.066
= ------------- = --------------------- = 295 m (EQ 4-25)
f 3
50 10
In this case the best solution for the primary is the use of a copper foil. An ETD44 bobbin has a width of
30 mm. Because of the necessary creepage, the foil width is set to 25 mm. Based on the result of
EQ 4-23, the foil thickness yields 100 m and has excellent skin performance when compared with skin
depth at the current switching frequency.
From the result of EQ 4-24, the secondary winding wire diameter yields 0.338 mm. The nearest wire
diameter in production is 0.315mm. A wire with a larger diameter is not helpful any more because of the
increased ac resistance due to the skin effect.
The primary winding of the push-pull converter transformer uses a center-tapped windings as well as the
secondary windings. As the power transformer is a part of the push-pull converter, there are some
restrictions required, especially with respect to the leakage inductance. With inverter transistor turn-off,
the drain voltage in push-pull is not clamped by the circuit topology itself. For ideal case (zero leakage),
the drain voltage is clamped through the transformer coupling when the rectifier diodes are re-opened.
60V
40V
20V
0V
9.458us 9.600us 9.800us 10.000us 10.200us 10.400us 10.600us 10.800us

V(M1:d) V(M2:d) V(M3:g) V(M2:g)
Time
Figure 4-14. Simulated Drain-to-Source and Gate-to-Source MOSFETs Voltages

However, when leakage is non-zero, coupling between the primary and the secondary is not so close and
the transformer acts more than an inductive load. As a result, inverter transistors receive voltage spikes
and ringing at the drain voltage, usually leading to the use of MOSFETs with a higher break-down drain
voltage (Figure 4-14). Due to the necessity to decrease the leakage inductance, an interleaved winding
layout has to be used, as seen in Figure 4-15.
Hardware Design

L6 29T Cu f 0.315mm
L5 29T Cu f 0.315mm
L4 3T Cu stripe 25x0.15mm
500V insulation layer
L3 3T Cu stripe 25x0.15mm
L2 29T Cu f 0.315mm
L1 29T Cu f 0.315mm
18 10
Core ETD44/22/15 N97 B66365-G-X197 2pcs

Coil former B66366-B1018-T1 1pcs L6 L2 L1 L5
Yoke B66366-A2000 2pcs
L4 L3
(EPCOS components)
1 9
Figure 4-15. dc/dc Power Transformer Layout of Windings

The transformer specification is presented by Table 4-6. The magnetizing inductance values are obtained
from the manufacturer. The AL constant, total leakage, is obtained initially from numeric parametric
simulation results, and afterwards is verified experimentally on the sample. Resistance values are
measured values. Test voltages come from general standards defined for the inductive components used
in SMPS. Measurements on the sample show that it is possible to achieve a relative leakage less than
0.6%.
Table 4-6. dc/dc Transformer Specification
Magnetizing inductance referred to the secondary 2.5mH+30-20%

Magnetizing inductance referred to the primary 30H+30-20%
Total leakage inductance referred to the secondary <20uH
Primary DC resistance <1mOhm
Secondary DC resistance <0.6Ohm
Test Voltage secondary-to-secondary and primary-to-secondary 2kV AC
Test Voltage primary-to-primary 150V AC
4.4.2.2 Inverter MOSFETs

As mentioned above, MOSFETs voltage rating is given by voltage spikes that can possibly occur during
MOSFET switch-off. Of course it depends on the input voltage, load conditions, and transformer
properties. For push-pull a number of twice the input voltage is usually sufficient. The current rating of the
MOSFETs (chip size) is always a compromise because a small chip has large RDS(ON) that causes high
conduction losses. On the other hand, a large chip has low RDS(ON), but the chip capacitances are higher,
and, in the case of hard-switched topologies, the energy stored in the capacitances is not recovered in
the switching process, but instead, energy is dissipated in the chip. This is especially the case in
applications where the supply voltage is greater than 200 V.
The primary factor for chip selection are the effective drain current and the switching frequency. Then a
suitable device is selected. Power loss components are calculated and compared with the designed
maximum power loss per package.
Simulation results (Figure 4-12) show a value of 19.1 A (transistor and primary winding currents are the
same). Dynamically, a current level as high as 50 to 60 A is observed when a load transient occurs and
the regulator attempts to hold the output voltage level. Of course the transistor has to withstand such
conditions for a number of milliseconds.
A couple of ON Semis twin NTP45N06 could be a solution. RDS(ON) for the transistor is 26 m. If a single
NTP45N06 switches the current with an effective value of 19.1 A, conduction losses are as high as 9.5 W.
To lower the conduction losses and to ensure the transistor switching robustness in dynamic conditions,
lets consider the twin NTP45N06 which decrease overall conduction losses to the half (power loss per
package decreases to a quarter - 2.4 W). However, the switching and the capacitance losses have to be
considered, due to the increased overall chip area, and hence the overall chip capacitance.
Switching losses are given by EQ 4-26 (ref. [2]).
I SW
P SW = V D S ( Q G D + Q GS2 ) f SW -------- (EQ 4-26)
IG
3 30
P SW = 24 ( 3nC + 15nC ) 50 10 ------
- = 0.72 W (EQ 4-27)
0.9
where
VDS = drain-to-source voltage at the switching instance

QGD = miller part of the gate charge
QGS2 = post-threshold voltage gate charge
fSW = switching frequency
ISW = drain current at the instant of switch off
IG = available mean driver current
Note that VDS can reach a level close to 60V as depending on the particular duty cycle, input voltage, and
output load conditions. The same is true for ISW parameter, and the loss value can be impacted.
CAUTION
If the output load conditions or large transformer leakage cause over
voltage spikes at the drain and the maximum drain voltage is reached, the
voltage is clamped by MOSFET internal avalanche process (see
Figure 4-14 fourth wave oscillation on green waveform). If the energy of
the spikes is high enough, chip temperature will exceed the maximum limit
and the semiconductor structure is destroyed. Please always observe the
drain-to-source voltage when testing the prototype. If this is the case,
increase the MOSFET voltage class or redesign the power transformer in
order to decrease the leakage.
Hardware Design
Turn-on capacitance losses PCAP for the NTP45N06 are given by EQ 4-28.
1 2
P CAP = f SW W CAP = f SW --- C OSS ( EFF ) V D S (EQ 4-28)
2
3 1 12 2
P CAP = 50 10 --- 380 10 60 = 34 mW (EQ 4-29)
2
where
fSW = switching frequency

WCAP = capacitance energy (see ref. [1])
COSS(EFF) = effective output capacity of the MOSFET (see ref. [2])
The sum of the switching and the capacitance losses is less than 0.8W per transistor at nominal
conditions, resulting in 1.6 W for the single NTP45N06 solution and 3.2W for the twin solution. When all
the loss contributions are compared, prevalence of the conduction losses is clear. The twin NTP45N06
solution results in an overall loss of 3.2W per package (the conduction component is 2.4 W, the switching
component 0.8W). Therefore, the twin solution doesnt contribute significantly to lower a converter
efficiency. Power loss 3.2 W per package means moderate package utilization for TO220, with a good
power loss margin.
The power losses can also be calculated by simulation of the model. Figure 4-16 shows the MOSFET
instantaneous power and energy obtained by instantaneous power integration. The average power is
then calculated by the definition of the power - the energy loss referred to the switching period.
400W 8.04m
1 2
200W 8.00m
0W 7.96m
>>
-200W 7.92m
2.208ms 2.212ms 2.216ms 2.220ms 2.224ms 2.228ms 2.232ms
1 W(M3) 2 S(W(M3))
Time
Figure 4-16. Inverter MOSFET Power Analysis
The use of a single transistor with a higher rated drain current is also possible, however, the copper lead
utilization is rather high even though manufacturers define the value around 75 A as a limit for TO220
package leads.
4.4.2.3 Rectifier Diodes

Rated diode voltage is given by the voltage waveform applied to the diode. However, diode voltage
waveforms are different from that of the MOSFETs since the rectifier diodes are placed in a different
topology. As the rectifier is current-loaded there is no natural clamp for over voltage spikes at the instant
of a diode reverse recovery. That is why a suitable snubber has to be implemented in order to cut-off the
excess energy that could possibly overheat the diode chip by internal avalanche.
As dc/dc converter nominal output voltage is 2x390V (Figure 4-18 shows secondary voltage of the power
transformer), and during dynamic conditions it can reach 2 x 420 V, the possibility of selecting the diode
voltage rating is constrained. Figure 4-17 shows waveforms of the rectifier diode voltage and current. In
this case, diodes with a break-down voltage of 1200V are selected.
0.5KV 1.5A
1 2
1.0A
0V
0.5A
-0.5KV
0A
>>
-1.0KV -0.5A
2.3075ms 2.3100ms 2.3150ms 2.3200ms 2.3250ms 2.3300ms
1 V(D1:1,D1:2) 2 I(D1)
Time
Figure 4-17. Rectifier Diode Voltage and Current Waveform

When choosing the rectifier current rating, similarly as with the MOSFETs, the anode effective current and
switching frequency have to be considered. Simulation results for the nominal anode effective current
shows a value of 0.54 A and a 1.3 W power loss. Because the power loss is rather high for a practical
usage of the DO241 package, diodes with a fully-isolated TO220 package are chosen. One possibility is
to use of the Fairchild ultrafast diode FFPF05U120S with 5-A rated current, 1200 V rated voltage, and
100ns reverse recovery time, which is good enough for 50 kHz switching frequency.
Hardware Design
4.4.2.4 Filter Chokes

A basic design consideration when implementing a filter choke is to look at the rectified current ripple. For
an output current level in the range of 0.5 to 2 A, the relative ripple ri can be considered in the range of
50 to 20%. Let ri equal 30% for nominal conditions. Then the filter choke inductance value is given by
EQ 4-30:
T M AX T
L = V L ------- = [ ( V IN V LOSS ) p V OU T ] --------------------- (EQ 4-30)
i r i I OUT
6
0.98 10 10
L = [ ( 24 1.6 ) 18 390 ] ----------------------------------- = 583 H (EQ 4-31)
0.3 0.74
where
VL = voltage across the choke when active cycle

= the time during active cycle
i = current ripple
VIN = nominal input voltage
VLOSS = voltage drop on resistive components (RDS(ON), transformer primary, etc.)
p = transformer primary to secondary ratio
VOUT = nominal output voltage
MAX = maximal switching duty cycle
ri = relative current ripple
IOUT = nominal output current
Filter choke performance is analyzed by simulation, and the results (Figure 4-18) verified a good design
procedure. Choke PCV2-564-02 from Coilcraft, with 560 H inductance and 2 A saturation current, is
chosen.
Power Factor Correction and Output Inverter
800mA 1.0KV
1 2
400mA 0.5KV
0A 0V
-400mA -0.5KV
>>
-800mA -1.0KV
1 I(L16) I(L17) 2 V(R3:2,R4:2)
Time
Figure 4-18. Secondary Voltage and Rectified Current Waveforms
4.5 Power Factor Correction and Output Inverter
4.5.1 PFC Booster Operational Description

This section deals with a design of the power factor correction booster (PFC). The PFC forms the input
stage of the UPS. It is a switchmode power converter, which provides an a.c. input current waveform that
is sinusoidal and in phase with the line voltage. The power factor is maintained so as to be close to one.
The continuous current - boost converter topology was chosen for the PFC circuitry design, as shown in
Figure 4-19. The PFC specifications are listed in Table 4-7. A power circuit consists of a current sensing
transformer CT1, input inductor L505, rectifying bridge D606, power switch Q606, voltage doubler diodes
D604, D608, and filtering capacitors C603, C602, C607, and C608. The PFC control algorithm
implemented uses an indirect digital control approach. To decrease MCU load the input current controller
is built externally.
Table 4-7. Digital PFC Specifications
Parameter Value Unit
Input Voltage Min. 80 V[r.m.s.]
Input Voltage Max. 270 V[r.m.s.]
Output d.c. Voltage 390 V
Output Power Nominal 525 W
Input Current Nominal 2.3 A[r.m.s]
Switching frequency 30 to 60 kHz
Hardware Design
I_IN1 I_IN2
7
CT1
1:100
L505
D604
L1 DCB_POS
2
2.5mH
RHRP8120
D606
KBPC606
- +
C602
C603 +
Q606 MKP10/22nF/630VDC
IRG4IBC20W 330uF/450V
GATE_PFC
GND_PFC
N N
GND
C607
+ C608
MKP10/22nF/630VDC 330uF/450V
D608
DCB_NEG
RHRP8120
Figure 4-19. PFC Power Stage

The output voltage level is controlled using a digital controller algorithm executed by the MCU. The MCU
generates a sinusoidal reference waveform for the discrete current controller. The current controller circuit
can be seen in Figure 4-20. The controller performs hysteretic current control. Comparators U606A and
U606C compare the actual input current value I_IN with the upper and the low limits set by the DA1 and
DA0 signals, respectively. Comparator U606B turns on and off power switch Q606 according to the
U606A and U606C outputs. The UPS input current corresponds to the shape of the reference signals DA0
and DA1 generated by the MCU. The PFC operation is disabled if the PFC_EN signal is tied low by MCU
control.
Alternatively (if signal DA0 is not available), the low hysteresis limit can be adjusted by the configurable
voltage divider. The resulting hysteresis is then defined by the combination of resistors R664, R673,
R674, and R675. The voltage divider can be configured according to the DIV1 and DIV2 signals.
NOTE
Selecting whether the low hysteresis limit is taken from DA0 signal or from
the configurable voltage divider has to be done by resoldering the zero
resistors R666 and R667. If R666 is populated, the DA0 signal is selected.
If R667 is populated, the configurable divider is selected. By default R666
is populated and R667 is not.
+5V_A
+5V_A
R657
33 +5V_D +5V_D
C627
100n R658 R659 R660 C628
3
GNDA 10k 10k R661 100n
U606A 10k 470
R662
R663 4 - V+ 2 470
DA1 5 + V-
3
LM339M D GND
100
U606B
12
C629 R664 6 - V+ G
100n 1.6k 1
7 + V-
GNDA Q609 S
GNDA LM339M MMBF0201NLT1
R665
R666
12
DA0
0
3
100
C630 R667 U606C R669 R670 TP611
GND
R668 100n 8 - V+ 10k 10k
PFC_CTRL
PWM_PFC
14
0
I_IN 9 + V-
C631
LM339M +5V_D
100 100n
12
GNDA GNDA R671
GNDA 4.7k
D
UNI-3 PFC_EN G
Q610 S
MMBF0201NLT1
60%
R673 R674 R675
All On 55%
3.3k
75%
10k
85%
9.1k GND
D D
DIV1 G DIV2 G
Q611 S Q612 S
MMBF0201NLT1 MMBF0201NLT1
GNDA GNDA GNDA U601 +15V_PFC
1 8 D609
R606
C609 GATE_PFC
PWM_PFC 2 7 100nF 10
BAT42
R607 D628
3 6
15V
100
4 5
GND
GND_PFC
HCPL3150
GND_PFC
Figure 4-20. PFC Current Controller

Hardware Design
4.5.2 PFC Booster Design Considerations

In this section we will discuss the design considerations of the PFC booster critical components.
4.5.2.1 PFC Boost Inductor L1

The input inductor must be selected with respect to two parameters, the input current ripple and the
switching frequency. It is designed for maximum input power, minimum input voltage, when the sine wave
current peak is at a maximum.
The maximum input current value is then calculated from the maximum output power Pout max and
minimum input voltage Vin min. We also have to include efficiency of the boost converter. For a continuous
current boost converter, the efficiency is estimated at 95%. The maximum current value is calculated as
follows:
Pout max 525
I in max = 2 ----------------------
- = 2 ------------------------ = 4.2A (EQ 4-32)
V in min 184 0.95
If we know the input current maximum value we can calculate a current ripple. We chose the current ripple
to be 15% of the input peak current. For the given peak current value it is:
I = I in max 0.15 = 0.645A (EQ 4-33)
When the PFC switch is turned on, the following equation has to be met:
I
L 1 -------- = V in (EQ 4-34)
T on
where
L1 = inductance of the input boost inductor

I = p-p input current ripple
Ton = turn-on time of the PFC switch
Vin = instantaneous input voltage value
Turn on time T on can be expressed from EQ 4-34 as follows:
I L
T on = ---------------1- (EQ 4-35)
V in
When the PFC switch is turned off, the following equation has to be met:
I
L 1 --------- = V in V out (EQ 4-36)
T off
where
Toff = turn-off time of the PFC switch

Vout = output voltage
Again, turn off time Toff can be expressed:
I L 1
T off = -----------------------
- (EQ 4-37)
V i n V out
Switching period T equals the sum of Ton and Toff times:

I L I L 1 I L 1 V out
T = T on + T off = ---------------1- -----------------------
- = ------------------------------------
- (EQ 4-38)
Vi n V in V out 2
V out V in V in
Frequency is an inverse value of the period. The switching frequency of the PFC is then given by the
formula:
2
1 V out V i n V in
f sw = --- = ------------------------------------
- (EQ 4-39)
T I L 1 V out
Switching losses of the IGBT transistor are proportional to the switching frequency. To maintain switching
losses within acceptable limits we have to design the input inductor L1 with respect to a maximum
switching frequency. From EQ 4-39, we can calculate the level of input voltage (Vin) when the switching
frequency reaches its maximum value. We get the maximum switching frequency at
V out
V in = ---------
- (EQ 4-40)
2
If we substitute EQ 4-40 for EQ 4-39 we can solve the equation and find the value of the required input
inductance value for the given ripple current (I), output voltage (Vout) and maximum switching frequency
(fmax):
V out
L 1 = --------------------------
- (EQ 4-41)
4 I f max
If we enumerate the equation for desired values we get:

390 3
L 1 = -------------------------------------------- = 2.5 10 H = 2.5mH (EQ 4-42)
3
4 0.645 60 10
To limit the maximum frequency at 60 kHz at ripple current 0.645 A, we choose the input PFC inductance
L1 = 2.5 mH.
4.5.2.2 L1 Inductor Core Selection

As soon as we know the required inductance, we can proceed to select the core material and size. For
the PFC application, we will consider an iron powder material.
Size of the core can be established based by an iterative process using manufacturers catalog data. We
have chosen Micrometals as a material supplier. They offer a design software, which makes this process
easier. We used this software to find the best fitting core.
In the window PFC Boost Design Requirements we entered the in following parameters (see Table 4-8).
Hardware Design
:
Table 4-8. PFC Inductor Parameters
INDUCTANCE AT MAX CURRENT 2500 H
MAXIMUM CURRENT 5 A
PEAK REGULATOR INPUT VOLTAGE 113 V
REGULATOR dc OUTPUT VOLTAGE 390 V
FREQUENCY 60 kHz
TEMPERATURE 55 C
CORE SHAPE TOROID -
WINDING TYPE FULL WINDOW -
We ran the calculation and got a list of suitable cores, that met our selection criteria. From the list we
selected core: T175-8/90. The software calculates all important data (number of turns, wire diameter,
losses, Rdc, Al, dimensions, etc.). For the selected core, the parameters are as follows:
Table 4-9. Design Parameters for Core P/N: T175-8/90
Al 48 nH
TURNS 287 -
WIRE 1.00 mm
FILL 38.9 %
Rdc 0.4971
Core Loss 0.28 W
Cu Loss 6.21 W
Temp. Rise 41.8 C
The core T175-8/90 meets all of our criteria, is an acceptable size, with moderate losses and good
linearity.
4.5.2.3 dc-Bus Capacitor Design

When designing a dc-bus capacitor, we must consider its rated voltage, capacitance, size, and cost.
Because there is no upper limit to the capacitance (the higher capacitance the better), we should focus
on finding the possible smallest capacitance, which still meets our requirements on dc-bus voltage ripple
and output voltage quality. The correct design of capacitor is very important and can significantly influence
final manufacturing cost of the product. The cost of capacitor rises exponentially with its rated voltage and
capacitance.
The dc-bus capacitor is a storage of energy for output power factor circuit and feeds an output inverter.
The dc-bus voltage should be set above the peak at maximum r.m.s. input voltage. For input RMS voltage
Vin = 270 V, the peak voltage is Vin peak max = 381 V. To achieve good regulation of the dc-bus voltage,
the dc-bus voltage should be at least 10% above the peak at nominal r.m.s. input voltage, i.e. for
Vin nom = 230 V RMS: Vdc-bus min = 1.1x1.41x230 = 356 V. Having Vin peak max and Vdc-bus min, we can
determine the dc-bus nominal voltage. We chose Vdc-bus nom = 390 V.
The dc-bus capacitor voltage should at least be rated at 450 V dc.
If ac input is lost, it is desired that the dc-bus capacitor is large enough to hold up the dc-bus voltage at
value Vdc-bus hup, allowing the output inverter voltage to remain within specifications for a time T hup.
The maximum nominal output voltage is Vout nom = 230 V RMS. The dc-bus voltage has to be higher than
the output voltage peak value Vout peak = 325 V. The hold-up time we define as a half-period of the output
ac voltage frequency Thup = 10ms. The minimum dc-bus capacitor value can calculated:
I av T hup
C 0 = ----------------------------------------------------- (EQ 4-43)
V dc busnom V outpeak
where
Iav is the average capacitor current during the drop from Vdc-bus nom to Vout peak.
The Iav current can be calculated according to the formula:
2P out
I a v = -------------------------------------------------------------- (EQ 4-44)
( V dc busnom + V outpeak )
where
Pout is the inverter output power
is the inverter efficiency
We can enumerate equation EQ 4-44 and obtain:
2 525
I a v = ---------------------------------------- = 1.728A (EQ 4-45)
0.85 ( 390 + 325 )
The minimum output capacitor value can be calculated if we enumerate formula EQ 4-43:
3
1.728 10 10 6
C 0 = --------------------------------------- = 266 10 F (EQ 4-46)
390 325
The minimum output capacitance of the dc-bus capacitor is 266F.
The next parameter we need to know for selecting the output capacitor is the ripple current rating. The
dc-bus capacitor current consists of a dc-component plus an ac-component (100/120 Hz). The
dc-component flows to the load, ac-component flows into the capacitor C0. The ripple current amplitude
is equal to the peak load current. The ripple current can be then calculated:
I load
I ri ppl e = ---------
- (EQ 4-47)
2
The peak load current Iload is:
Pout 525
I l oad = ------------------------------------------
- = ------------------------------- = 0.792A (EQ 4-48)
2 V dc busnom 2 390 0.85
Hardware Design
Ripple current is then: Iripple = 0.792/1.41 = 0.562 A.

The waveform applied to the dc-bus capacitor is a near-rectangular waveform at the switching frequency.
Therefore the dc-bus capacitor should have a low impedance at the switching frequency. A low-ESR
electrolytic capacitor should be considered for this application.
Considering all the above requirements, we selected following dc-bus capacitor:
Table 4-10. dc-bus Capacitor Parameters
Manufacturer BC Components (Vishay)
Catalogue Number 2222 157 47331
Rated Capacitance 330 F
Rated Voltage 450 V d.c.
ESR @ 100 Hz 300 m
Ripple Current@ 120 Hz 2.19 A
4.5.3 Output Inverter Operational Description

This section deals with the design of the output inverter of the single-phase UPS. The purpose of the
output inverter is to convert dc-voltage of the dc-bus to an output single-phase sinusoidal voltage of the
required amplitude and frequency.
The topology of the inverter circuitry is shown in Figure 4-21. The power circuit consists of IGBT power
switches Q605 and Q608, which are connected across dc-bus capacitors C602, C608. An emitter
terminal of Q605 and a collector terminal of Q608 are connected to a sinusoidal filter (inductor L506 and
a capacitor C605). Output of the sinusoidal filter is then connected to the by-pass relay RE2 and EMC
filter (L205, C604, C602). Output relays RE1, RE3, connect the inverter output to output terminals of the
UPS. The nominal specifications of the output inverter are listed in theTable 4-11.
Table 4-11. Output Inverter Specifications
Input Voltage Min. 2x340 V[d.c.]
Input Voltage Max. 2x430 V[d.c.]
Output a.c. Voltage 80 - 270 V [r.m.s.]
Output Apparent Power Nominal(1) 750 VA
Output Current Nominal 3.3 A[r.m.s]
1. Nominal output apparent power for nominal output voltage 230 V r.m.s.
RE1
MZPA001
5 o
o 4 OUT1
3 o
+15V 1 2
RE2
MZPA001
D602
5 o
D
o 4
BAT42
L2 3 o R602
G
RLY_OUT1
100 Q602 S
+15V 1 2 MMBF0201NLT1
GND
D603 RE3
MZPA001
BAT42 D
5 o
R603 o 4 OUT2
RLY_BYPASS G
100 3 o
Q603 S
MMBF0201NLT1
GND +15V 1 2
DCB_POS
D605
BAT42 D
R604 G
RLY_OUT2
100
Q604 S
MMBF0201NLT1
Q605 GND
GATE_TOP
C602
+ HGTG10N120BND
V_OUT
GND_TOP L506
330uF/450V
5mH C604
C605 2 L507 1 PE
6.8uF/400V 4 3 4.7nF/Y1 C606
TL34P 4.7nF/Y1
N
N_OUT
1
2
3
4
CT2
GND
CS2106
8
5
I_OUT2 I_OUT1
Q608
GATE_BOT
+ C608
330uF/450V HGTG10N120BND
GND_BOT
DCB_NEG
Figure 4-21. Output Inverter Power Circuit

Hardware Design
The power IGBTs Q605 and Q608 switch in a complementary manner (if Q605 is on, Q608 is off, and vice
versa). Using the power IGBTs, the dc-bus voltage is pulse-width modulated at 20kHz switching
frequency to obtain an output voltage with a low frequency a.c. component (50/60 Hz). The junction of
C602 and C608 is a zero-volts reference for the generated output waveform. The junction of the
capacitors is galvanically connected to the mains N-terminal and is labelled as system ground.
Switching pulses to gates Q605 and Q608 are generated by the dual IGBT gate opto-drive HCPL-315J
(U615). The opto-drive provides the circuitry with galvanic isolation between the MCU and each of the
IGBTs. Its topology is shown in the Figure 4-22. The IGBT gates are floating during the inverter operation
in a voltage range +/- 430 V dc. Each channel of the dual opto-drive IC is supplied from a galvanically
isolated voltage supply of +15V dc.
GATE_TOP
D611 +15V_TOP
D624
D610 15V
R609
BAT42
C610
R608 100nF 33
BAT42 D625
PWM_TOP R610 5V
330
100
GND_TOP
U615
D613 1 16
N/C VCC1 C632
2 15 GND_TOP
ANODE1 VO1 100nF
3 CATHODE1 VEE1 14
BAT42
R611
PWM_BOT 6 11 -5V_TOP
ANODE2 VCC2
330 7 CATHODE2 VO2 10 GATE_BOT
8 N/C VEE2 9
+15V_BOT
HCPL-315J D626
D612 15V
R612
C611
100nF 33
GND BAT42 D627
R613 5V
100
GND_BOT
C633
100nF
GND_BOT
-5V_BOT
Figure 4-22. Inverter IGBT Gate Drive Circuitry

The by-pass relay RE2 connects the UPS output to either the inverter or the mains voltage.
The relays RE1 and RE3 connect the UPS output socket banks to the output voltage.
A current transformer CT2 is put into the output current path. Together with current-to-voltage converter
circuitry, it makes up the sensing circuitry of the output load current.
NOTE
Please note that during operation, the voltage on the power IGBTs is a sum
of the voltages on the dc-bus capacitors, i.e., it can reach up to
2 x 430 V = 960 V! The IGBTs must be rated for a collector-emitter voltage
of 1200 V.
4.5.4 Output Inverter Design Considerations

In this section we will discuss the design considerations of the critical components of the output inverter.
The sinusoidal output filter is a low-pass LC-filter consisting of an inductor L506 and a capacitor C605.
The resonant frequency of the circuit has to be selected with respect to the output voltage control loop.
Based on the Simulink simulation results we have selected a resonant frequency in the range:
600 to 900 Hz.
Having the resonant frequency we are able to select values of the inductor and capacitor. To achieve the
required resonant frequency of the filter we have plenty of variants of L and C distribution. The values of
the components have to be selected with consideration of their size, cost and availability. Considering the
components available in the market, we have chosen following combination:
L506 = 5 mH
C605 = 6.8 F
The resonant frequency of such a circuit is 863 Hz and falls in our range.
4.5.4.1 C605 Capacitor Selection

The capacitor parameters have to fulfil safety requirements for rated ac voltage. Low ESR and ESL
parameters are required to achieve a low output voltage ripple. For the output sinusoidal filter we selected
MKP 338 4 X2 capacitor from Vishay BC components. See Table 4-12.
Table 4-12. MKP 338 4 X2 Capacitor Reference Data
Parameter Value
Capacitance 6.8 F
Capacitance tolerance 20%
Rated (ac) voltage, 50 to 60 Hz 300V
Rated (dc) voltage 630V
Rated temperature 105C
Safety class X2; across the line
4.5.4.2 L506 Inductor Core Selection

As soon as we know the required inductance, we can proceed to select the core material and size.
Because the inductor current contains a high frequency ripple, we will consider an iron-powder core.
Size of the core can be established by an iterative process using the manufacturers catalog data. We
have chosen Micrometals as the material supplier. Again as with the PFC inductor design, we used the
Micrometals software to find the best fitting core.
For the design of the output filter inductor, we can use either dc biased design or PFC boost. The
calculations of both are similar, however, the PFC Boost calculations account for a periodic change to
the switching duty-cycle. We can thus more accurately represent the losses in the inductor core.
Therefore we selected PFC Boost design. In the parameter window of the design, we entered the
parameters shown in Table 4-13.
Hardware Design
Table 4-13. Output Filter Inductor Parameters
Inductance at max current 5000 H
Maximum current 4.6 A
Peak regulator input voltage 340 V
Regulator dc output voltage 400 V
Frequency 20 kHz
Temperature 55 C
Core shape Toroid -
Winding type Full window -
NOTE
Note that we swapped the input and output peak voltage values in the
design parameters. In a real inverter, the dc voltage is the input parameter
and the ac voltage is the output parameter. To make an analogy with PFC,
we have to swap these parameters in the input table.
We ran the calculation and got a list of suitable cores that met our selection criteria. From the list we
selected core: T200-30B. The software calculates all important data (number of turns, wire diameter,
losses, Rdc, Al, dimensions, etc.). For the selected core, the parameters are as follows:
Table 4-14. Design Parameters for Core P/N: T175-8/90
Al 51 nH
Turns 388 -
Wire 1.00 MM.
Fill 38.5 %
Rdc 0.8868 Ohms
Core loss 1.46 W
Cu loss 9.38 W
Temperature rise 46.4 C
The core T200-30B meets all of our criteria, is an acceptable size, with moderate losses and low price.
Chapter 5
Software Design
5.1 Introduction
This section describes the design of the software blocks for the UPS. The software is described in terms
of:
Data flow
Main software flowchart
State diagram
For more information on the control technique used, see Chapter 3 UPS Control.
5.2 Data Flow

The control algorithm obtains values from the user interface and sensors, processes them, and generates
PWM signals for the dc/dc step-up converter, output inverter, and sine wave reference for PFC, as can
be seen on the data flow analysis shown in Figure 5-1.
5.2.1 Software Variables and Defined Constants

Important system variables, named in the data flow, are listed in Table 5-1. The table includes the name,
range used, and representation in real quantities.
counter_actual
Button
v_out_rms Processing
PLL
Algorithm
Mains Line buttonStatus
RMS Detection
Correction
phase_pfc phase_out
Application State
phase_pfc_inc phase_out_inc amplitude_correction amplitude_ref v_out_freq_detect v_dcb[] Machine
Sine Wave DC Bus

v_dcb_req Scaling appState
Reference
Ramp
v_sin_ref v_out PWM_to_DCB_scale LED
Processing
v_dcb[] v_dcb_req_rmp v_dcdc_req
Inverter
Control
PFC Control V_bat I_bat
Ramp
PWMB_duty_cycle
i_n_ref Battery Charge
v_dcdc_req_rmp v_dcdc_sum Control
Sine Wave
Reference DC/DC Step Up
Control BatState
pfc_ref_h
PWMC_duty_cycle
Figure 5-1. Main Data Flow

Data Flow
Table 5-1. Software Variables

Name Type <Range>; [Scale] Description
amp_ControllerPar Structure - PI controller parameters for RMS correction
amplitude_correction U16 <0, 39936>; [0V, 400V] output of RMS correction
amplitude_ref U16 <0, 39936>; [0V, 400V] required amplitude of output sine wave
appState enum - state of application state machine
BatState enum - state of battery charger
<0,5580>; [0 s, 7.14 ms (70
counter_actual U16 period of input voltage zero crossing
Hz)]
dcdc_duty U16 <0, 121>; [0%, 96.8%] duty cycle of dc/dc step-up converter
i_bat S16 <0, 1023>; [0 A, 2.34 A] battery charging current
<-32768, 32767>;
i_out S16 actual output current
[-13 A, 13 A]
<-32768, 32767>;
i_out_rms S16 RMS value of output current
[-13 A, 13 A]
pfc_ref_h U8 <0, 152>; [0 A, 5 A] required actual input (PFC) current
<-32768, 32767>; phase difference between expected and actual
phase_diff S16
[-180, 180] phase of PLL
<-32768, 32767>;
phase_measured S16 calculated phase
[-180, 180]
<-32768, 32767>;
phase_out S16 actual phase of generated output voltage
[-180, 180]
<33554, 58720>;
phase_out_inc U16 increment to sine wave table (output voltage)
[40 Hz, 70 Hz]
<-32768, 32767>;
phase_pfc S16 actual phase of input voltage calculated by PLL
[-180, 180]
PWMB_duty_cycle U16 <0, 625>; [-100%, 100%] duty cycle of output inverter
PWMC_duty_cycle U16 <0, 121>; [0%, 96.8%] duty cycle of dc/dc step-up converter
temperature U16 <0, 205>; [0 C, 100 C] temperature of power stage heatsink
v_bat U16 <0, 1023>; [0 V, 39 V] battery voltage
v_dcb[] U16 <0, 1023>; [0 V, 450 V] dc bus voltage
v_dcdcControllerPar Structure - PI controller parameters for dc/dc controller
v_in U16 <0, 1023>; [0 V, 324 V] RMS value of input voltage
<-19968, 19968>;
v_out S16 actual output voltage
[-400 V, 400 V]
<33554, 58720>;
v_out_freq_detect U16 detected input frequency
[40 Hz, 70 Hz]
<-19968, 19968>;
v_out_rms U16 RMS value of output voltage
[-400 V, 400 V]
v_pfcControlerPar Structure - PI controller parameters for PFC controller
<-19968, 19968>; required value of output voltage (sine wave
v_sine_ref S16
[-400 V, 400 V] reference including amplitude correction)
Type: S8 = signed 8-bit, U8 = unsigned 8-bit, S16 = signed 16-bit, U16 = unsigned 16-bit.
Software Design
5.2.2 Process PLL Algorithm

The PLL algorithm synchronizes the pointer to the PFC sine wave reference with the input line voltage.
The algorithm uses the variable counter_actual as an input and calculates the phase_pfc,
phase_pfc_inc, phase_out and phase_out_inc. The variables relating to the output inverter are
generated if the output is synchronized with the output.
5.2.3 Process RMS Correction

Because the output inverter PID controller is not able to keep a constant RMS value of output voltage due
to slight or missing integral part of the controller, the RMS correction must be calculated. The RMS
controller compares the actual RMS value v_out_rms with the required RMS value calculated from
amplitude_ref. The output of PI controller is correction to the amplitude, stored in
amplitude_correction.
5.2.4 Process Mains Line Detection

This process sets the mains line system to 230 V, 50 Hz or 115 V, 60 Hz according to state of
START/STOP switch on the MC9S12E128 controller board. The detected values amplitude_ref and
v_out_freq_detected are used for the output inverter to generate the correct output and for the PFC
PLL to determine that the PLL algorithm is synchronized.
5.2.5 Process Ramp

The ramp process changes an input value in a time period with a predefined slope. A different ramp can
be defined for a rising and falling slope.
5.2.6 Process Sine Wave Reference

The sine wave reference process generates the sine wave reference waveform v_sin ref based on the
actual phase phase_out, phase increment corresponding to the generated frequency phase_out_inc,
and amplitude amplitude_ref + amplitude_correction.
5.2.7 Process Button Processing

The button processing reads the status of the ON/OFF and BYPASS buttons. It recognizes a short and
long push. The results are saved in variable buttonStatus.
5.2.8 Process LED Processing

The process handles the LEDs on the user interface. Each LED can be switched on, off, or to flash. The
LED status bar works in two modes. In output power mode, the status bar displays the actual output
power. In battery mode it shows remaining battery capacity.
5.2.9 Process Application State Machine

This process provides the state machine of UPS. The state machine defines the following states:
Init
Standby on battery
Standby on line
Run on battery
Data Flow
Run on line
Run on bypass
Error
UPS off
After RESET, the state machine enters into the Standby on battery state if the mains line is available.
Then if the user pushes the ON/OFF button, the state machine continues on to the Run on line state.
During mains line failure, the state machine goes to the Run on battery state. The state machine stays
there until the batteries are discharged, the user switches the UPS off, or the main line is restored. If the
batteries are discharged the state machine goes to the Standby on battery state. If the state machine
stays in this state one minute, the UPS is switched off (UPS state) to avoid total discharge of the batteries.
In the case of some fault, the state machine goes into the Error state.
If the state machine goes from one to another state, a respective transition function is called.
CPU RESET
INIT
STANDBY STANDBY RUN

RUN ON LINE ERROR
BATTERY ONLINE ON BATTERY
RUN BYPASS
UPS OFF
Figure 5-2. Application State Machine
5.2.10 Process PFC Control
The PFC control process consists of the PI controller, which controls the dc bus voltage
v_dcb[] to the required value v_dcb_req (v_dcb_req_rmp). The result defines the
amplitude of the input current (i_n_ref).
Software Design
5.2.11 Process Sine Wave Reference (PFC)

This process generates a rectified sine wave waveform based on the required amplitude i_n_ref, actual
phase phase_pfc, and the required frequency phase_pfc_inc. The result pfc_ref_h is sent to the
D/A converter and is used as the reference for the external current controller.
5.2.12 Process dc Bus Scaling

The scaling process calculates the correction constant PWM_to_DCB_scale for inverter duty cycle. The
duty cycle, which outputs from the PID controller, is related to constant dc bus voltage. If the actual dc
bus is different, the duty cycle has to be recalculated to the actual dc bus. For example, if the output duty
cycle is 50% (195 V) for 390 V of dc bus voltage and the actual dc bus voltage is equal to 380 V, the
resultant duty cycle has to be recalculated to 51.3% to maintain 195 V.
5.2.13 Process dc/dc Step-Up Control

The process is similar to the PFC control process. The input value is v_dcdc_req (v_dcdc_req_rmp)
and the result is PWMC_duty_cycle.
5.2.14 Process Inverter Control

The inverter control process performs PID controller including feed forward technique. The inputs are
v_sin_ref, v_out, and PWM_to_DCB_scale, and the output is the duty cycle PWMB_duty_cycle.
5.2.15 Process Battery Charge Control

The battery charger control process charges the batteries. The charging current i_bat and battery
voltage v_bat are read, and according to the actual battery current, the state of the charging algorithm
BatState is set to BULK CHARGE MODE, ABSORPTION MODE, or FLOAT MODE.
5.3 Main Software Flowchart

The software is written in C language using Metrowerks CodeWarrior software. Some time-critical parts
such as sine wave generation and arithmetical functions are written in assembler.
The software consists of the following parts:
Initialization of peripherals and variables
Background group
5 periodic interrupts (2 x 50 s, 1 x 1 ms, 1 x 10 (8.3) ms, 1 x 50 ms)
3 event interrupts (PMF faults, LVI, SCI)
5.3.1 Initialization of Peripherals and Variables

After RESET, the program goes into the initialization routine. The routine initializes the following
peripherals:
PLL
I/O pins
Analog to digital converter
Digital to analog converter
Pulse-width modulator with fault protection
Timer 0
Main Software Flowchart
Pulse-width modulator
Voltage regulator
Subsequently, the communication with the PC is initialized, and the program variables are set to default
values.
Then the program enters the never-ending loop providing the application state machine (see main
function listing below).
void main ()
{
InitPeripherals();
PCMaster_Config();
EnableInterrupts; /* enable interrupts to make this routine
interruptible
(defined int PCMaster-S12.h) */
PCMasterInit(); // init PCMaster functions
InitVariables();
while(1)
{
appStateFcn[appState]();
FanControl();
}
}
The structure of the background loop can also be seen in Figure 5-3.
RESET
Peripheral and variable

inicialization
Background loop
Application state machine

execution
END
of Background loop
Figure 5-3. Background Loop
Software Design
5.3.2 Periodic Interrupts

The software uses five periodic interrupts. They are:
PMF reload interrupt (called every 50 s)
ATD conversion complete interrupt (called every 50 s)
TIM0 CH4 input capture interrupt (called every 8.3 or 10 ms)
TIM0 CH5 output compare interrupt (called every 1 ms)
TIM0 CH6 output compare interrupt (called every 50 ms)
5.3.2.1 PMF Reload Interrupt

The PMF Reload Interrupt is part of the UPS main control loop. The source of the interrupt is a reload
event of counter B (output inverter). The structure of the interrupt can be seen on Figure 5-4.
PMF B Reload Interrupt

(50 ms)
Read samples
of slow ATD Conversion
Start fast ATD Conversion
Lost detection
of Line Zero Crossing
Output power and

RMS Value Calculation
Input voltage polarity detection
PFC reference sine wave

generation
Inverter reference sine wave

generation
END
of Interrupt Service Routine
Figure 5-4. Structure of PMF Interrupt

The interrupt starts by reading a slow ATD conversion. A slow ATD conversion means that the quantities
are not converted every 50 s. There is a table which defines the order of quantities to be converted. The
results of a slow ATD conversion are ready from previous interrupt.
After saving the conversion results, a fast ATD conversion is set and started. A fast ATD conversion
means that the quantities are converted every interrupt (50 s). The output voltage and current are
sensed in the fast ATD conversion.
While the fast ATD conversion is running the following tasks are performed:
Detection of missing zero crossing on the input line
Detection of input voltage polarity
RMS value calculation and output power calculation (multiplication and addition)
Generation of rectified sine waveform for the PFC
Generation of sine wave reference for the output inverter
The execution time for these tasks is shorter than the conversion time in a fast ATD conversion.
5.3.2.2 ATD Conversion Complete Interrupt

As soon as the fast conversion is completed and the PMF reload interrupt executed, the ATD conversion
complete interrupt is called. This interrupt performs the inverter control and starts the next slow ATD
conversion (see Figure 5-5). Because this interrupt is bounded by the PMF reload interrupt, the execution
period is also 50 s.
Both interrupts, together with the TIM0 CH5 output compare interrupt, comprise the main part of the UPS
control algorithm. The PMF reload and ATD conversion complete interrupts have the highest priority and
are uninterruptible.
ATD Conv. Complete Interrupt

(50 ms)
Start fast ATD conversion
Output inverter controller
END
Figure 5-5. Structure of ATD Conversion Complete Interrupt
5.3.2.3 TIM0 CH4 Input Capture Interrupt

The source of this interrupt is a zero crossing on the input voltage. So the interrupt is executed every
8.3 ms or 10 ms. The interrupt performs a phase locked loop algorithm, which synchronizes the
generation of PFC and output inverter sine wave references with the input voltage.
Software Design
TIM 0 ch 4 IC Interrupt
(Line Zero Crossing)
PFC PLL algorithm
END
Figure 5-6. TIM0 CH4 Input Capture Interrupt
5.3.2.4 TIM0 CH5 Output Compare Interrupt

The source of this interrupt is the output compare event, set to generate event every 1 ms. This interrupt
comprises the second part of the control algorithm. The structure of the interrupt is shown in Figure 5-7.
TIM 0 ch 5 OC Interrupt
(1 ms)
PFC control loop
DC/DC step up converter

control loop
Filtering and scaling

of analog values
Output power and

RMS values calculation
RMS correction
END
Figure 5-7. Structure of TIM0 CH5 Output Compare Interrupt

The interrupt performs following tasks:
Voltage control loop of the PFC
dc/dc step-up converter control loop
Filtering and scaling of analog values measured in the slow ATD conversion
finishing the RMS and output power calculations (multiplication by constant and square root)
RMS correction algorithm
This routine has a lower priority and can be interrupted by the PMF reload and ATD complete interrupts.
5.3.2.5 TIM0 CH6 Output Compare Interrupt

The last periodic interrupt is called every 50 ms. The time base is derived from TIM0 CH6 output compare
event, which is set to generate this period. The interrupt performs background tasks which require
periodic execution but with a very low priority. The tasks are:
Software timers
User interface handling (buttons, LED diodes)
Battery charger algorithm
TIM 0 ch 6 OC Interrupt
(50 ms)
Software timers
User interface handling
Battery charging
END
Figure 5-8. Structure of TIM0 CH6 Output Compare Interrupt
5.3.3 Event Interrupts

The event interrupts are called on an event. The UPS application uses following event interrupts:
SCI interrupt (performing the communication with PC)
PMF fault interrupt
Voltage regulator low voltage inhibit interrupt
5.3.4 Interrupt Time Execution and MCU Load Estimation

The time execution of periodic interrupts was measured by oscilloscope. The result can be seen in
Figure 5-9.
Software Design
Trace
PMF Reload Interrupt
Trace
ATD Complete Interrupt
Trace
1 ms Interrupt
Trace
50 ms
Figure 5-9. CPU Load of UPS Application

Trace 1 (blue) represents a PMF reload interrupt; Trace 2 (cyan) is an ATD complete interrupt; Trace 3
shows 1 ms interrupt; Trace 4 (green) is 50 ms. The total MCU load is 65.16%. The execution time of each
interrupt can be seen in Table 5-2, and the size code in Table 5-3.
Table 5-2. Execution Time of Periodic Interrupts
Execution Execution
Name
Period Time
PMF reload interrupt 50 s 15.8 s
ATD conversion complete interrupt 50 s 14.2 s
TIM0 CH4 input capture interrupt 8.3 ms or 10 ms 7.8 s
TIM0 CH5 output compare interrupt 1 ms 50 s
TIM0 CH6 output compare interrupt 1 ms 35.8 s
Table 5-3. Size of UPS Application Code
Memory Type Size in Bytes
FLASH 10087
RAM 2502
Stack 512
Software Constant Calculations
5.4 Software Constant Calculations

This section describes the calculation of some software constants from real values to software
implementation.
5.4.1 PI and PID Controller Constants

Because the MCU works with integer arithmetic only each constant KREAL in the real system is expressed
in the software as:
GAIN
K REAL = -----------------------------
( 16 SCA LE )
2 (EQ 5-1)
To keep the maximal precision of calculation, the SCALE should be set in order to push the GAIN into the
upper half of the variable range.
Example:
Lets convert a constant 25 in U16 representation. The upper half of the U16 range is from 32768 to
65536. The get this constant to optimal range we set the SCALE to 5. Then the GAIN = 25 .
2(16-5) = 51200.
NOTE
Note that the SCALE is shared for all constants in the PI/PID controller. So
in case of a highly different order in the constants, a compromise has to be
made.
The controller implementation is explained in 3.1.5 PI and PID Controller. From EQ 3-7 results, the
proportional constant is equal to the gain of the system.
The integral constant of the controller can be expressed as:
Kh
------- (EQ 5-2)
TI
where
TI = Integral time constant
h = Sampling time
K = Controller gain
See EQ 3-8. The derivative constants are defined as:
TD
kd1 = --------------------
-
T D + Nh (EQ 5-3)
KT D N (EQ 5-4)
kd2 = --------------------
-
T D + Nh
Software Design
where
h = Sampling time
TD = Derivative time constant
N = Filter constant
NOTE
The proportional constant of the output inverter controller is called q1 in the
software.
Example:
Lets have constants for the PFC controller. The PFC uses the PI controller, where the controller gain
K(P) = 100 and Integral time constant TI = 0.0016 s. The controller is calculated every 1 ms.
3
100 1 10
From EQ 5-2 we can calculate integral constant as: ------------------------------
- = 6.25 .
0.0016
Since the scale is common for both constants, we choose SCALE = 8. Then we get a proportional gain
100 . 2(16-8) = 25600 and an integral gain 6.25 . 2(16-8) = 1600. In the source code we can see:
#define PFC_P_GAIN_BASE 25600

#define PFC_I_GAIN_BASE 1600
#define PFC_SCALE 8
Chapter 6
6.1 Test Equipment

All tests were done using the following equipment:
2x multimeter 34401A, Hewlett Packard
Scope TDS3014B, Tektronix
3-phase precision power meter LMG 310, Zimmer Electronic Systems
6.2 Load Parameters

The parameters were measured for both linear and non-linear loads. The loads were calculated according
to standard IEC 62040-1. The reference load was calculated for a nominal output power of 750 VA. The
parameters of the loads are:
Linear load: R = 100
Non-linear load: R = 160 W, RS = 2.8 W, C = 780 mF (see Figure 6-1)
D1 D3
Rs
2.8 + P1
C1 160
937 uF
D2 D4
Figure 6-1. Non-Linear Load
6.3 Test Results
6.3.1 Overall Efficiency at Linear Load

The total efficiency at a linear load is 91%. See Figure 6-2. The picture shows the display of 3-phase
precision power meter indicating the input power (P1), output power (P2), losses (LOSS) and calculated
efficiency (EFF).
Figure 6-2. Overall Efficiency at Linear Load
Figure 6-3. Output Voltage and Current at Linear Load
6.3.2 Overall Efficiency at Non-linear Load
The total efficiency at a non-linear load is 90%. See Figure 6-4.
Figure 6-4. Overall Efficiency at Non-linear Load
Figure 6-5. Output Voltage and Current at Non-linear Load
6.3.3 Output Frequency Measurement

The next two pictures show the generation of output frequency. The left multimeter shows input
frequency, and the right one shows output frequency. Figure 6-6 shows the synchronized output with
input. Figure 6-7 shows a free running mode. In this case the precision of the output frequency is given
by the precision of the MCU crystal.
Figure 6-6. Output Frequency in Synchronized Mode
Figure 6-7. Output Frequency in Free-running Mode
Test Results
6.3.4 Output Voltage THD

Output voltage THD was measured for three cases:
Without load: THD = 0.4%
With full linear load: THD = 1%
With full non-linear load: THD = 5%
The next two pictures show details of output voltage and current at a non-linear load.
Figure 6-8. Output Voltage and Current at Non-linear Load Detail
Figure 6-9. Output Voltage and Current at Non-linear Load
6.3.5 Power Factor Measurement

The power factor measured can be seen in Figure 6-10. The figure shows input voltage U3, input current
I3, and power factor 3.
Figure 6-10. Power Factor Measurement
6.3.6 Response on Step Load

The following four pictures show the response of the output controller a on step load from 20% to 100%,
and vice versa, for a linear load.
Test Results
Figure 6-11. Load Step from 20% to 100%
Figure 6-12. Load Step from 20% to 100% Detail
Figure 6-13. Load Step from 100% to 20%
Figure 6-14. Load Step from 100% to 20% Detail
Test Results
6.3.7 Summary
All measured parameters are summarized in Table 6-1
Table 6-1. Summary of Measured Parameters
Load
Parameter
Linear Non-linear
Efficiency 91% 90%
Output voltage THD without load 0.4%
Output voltage THD 1% 5%
Power factor 0.99
Precision of generated frequency < 0.01%
Chapter 7
WARNING
This application operates in an environment that includes dangerous
voltages. The application includes batteries and dangerous voltage
may appear even if the application is not connected to the mains line.
An isolating transformer should be used during debugging. If an
isolating transformer is not used, power stage grounds and
oscilloscope grounds will be at different potentials, unless the
oscilloscope is floating. Note that probe grounds, such as in the case
of a floating oscilloscope, are subject to dangerous voltages. Take
note of the following points and recommendations
Switch off the high-voltage supply before moving scope probes or

making connections.
Avoid inadvertently touching live parts, and use plastic covers
where possible.
When the high voltage is applied, using only one hand to operate
the test setup will reduce the possibility of electrical shock.
Avoid using the application in laboratory environments that have
grounded tables or chairs.
Wear safety glasses, avoid ties and jewelry, use shields, and make
use of personnel trained in high-voltage laboratory techniques.
The power module heatsink can reach temperatures hot enough to
cause burns.
When powering down, due to storage in the bus capacitors,
dangerous voltages are present until the power-on LED is off.
7.1 Hardware Setup

The UPS demo is mounted into a metal case which provides safe operation. The case cover is made from
transparent plastic, which allows the UPS construction to be seen (see Figure 7-1).
Figure 7-1. UPS Demo

WARNING
Do not touch any part of the board inside the metal case regardless of
whether the UPS is running from mains line or batteries. There is a
high risk of electric shock caused by high voltage, which may cause
serious injury or death.
To prepare the UPS for operation, follow these steps:
1. Connect the power supply cable to the INPUT LINE socket.
2. Connect the load supply cable to any OUTPUT SECTION socket. Be sure that the load power is
within the limit of the UPS demo.
3. In the case of remote operation from a PC, connect a serial cable between the PC and the J2
connector of the UPS (on the right-hand side in Figure 7-3 and Figure 7-5).
4. Switch MAINS INPUT LINE switch ON.
If the mains line is available, the UPS will go into standby on-line mode. In this mode, the MCU
works and the batteries are charged, but the output is still switched off.
5. In the case of remote operation, run the FreeMaster software on the PC and load the project file,
UPS.pmp.
The UPS is ready for operation.
MAINS LINE OUTPUT
SWITCH SECTION 2
OUTPUT
SECTION 1
MAIN LINE
INPUT
Figure 7-2. UPS Input and Outputs
7.1.1 Setting of Mains Line System

Because the UPS can not detect the mains line system if it starts to run from batteries, the system can be
predefined by the START/STOP switch on the MC9S12E128 controller board. If the switch is in the RUN
position, the UPS generates outputs 230 V, 50 Hz. In STOP position, the UPS generates 115 V, 60 Hz.
External Battery Serial Ports

Connector
Figure 7-3. UPS Serial Ports and External Battery Connector
7.2 Software Setup
7.2.1 Application Software Files

The application software files are:
...\software\UPS\OnlineUPS\on_line_ups.mcp, application project file
...\software\UPS\OnlineUPS\sources\main.c, main program
...\software\UPS\OnlineUPS\sources\main.h,
header file for main code
...\software\UPS\OnlineUPS\sources\PCMaster.c, library of FreeMaster functions
...\software\UPS\OnlineUPS\sources\PCMaster.h,
library of FreeMaster functions definitions file
...\software\UPS\OnlineUPS\sources\PCMasterConfig.h,
configuration file for FreeMaster
...\software\UPS\OnlineUPS\sources\projectglobals.h, global definitions file of HCS12
stationary
...\software\UPS\OnlineUPS\sources\projectvectors.c, source file of interrupt routines
...\software\UPS\OnlineUPS\sources\projectvectors.h, header file for interrupt routines
...\software\UPS\OnlineUPS\sources\START12.C, start up code for HCS12 stationary
...\software\algorithms\sin.asm,
library with sine wave generation functions
...\software\algorithms\sin.h,
header file for sine wave generation functions
...\software\algorithms\sinlut.asm,
sinus look up table for sine wave generation functions
...\software\algorithms\upsmath.asm,
library of mathematical functions written in assembler
...\software\algorithms\upsmath.c,
library of mathematical functions written in C language
...\software\algorithms\upsmath.h,
header file for library of mathematical functions
7.2.2 Application PC Master Software Control Files

The application PC master software control files are:
...\software\UPS\OnlineUPS\PCMaster\UPS.pmp,
PC master software project file
...\software\UPS\OnlineUPS\PCMaster\source,
directory with PC master software control page files

Software Setup
7.2.3 Application Build

To build the online UPS application, open the on_line_ups.mcp project file and execute the Make
command, as shown in Figure 7-4. This will build and link the application with all the required Metrowerks
libraries.
Figure 7-4. Execute Make Command

7.2.4 Programming the MCU

Because the UPS power supply is controlled by the MCU, the following sequence must be used to
program the MCU:
1. Switch the UPS OFF by the ON/OFF switch
2. Switch the MAINS LINE switch to OFF
3. Wait one minute until the UPS has totally switched off
4. Disconnect the power supply cable from the socket
5. Remove the transparent plastic cover
6. Disconnect the cable from J4 on the user interface
7. Connect a BDM cable to the MC9S12E128 controller board
8. Connect the cable to any test point named GND on the UPS power stage (e.g., TP206)
9. Load the code to the MCU
10. Remove the cable from GND test point and wait until the UPS has totally switched off
11. Connect the cable back to J4 on the user interface
12. Re-install the transparent plastic cover
WARNING
The BDM connector is not galvanically isolated. Therefore, be sure
that the UPS is disconnected from the mains line during
programming.
7.3 Application Control

The UPS can be controlled by the MAINS LINE switch (Figure 7-2) and by the two ON/OFF or BYPASS
buttons. The status of the UPS is indicated by four LEDs and an LED bar graph.
7.3.1 On-line Operation

If the mains line is available and the UPS is set up as is described in 7.1 Hardware Setup, the UPS is in
standby on-line mode. To switch the UPS on, quickly push the ON/OFF button. As soon as the button is
released the UPS goes into run on-line mode. All UPS outputs are active and the UPS supplies the load.
The run on-line mode is indicated by the green status LED. The actual load is indicated by LED bar graph.
Optionally, a bypass can be activated by quickly pushing the BYPASS button. In bypass mode the load
is connected directly to the mains line. The bypass mode is indicated by the yellow LED.

Application Control
ON/OFF Status
Button LEDs
LED Bargraph
Bypass
Button
Figure 7-5. UPS User Interface

In the case of a mains line failure, the UPS automatically goes into run on battery mode. If the UPS is in
bypass mode at the moment of the failure, the UPS is switched off. Run on battery mode is indicated by
the orange LED and the UPS regularly beeps. If the batteries are discharged the UPS switches the
outputs off and goes into standby on battery mode. In this mode the UPS stays for one minute, then
switches itself off.
Then user can switch the UPS by pushing the ON/OFF button for more than four seconds, during this time
the UPS constantly beeps.
7.3.2 Battery Operation

If the mains line is not available, the UPS goes directly into run-on-battery mode after the ON/OFF button
is pressed for less than four seconds and released. The bypass is not available during battery operation.
The UPS can be switched off by the user in the same way as in on-line operation. If the mains line is
restored during battery operation, the UPS goes automatically into the run on-line mode.

7.3.3 Remote Operation

If the UPS is connected to the PC it can be controlled by the FreeMaster software. The FreeMasters
control page offers the same interface, so that the UPS can be controlled from in the same way. The
remote control works in parallel with the user interface.
Figure 7-6. UPS Project in FreeMaster

In addition to remote control, the FreeMaster displays the values of some variables. There is also a
recorder and scope showing the output voltage and temperature of the power stage.

Application Control
Appendix A. Schematics
A.1 Schematics of Power Stage

5 4 3 2 1
J101
J104 J100 PSH02_02P
J102 J103
1
2
+VBAT
D D
F101 /POWER_EN
POWER_EN
1 3
2 4
+15V_TOP
+15V_BOT
+15V_PFC
GND_TOP
GND_BOT
GND_PFC
+5V_REF
-5V_TOP
-5V_BOT
FUSE AUTO 40A
+5V_D
+5V_A
GNDA
+15V
GND
+VBAT
Battery Charger
L J105 L +VBAT
N +VBAT -VBAT
F102 +15V +15V_TOP
-VBAT
+5V_A +5V_A +5V_D
GNDA /POWER_ON +5V_A -5V_TOP
6.3A/fast GND_TOP
GND
+15V_BOT
GNDA GND GND
F100 HV_BAT_LEVEL -5V_BOT
GND_BOT
IBAT_CONTROL
+15V_PFC
2A/fast GNDA
VBAT
N J106 IBAT
+5V_REF GND_PFC
PFC+Inverter
GNDA
GND
+5V_D
GND_PFC
+5V_A
+15V
+15V_PFC
-5V_TOP
GND_TOP
+15V_TOP
+5V_REF
-5V_BOT
GND_BOT
+15V_BOT
L1
C L2 C
N
PE MH100 PE
PE CONNECTION
PWM_TOP
PWM_BOT J107
GNDA J108
GNDA PWM10 FAN_PWM
GND PWM12
+5V_D
UNI-3 PFC_EN
GND +5V_D TIM14 RLY_IN OUT1
V_DCB_TOP
V_OUT_TOP
V_DCB_BOT
V_OUT_BOT
+5V_A +5V_A TIM15 RLY_BYPASS OUT2 J109
DCB_NEG
+15V
DCB_POS
+15V TIM16 RLY_OUT1 N_OUT
PFC_ZC
FAULT0
FAULT1
TIM17 RLY_OUT2
I_OUT
TEMP
FAN+
DIV1
DIV2
V_IN
DA0
DA1
J110
I_IN
AD2 FAN-
AD3 1
2
AD1
PSH02_02P
AD4 UNI-3_PWM2
J111
AD5 UNI-3_PWM3
AD6 UNI-3_PWM4 1
UNI-3 PHAIS UNI-3_PWM5 2
UNI-3 PHCIS
PSH02_02P
UNI-3 DCBI UNI-3 PFC_EN
UNI-3 DCBV UNI-3 SERIAL
UNI-3 BEMFZCA
B UNI-3 BEMFZCC B
UNI-3 BEMFZCB
UNI-3 PFC_ZC DC-DC Step Up
DA0
Fault1
Fault0
DA1 GND
GND GNDA
GNDA +VBAT DCB_POS
-VBAT +VBAT DCB_NEG
-VBAT
PWM4
PWM5
A A
Motorola MCSL Roznov

1. maje 1009
756 61 Roznov p. R., Czech Republic, Europe
Title
750 VA UPS Power Stage
Author: Pavel Grasblum
Size Schematic Name: 00165_01 Rev
A3 Design File Name: 01
Modify Date: Wednesday, October 01, 2003 Sheet 2 of 10

Copyright Motorola 2003 POPI Status: Motorola General Business
5 4 3 2 1
Figure 7-7. Block Schematic

C201
R201 TP201
+15V_TOP
220
T1 100pF D201 +15V_TOP
12
LL4448 TP209
D202 GND_TOP
+ C202
8z. 100uF/16V BZV55/15V
+15V 1 11
C204 8 +
D203 GND_TOP TP210
C203 -5V_TOP
L201 BZV55/5V1
47nF 100uF/16V
330u 5z. 8z.
7
R202 GND -5V_TOP
2
D204 6 C205
R203 15k R205 TP202
R204 +15V_BOT
U201 D D1
510R
1 8 MMBD914LT1
220 6z. 100pF D205
220
+15V_BOT
R206 COMP VREF
16K 2 VFB VCC 7 R207 5
1
3 6 G
ISENSE OUT Q201 TP211
+ C206 4 5 33 LL4448 D206
RT/CT GND S NTF3055 C208 TR01/MC145 + C207 GND_BOT
330uF/35V BZV55/15V
UC3843 100uF/16V
R209
2
R208 C209 100pF
N/P 1k
100nF + C210 GND_BOT TP212
C211 R210 D207
C212 100uF/16V -5V_BOT
100pF 1.8 BZV55/5V1
100pF
GND GND GND GND GND GND GND -5V_BOT

C213
R211 TP203
220 +15V_PFC
100pF D208 +15V_PFC
LL4448
+ TP213
C214 D209
GND_PFC
100uF/16V BZV55/15V
GND_PFC GND_PFC
+VBAT U202
LM2575-5
TP204 +5V_D
R212 4
1 +5V_D
33k
L202
2
470uH
1
/POWER_EN TP206
R200
5
+ 510 GND
D210 +15V_TOP +15V_TOP
+ MBRA140
C215
2
Q200 C216 220uF/35V GND_TOP
BC846 22uF/50V D211 GND
KA3528LSGT GND_TOP
R213
+5V_A +5V_A POWER_EN -5V_TOP -5V_TOP
100
+5V_REF +5V_REF +15V_BOT +15V_BOT

+5V_D +5V_D GND_BOT

U200 GND_BOT
LM2575-ADJ
+15V +15V TP200 +15V
4 -5V_BOT -5V_BOT
1 +15V
GND L203 L204
2
1
GND 680uH 1u +15V_PFC +15V_PFC
1
R214
GNDA R215 2.4k
3
D213 20K
GND_PFC
GNDA + MBRA140
2
+ GND GNDA GND_PFC
12
C218
22uF/50V R216 C217 D214 GROUND CONNECTION
1.8K 220uF/35V KA3528LSGT
2
GND GND GND GND GND
GND
TP207 TP208
U203 +5V_A Vref
L205 MC78L05ACP +5V_A L200 +5V_REF
+15V 3 VIN VO 1
220uH 220uH
+
GND
+ C221 C200
100nF C220
C219 100nF 22u/20V
22u/20V
2
GNDA GNDA GNDA
Figure 7-8. Auxiliary Power Supplies

5 4 3 2 1
D D
TP300
D301 Vbat
D302 C302 BYW29E-200 29.4V @ Q4 ON
D303 T300 L300
B250R 220uF/450V P6KE200 27.4V @ Q4 OFF
1 13 +VBAT
47uH
+
C301 LINE_OK
R301
4.7nF 68k R302 R303
L
+
1M 9 24k
D304
R304
7 39k
-
1N4148 C303
6 5 R305
D305 R306 220uF/50V 1k8
TR02/MC145 100nF 220uF/50V
N BYV26C 1M R307
+ + 100u/50 +
620
C304 C305 C306

R309
2k4 5.05V @ 39V
VBAT
D
R310
R311 5K6
R312 C315
33k
D300 G 200 100n
C 1N4148 C
R300
L301 0.1 S
7 2 GND_TR
U300 -VBAT
47uH
L Q301
sense
sense
C
ISO300 GND_CH MMBF0201NLT1 GND
CONTROL
1 SFH615A-2
4 1
F X R329 IBAT1 IBAT2
R313
TOP249Y 27R 1K
4 5 3 GNDA
3 2 R314
HV_BAT_LEVEL
100
C316
R315 +
7.5k 100n C307 R308
47uF/10V 3K6
R331
100
R316 R317
220 33K +5V_A D309
100nF 5V1
C300
C309 C308
470nF GND_CH GND
1
R319 Q300 220n
1k6 MC33502 3
B U301B + R318 B
IBAT1 6 -
R320 1 BC847 8
7 2 - 100k
IBAT2 5 U301A U302
100K
+
6
MC33502 TL431ACD
R321 4
1k6 R322
220 GND
C314 R323 R324
N/P GND_CH 1k 1k
IBAT_CONTROL
R325
33K C310 C311
470nF 470nF
GND
4.875V @ 2.34A
IBAT GND
GND
+5V_A +5V_A C312 D307

R327 R328
LINE_OK /POWER_ON
GND 560 68K
10nF/100V BAV103 D
GND
A D308 C313 R330 A
GNDA G
BAV103 10k
100nF/100V
GNDA Q302 S Motorola MCSL Roznov
MMBF0201NLT1 1. maje 1009
Title
GND_TR GND 750 VA UPS Power Stage
Size Schematic Name: Battery Charger Rev
Modify Date: Thursday, August 19, 2004 Sheet 4 of 10

5 4 3 2 1
Figure 7-9. Battery Charger

5 4 3 2 1
GND
J401
GND
GNDA 1 2
D
3 4 D
UNI-3_PWM2 5 6 GND
GNDA 7 8
UNI-3_PWM3
UNI-3_PWM4 9 10
+5V_A +5V_A UNI-3_PWM5 11 12
GND 13 14 +5V_D
+5V_D 15 16
+5V_D +5V_D GNDA 17 18 GNDA
+15V 19 20
UNI-3 DCBV 21 22 UNI-3 DCBI
+15V +15V UNI-3 PHAIS 23 24
UNI-3 PHCIS 25 26
27 28 GNDA
29 30 UNI-3 SERIAL
31 32 UNI-3 PFC_EN
UNI-3 PFC_ZC 33 34 UNI-3 BEMFZCA
UNI-3 BEMFZCB 35 36 UNI-3 BEMFZCC
GNDA 37 38
C 39 40 C
J402
2 1 UNI-3
Fault0
4 3 Fault1
6 5
8 7
10 9 J400
GND +5V
FAULTS HEADER AD1 2 1

AD3 4 3 AD2
AD5 6 5 AD4
8 7 AD6
DA1 10 9 DA0
12 11 +5V_A
GNDA 14 13
B B
ADC and DAC HEADER
J403
2 1
4 3
6 5 PWM10
8 7
10 9 PWM12
12 11
14 13
16 15
18 17 TIM14 Motorola MCSL Roznov
20 19 TIM15 1. maje 1009
22 21 TIM16
A 24 23
756 61 Roznov p. R., Czech Republic, Europe A
TIM17 Title
GND 26 25 750 VA UPS Power Stage
+5V
PWM and Timer HEADER Size Schematic Name: Control Board Interface Rev
A 01
Design File Name:
Modify Date: Wednesday, October 01, 2003 Sheet 5 of 10
5 4 3 2 1
Figure 7-10. Control Board Interface

L501
-OUT
DCB_NEG
650u/1A
D501
680u/50V 680u/50V 680u/50V +Bat 1 2 C501
+VBAT 22n/400V
MUR180
R501
1
C502 + C503 + C504 + C505 + C512 + C513 + 1k/5W
1 2
R502
2
FFPF05U120STU 1k/5W
-VBAT FFPF05U120STU 1 2
680u/50V 680u/50V 680u/50V D500 D502
GND_BAT MUR180
1 2 C506
22n/400V
D504 D505 D503 L502
+OUT
DCB_POS
650u/1A
FFPF05U120STU GND FFPF05U120STU
+15V +15V
13
15
10 18
T500
TR03/MC145
L503 1 9 L500
330u 330u
R503
4
6
100R/1W
1 2
100R/1W
1
47uF R504 47uF
C509 C508 C510
2 1 1n
1 2 1 2
+
+
GND_BAT GND_BAT
2
2
100n C507 GND_BAT 100n
C511 1n C500
1
GND_BAT GND_BAT
GND_BAT
Q501 Q500 Q502 Q503
NTP45N06 NTP45N06 NTP45N06 NTP45N06
6
6
U500 MC33152D U501 MC33152D
1 NC VCC NC 8 D D D D 8 NC VCC NC 1
TP501
PWM_4 TP502
R505 R500
2 InA OutA 7 1 2 G G G G1 2 7 OutA InA 2 PWM_5
10 10
PWM4 S S S S
R506 R507 PWM5
1
1
4 InB OutB 5 1 2 1 2 5 OutB InB 4
R508 R509
10 10
10k 10k
GND GND
2
2
GND_BAT
GND_BAT GND_BAT
GND_BAT GND_BAT
TP503 TP500 TP504

GND_BAT GND GNDA
GND
GND
GNDA
GND_BAT GND
GNDA GNDA
Figure 7-11. dc/dc Step-Up Converter

5 4 3 2 1
+5V_REF I_OUT1 I_OUT2

TP610
I_IN R614
130R
I_IN
R615
100k TP600
4
D614 D615 GNDA I_OUT
D616 D617
MBR0540 MBR0540 2
BZV55/5V1 BZV55/5V1
-
I_IN1 5 + 1 I_OUT
R616 R678 R679 7 1 2 3 +
I_IN2 6 MC33502D
180 180 180 - R600
D U604B U604A D
10
8
C612 R617 MC33502D
D618 D619 10n 100k C613
MBR0540 MBR0540
100n
1
+ C614 GNDA
GNDA GNDA 22uF
2
V_INP GNDA +5V_A
DCB_POS GNDA
+5V_REF +5V_REF
D600
1N4007 C616
R619 100n
300k TP602
R620 TP601 R621
-DCB_DIV GNDA 11k V_OUT_NEG
R618 11k
330k R623 R624
V_DCB_BOT_DIV 1 2 1 2
V_DCB_BOT V_OUT_BOT
R625 1K 0R
300k R626 D620
R627
1
R622 330k C617 330k BZV55/3V6
33n R672
470k
11K
C TP603 C
TP604 R628 R629 R630
2
R631 +DCB_DIV GNDA
V_IN 330k 300k 300k
130k R632
V_DCB_TOP_DIV 1 2 V_DCB_TOP
GNDA GNDA
V_IN 1K
R633 R634 R635
R636 11k C620 300k 300k
33K + C619 33n
10uF/10V V_OUT
R637
GNDA
R638
680k 300k
GNDA DCB_NEG +5V_D
GNDA
GNDA
R639
R640
300k
+5V_D R641 R642 10k
V_DCB_TOP_DIV 5 +
7 FAULT1
10k 10k 6 - TP605
C600 U605B
R643 V_OUT_POS
TP606 LM393D
330k
3
R644 100n
PFC_ZC R645
R646 R647 R648 U606D 10k 1 2 V_OUT_TOP
GNDA
V_INP 10 - V+ 1K
330k 330k 330k 13 PFC_ZC R649 D621
B B
D622 D623 C621 11 + V- 11k BAT42 C622
+5V_REF 33n
BAT42 BAT42 15n
LM339M
12
3
TP607 GNDA GNDA
GNDA R650 REF_POS
10K 2 GNDA
+5V_A +5V_A
+5V_A
1
R651 +5V_D +5V_D
GNDA
+5V_REF
680k
TP608 +15V +15V
R680
Q600 TEMP 33 +5V_D
LM35CA
R652 +5V_REF +5V_REF
+5V_A 3 2 1 2
+Vs +Vout TEMP
3
1K C623
TP609
GND
C624 100n GND

C634 R653 REF_NEG R654
100n C625
8
GND
33n 10K R655 10k
100n 2 3 GNDA
+ GNDA
1
10k 1 FAULT0
2 -
1
U605A GNDA
GNDA GNDA GNDA LM393D
4
A A
GNDA
R656 Motorola MCSL Roznov
V_DCB_BOT_DIV
1. maje 1009
10k
C626 756 61 Roznov p. R., Czech Republic, Europe
GNDA Title
100n 750 VA UPS Power Stage
Size Schematic Name: Analog_Sensing Rev
GNDA Modify Date: Monday, March 08, 2004 Sheet 7 of 10
5 4 3 2 1
Figure 7-12. Analog Sensing Circuits

5 4 3 2 1
D D
U601 +15V_PFC
+15V_TOP +15V_TOP
1 8 D609
R606
C609 GATE_PFC
PWM_PFC 2 7 100nF 10 GND_TOP
MBR0540
R607 D628 GND_TOP
3 6
15V
100 -5V_TOP -5V_TOP
4 5
GND
GND_PFC +15V_BOT +15V_BOT
HCPL3150
GND_PFC
GND_BOT
GATE_TOP GND_BOT
+15V_TOP -5V_BOT -5V_BOT

D611
D624
C D610 15V C
R609 +15V_PFC +15V_PFC
BAT42
C610
R608 100nF 33
MBR0540 D625
PWM_TOP R610 GND_PFC
5V
330 GND_PFC
100
GND_TOP GND
U615
D613 1 16
N/C VCC1 C632
2 15 GND_TOP
ANODE1 VO1 100nF
3 14 GND
CATHODE1 VEE1
BAT42
R611
PWM_BOT 6 11 -5V_TOP
ANODE2 VCC2
330 7 CATHODE2 VO2 10 GATE_BOT
8 N/C VEE2 9
+15V_BOT
HCPL-315J D626
D612 15V
R612
B C611 B
100nF 33
GND MBR0540 D627
R613 5V
100
GND_BOT
C633
100nF
GND_BOT
-5V_BOT

A
1. maje 1009 A
Title
Size Schematic Name: IGBT_Drives Rev
A4 01
Design File Name:
Modify Date: Monday, March 08, 2004 Sheet 8 of 10
5 4 3 2 1
Figure 7-13. PFC and Inverter IGBT Drivers

5 4 3 2 1
RE1
MZPA001
5 o
MBRS130 o 4 OUT1
+15V FAN+
3 o
D601 + C601
FAN-
L504 10u/15V +15V 1 2
D 330u RE2 D
D D1 MZPA001
D602
5 o
R601
FAN_PWM G
o 4
68 Q601 BAT42
S NTF3055
L2 3 o R602
Q602
RLY_OUT1
BC846
4K7
GND +15V 1 2
GND
D603 RE3
I_IN1 I_IN2 MZPA001
BAT42
5 o
R603 o 4 OUT2
7
RLY_BYPASS Q603
CT1 4K7 BC846
3 o
1:100
DCB_POS DCB_POS
V_INP L505 GND +15V 1 2
D604
L1
2
2.5mH
RHRP8120 D605
D606
KBPC606
C BAT42 C
+15V - +
R604 Q604
RLY_OUT2
4K7 BC846
RE4
1
MZPA002 GND
o
Q605
D607 GATE_TOP
BAT42 C602
C603 + HGTG10N120BND
o
V_OUT
2
Q606 MKP10/22nF/630VDC L506

IRG4IBC20W 330uF/450V GND_TOP
GATE_PFC 6mH C604

R605
Q607 C605 2 L507 1 PE
BC846 GND_PFC
4K7
3.3uF/400V 4 3 4.7nF/Y1 C606
TL34P 4.7nF/Y1
GND
RLY_IN N N_OUT
1
2
3
4
CT2
GND GND
B B
CS2106
5
I_OUT2 I_OUT1
Q608
C607 GATE_BOT
+ C608
MKP10/22nF/630VDC 330uF/450V HGTG10N120BND
GND_BOT
D608
+15V +15V
RHRP8120
DCB_NEG DCB_NEG
GND
GND
A A

1. maje 1009
Title
Size Schematic Name: Inverter Rev

5 4 3 2 1
Figure 7-14. PFC and Inverter

5 4 3 2 1
+5V_A
+5V_A
R657
33 +5V_D +5V_D
C627
D 100n R658 R659 R660 C628

D
3
GNDA 10k 10k R661 100n
U606A 10k 470
R663 4 - R662
100 V+ 2 470
DA1 5 + V-
3
LM339M D GND
U606B
12
C629 R664 6 - V+ G
10n 1.6k 1
7 + V-
GNDA Q609 S
R665 GNDA LM339M MMBF0201NLT1
N/P R666
12
DA0
N/P
3
C630 R667 U606C R669 R670 TP611
R668 N/P 8 - 10k 10k GND PWM_PFC
C 100 V+ 14 PFC_CTRL C
0 9
I_IN + V-
C631
LM339M +5V_D
10n
12
GNDA GNDA R671
GNDA 4.7k
D
MMBF0201NLT1 MMBF0201NLT1
60% 75% 85%
3.3K 10k 9.1k
UNI-3 PFC_EN G
Q610 S
MMBF0201NLT1
R673 R674 R675
N/P N/P N/P GND
B B
All On 55% D D
DIV1 G DIV2 G
Q611 S Q612 S
N/P N/P
GNDA GNDA GNDA

1. maje 1009
A A
Title
Author: Ivan Feno
Size Schematic Name: PFC_Control Rev
A4 01
Design File Name:
5 4 3 2 1
Figure 7-15. PFC Current Control Circuit

Application Control
A.2 Schematics of User Interface

5 4 3 2 1
+5V_D
R1
LED_FAULT
SW1
R2 1300
10k D1
L53LID
D BT_BYPASS D
J1
GND
2 1 BEEP
LED_LEV5 4 3 LED_LEV6 R3
LED_LEV3 6 5 LED_LEV4 Switch/P-0SYB LED_ON
LED_LEV1 8 7 LED_LEV2 +5V_D J2
J3 1300
10 9 5
BT_BYPASS 12 11 BT_ON/OFF 9 D2
LED_BAT 14 13 LED_BYPASS 1 2 4 L53LGD
LED_FAULT 16 15 LED_ON 3 4 8
R4
18 17 5 6 3
SW2 10k
20 19 7 8 7
22 21 +5V_D 9 10 2
24 23 6 GND
GND 26 25 BT_ON/OFF 1 R5
LED_BAT
HEADER 5X2 CON/CANNON9
HEADER 13x2 270
C D3 C
L53ND
GND Switch/P-0SEB
2
1
GND
R6 R7
LED_LEV1 J4 LED_BYPASS
PSH02_02W
1300 1300
R8
LED_LEV2 D4
1300 L53LYD
J6 J5
R9
LED_LEV3 5
1300 9
R10 1 2 4
LED_LEV4 3 4 8 GND
5 6 3 BEEP
1300
R11 7 8 7
B LED_LEV5 9 10 2 BZ1 B
1300 6
R12 1
LED_LEV6 HEADER 5X2
CON/CANNON9 SA003
1300
D5 D6 D7 D8 D9 D10
L53LID L53LGD L53LGD L53LGD L53LGD L53LID GND
+5V_D +5V_D
GND
GND

A 1. maje 1009 A
Title
UPS 750 VA User Interface
Size Schematic Name: 00165B01 Rev
Modify Date: Wednesday, September 10, 2003 Sheet 1 of 1
5 4 3 2 1
Figure 7-16. UPS User Interface

Application Control
A.3 Schematics of Input Filter

5 4 3 2 1
D D
4.7nF/Y1 SIOV-S20K275 R100

L J100 J103 L_OUT
C C
TL34P
4 3 SG-190
R103 C100 C100B C101 C102
330k 2 1 R101 R102
L100
N J101 J104 N_OUT

100nF/X1 1uF/X1 100nF/X1 SIOV-S20K275
C103
4.7nF/Y1
J102 MH1 PE
PE
GROUND CONNECTION
B MH2 B
GROUND CONNECTION

1. maje 1009
A 756 61 Roznov p. R., Czech Republic, Europe A
Title
750 VA UPS Input Filter
Size Schematic Name: 00165C01 Rev
A 01
Design File Name:
Modify Date: Monday, September 15, 2003 Sheet 2 of 2
5 4 3 2 1
Application Control
A.4 Parts List of UPS Power Stage

Table A-1. Parts List of UPS Power Stage (Sheet 1 of 5)
Reference Qty Description Manufacturer Part number
current transformer custom
CT1 1 TRONIC 3044202
design
CT2 1 current transformer COILCRAFT CS2106
C200, C209, C221, C303, C308, C610,
9 100-nF ceramic SMD 0805 any available
C611, C632, C633
C201, C205, C208, C211, C212, C213 6 100-pF ceramic SMD 0805 any available
100-F/16-V radial electrolytic
C202, C203, C207, C210, C214 5 any available
5 x 11 mm
C204 1 47-nF ceramic SMD 0805 any available
C206 1 any available
10 x 20 mm
C215, C217 2 any available
10 x 20 mm
C216, C218 2 22-F/50-V 5 x 11 mm any available
C219, C220 2 22-/20-V tantalum size D any available
C300 1 220n ceramic SMD 0805 any available
C301 1 4.7-nF polyester Vishay MKT1820
C302 1 220-F/450-V electrolytic EPCOS B43504
C304, C305 2 220-F/50-V electrolytic Rubycon ZL series
C306 1 100-/50-V electrolytic Jamicon
C307 1 47-F/10-V electrolytic Jamicon
C309, C310, C311 3 470-nF ceramic SMD 0805 any available
C312 1 10-nF/100-V ceramic any available
C313 1 100-nF/100-V ceramic any available
R208, C314, C630, R665, R666, R673,
8 no populated -
R674, R675
C315, C316, C600, C613, C616, C623,
11 100n ceramic SMD 0805 any available
C624, C626, C627, C628, C634
C500, C511 2 100n ceramic SMD 1206 any available
C501, C506 2 22n/400-V metallized WIMA MKP10
C502, C503, C504, C505, C512, C513 6 680/50-V Rubycon ZL series
C507, C508 2 1n/100-V WIMA MKS 2
C509, C510 2 any available
5 x 11 mm
C601 1 10-/15-V tantalum size D any available
C602, C608 2 330-F/450-V electrolytic EPCOS B43504
C603, C607 2 22-nF/630-Vdc WIMA MKP10
C604, C606 2 4.7-nF/Y1 any available
C605 1 3.3-F/400-V WIMA MKP10
C609 1 100-nF ceramic SMD 1206 any available
C612, C629, C631 3 10n ceramic SMD 0805 any available
5 x 11 mm


C617, C620, C622, C625 4 33n ceramic SMD 0805 any available
5 x 11 mm
C621 1 15n ceramic SMD 0805 any available
D201,D205,D208, D304 4 LL4448 signal diode Fairchild LL4448
D202,D206,D209 3 zener diode 15-V Philips BZV55/15V
D203,D207,D616,D617 4 zener diode 5.1-V Philips BZV55/5V1
D204 1 high-speed switching diode ON Semiconductor MMBD914LT1
D210,D213 2 schottky diode ON Semiconductor MBRA140
D211,D214 2 LED diode SMD green Kingbright KA3528SGT
D300 1 high-speed diode Philips 1N4148
D301 1 ultra fast diode Vishay BYW29E-200
Diotec
D302 1 bridge rectifier B250R
Semiconductor
D303 1 transient voltage suppressor Vishay P6KE200
D305 1 ultra fast diode Vishay BYV26C
D307,D308 2 general purpose diode Philips BAV103
D309 1 zener diode 5V1 Philips BZV55/5V1
D500,D502,D504,D505 4 fast recovery diode Fairchild FFPF05U120STU
D501,D503 2 ultra fast diode ON Semiconductor MUR180
D600 1 diode Philips 1N4007
D601 1 schottky diode ON Semiconductor MBRS130
D602,D603,D605,D607,D611,D613,D62
9 schottky diode Philips BAT42
1,D622,D623
D604,D608 2 hyperfast diode Fairchild RHRP8120
Diotec
D606 1 bridge rectifier KBPC606
Semiconductor
D609,D610,D612,D614,D615,D618,D61
7 schottky diode ON Semiconductor MBR0540
9
D620 1 zener diode 3V6 Philips BZV55/3V6
D624,D626,D628 3 zener diode 15 V Philips BZV55/15V
D625,D627 2 zener diode 5.1 V Philips BZV55/5V1
F100 1 fast fuse 2 A any available
F101 1 car fuse 40 A any available
F102 1 fast fuse 6.3 A any available
ISO300 1 optocupler Vishay SFH615A-2
J100,J102,J103,J104,J105,J106,J107,J
9 FASTON
108,J109
J101,J110,J111 3 connector EZK (distributor) PSH02_02P
J400 1 header 7 x 2 any available
J401 1 connector EZK (distributor) PFL_20X2
L200,L205 2 220-H axial inductor 130 mA FASTRON

Application Control

L201,L500,L503,L504 4 330 radial inductor 500 mA FASTRON
L202 1 470 H FASTRON 09P/F-471k
L203 1 680 H FASTRON 09P/F-681k
L204 1 1- axial inductor 1.2 A FASTRON
L300,L301 2 radial inductor 47 H Coilcraft PCV-1-473-03
L501, L502 2 560 / 1 A Coilcraft PCV-2-564-02
L505 1 2.5 mH custom design see 4.5.2.1
L506 1 5 mH custom design see 4.5.4.2
L507 1 toroid choke Tesla Blatna TL34P
Q200, Q602, Q603, Q604, Q607 5 general-purpose bipolar transistor ON Semiconductor BC846
Q201, Q601 2 Power MOSFET transistor ON Semiconductor NTF3055
Q300 1 general-purpose bipolar transistor ON Semiconductor BC847
Q301, Q302, Q609, Q610 4 Power MOSFET transistor ON Semiconductor MMBF0201NLT1
Q500, Q501, Q502, Q503 4 Power MOSFET transistor ON Semiconductor NTP45N06
National
Q600 1 temperature sensor LM35CA
Semiconductor
Q605, Q608 2 IGBT Fairchild HGTG10N120BND
International
Q606 1 IGBT IRG4IBC20W
Rectifier
Q611, Q612 2 no populated
RE1, RE2, RE3 3 relay CARLO GAVAZZI MZPA001
RE4 1 relay CARLO GAVAZZI MZPA002
R200, R203 2 510 SMD 0805 any available
R201, R204, R205, R211, R316, R322 6 220 SMD 0805 any available
R202 1 15k SMD 0805 any available
R207, R657, R680 3 33 SMD 0805 any available
R209, R323, R324, R329, R623, R632,
8 1k SMD 0805 any available
R645, R652
R210 1 1.8 SMD 0805 any available
R212, R317, R325 3 33k SMD 0805 any available
R213, R314, R331, R663, R668 5 100 SMD 0805 any available
R214 1 2.4k SMD 0805 any available
Isabellenhtte
R300 1 precision shunt resistor PMA-C - R100 - 1
Heusler GmbH KG
R301 1 68k, 2W any available
R302, R306 2 1M size 0207 any available
R305 1 1k8 SMD 0805 any available
R307 1 620 SMD 0805 any available
R308 1 3K6 SMD 0805 any available


R310 1 5K6 SMD 0805 any available
R311, R636 2 33k, size 0207 any available
R313 1 27R SMD 0805 any available
R318, R320, R615, R617 4 100k SMD 0805 any available
R319, R321 2 1k6 SMD 0805 any available
R330, R508, R509, R640, R641, R642,
R644, R654, R655, R656, R658, R659, 15 10k SMD 0805 any available
R660, R669, R670
R500, R505, R506, R507, R606 5 10 SMD 1206 any available
R501, R502 2 1-k/5-W any available
R503, R504 2 100R/1W any available
R602, R603, R604, R605 4 4K7 SMD 0805 any available
R614 1 130RSMD 0805 any available
R618, R626, R627, R628, R643, R646,
8 330k size 0207 any available
R647, R648
R619, R625, R629, R630, R634, R635,
8 300k size 0207 any available
R638, R639
R620, R621, R633, R649, R672 5 11k SMD 0805 any available
R622 1 470k size 0207 any available
R624, R667 2 0R SMD 0805 any available
R631 1 130k size 0207 any available
R637, R651 2 680k SMD 0805 any available
T1 1 transformer customer design see 4.3.1
T300 1 transformer customer design see 4.2.4
T500 1 transformer customer design see 4.4.2.1
U200 1 switching regulator ON Semiconductor LM2575-ADJ
U201 1 switching regulator ON Semiconductor UC3843
U202 1 switching regulator ON Semiconductor LM2575-5

Application Control

U203 1 linear regulator ON Semiconductor MC78L05ACP
U300 1 switching regulator Power Integrations TOP249Y
U301, U604 1 operational amplifier ON Semiconductor MC33502
U302 1 voltage reference Fairchild TL431ACD
U500,U501 2 MOSFET driver ON Semiconductor MC33152D
U601 1 opto driver Agilent HCPL3150
U605 1 dual comparators ON Semiconductor LM393D
U606 1 quad comparators ON Semiconductor LM339M
U615 1 opto driver Agilent HCPL-315J
A.5 Parts List of User Interface

Table A-2. Parts List of User Interface
BZ1 1 buzzer EZK (distributor) SA003
D1, D10 3 LED diode red Kingbright L53LID
D2,D5,D6,D7,D8,D9 6 LED diode green Kingbright L53LGD
D3 1 LED diode orange Kingbright L53ND
D4 1 LED diode yellow Kingbright L53LYD
J2,J5 2 connector CANNON 9 pin any available
J3,J6 2 header 5 x 2 any available
J4 1 connector any available
R1, R3, R6, R7, R8, R9, R10, R11, R12 9 1300 SMD 0805 any available
switch 15501
SW1 1 Switch MEC extender 16250
cap 1D06
switch 15501
SW2 1 Switch MEC extender 16250
cap 1D02

A.6 Parts List of Input Filter

Table A-3. Parts List of Input Filter
C100B 1 1F / X1 EPCOS B81133
C100, C101 2 100-nF / X1 EPCOS B81133
C102, C103 2 4.7-nF / Y1 MURATA DE2E3KH472MA3B
J100,J101,J102,J103,J104 5 faston 6.3 mm any available
L100 1 toroid choke Tesla Blatna TL34P
Rhopoint
R100 1 inrush current limiter SG-190
Components
R101, R102 2 EPCOS SIOV-S20K275
R103 1 330k, 0.6 W any available

Application Control
Appendix B. References
1. Feno, I.: Analysis and Synthesis of the IGBT switching techniques and verification in Partial Series
Resonant Converter. Ph.D. Dissertation, University of Zilina, Faculty of Electrical Engineering,
August 2003.
2. A More Realistic Characterization Of Power MOSFET Output Capacitance Coss. Application Note
AN-1001, International Rectifier.
3. Billings, K.: Switchmode Power Supply Handbook, second edition. McGraw-Hill, 1999.
4. Pressman, A. I.: Switching Power Supply Design, second edition, McGraw-Hill, 1998.
5. International Standard IEC62040-1-1, Uninterruptable power systems (UPS) - Part 1-2: General
and safety requirements for UPS used in operator access areas.
6. International Standard IEC62040-1-2, Uninterruptable power systems (UPS) - Part 1-2: General
and safety requirements for UPS used in restricted access locations.
7. International Standard IEC62040-2, Uninterruptable power systems (UPS) - Part 2:
Electromagnetic compatibility (EMC) requirements.
8. International Standard IEC62040-3, Uninterruptable power systems (UPS) - Part 3: Method of
specifying the performance and test requirements.
9. YUASA NP valve regulated lead acid battery manual. Yuasa Battery GMBH, 1999.
10. TOP242-250 Up to 290 W Extended power, design flexible, EcoSmart, integrated off-line switcher
family, data sheet. Power Integrations, August 2003
11. AN-18, TOPSwitch Flyback Transformer Construction Guide. Power Integrations, 1996.
12. AN-16, TOPSwitch Flyback Design Methodology. Power Integrations, 1996.
13. MC9S12E-Family Device User Guide, data sheet. Motorola, 2003.
14. HCS12 CPU V2.0 Reference Manual, Reference Manual. Motorola, 2003.
15. HCS12 10-Bit, 16-Channel Analog to Digital Converter (ATD) Block Guide. Reference Manual.
Motorola, 2003.
16. HCS12 Background Debug Module Block Guide. Reference Manual. Motorola, 2003.
17. HCS12 Clocks and Reset Generator (CRG) Block Guide. Reference Manual. Motorola, 2003.
18. Digital-to-Analog Converter: 8-Bit, 1-Channel. Reference Manual. Motorola, 2003.
19. Debug Module. Reference Manual. Motorola, 2003.
20. Port Integration Module: 9S12E128. Reference Manual. Motorola, 2003.
21. HCS12 128K FLASH Block Guide. Reference Manual. Motorola, 2003.
22. HCS12 Inter-Integrated Circuit (IIC) Block Guide. Reference Manual. Motorola, 2003.
23. Interrupt (INT) Module V1 Block User Guide. Reference Manual. Motorola, 2003.
24. Multiplexed External Bus Interface (MEBI) Module V3 Block User Guide. Reference Manual.
Motorola, 2003.
25. Module Mapping Control (MMC) V4 Block User Guide. Reference Manual. Motorola, 2003.
26. HCS12 Oscillator Block Guide. Reference Manual. Motorola, 2003.
27. Pulse Modulator with Fault Protection: 15-Bit, 6-Channel. Reference Manual. Motorola, 2003.
28. HCS12 8-Bit, 6-Channel Pulse Width Modulator (PWM) Block Guide. Reference Manual. Motorola,
2003.
29. HCS12 Serial Communications Interface (SCI) Block Guide. Reference Manual. Motorola, 2003.
30. HCS12 Serial Peripheral Interface (SPI) Block Guide. Reference Manual. Motorola, 2003.
31. Timer: 16-Bit, 4-Channel. Reference Manual. Motorola, 2003.
32. Voltage Regulator 3V3 Block User Guide V2. Reference Manual. Motorola, 2003.
33. MC9S12E128 Controller Board, Design Reference Manual, Motorola 2004


Application Control
Appendix C. Glossary
ac alternating current
ac/dc converter a converter that converts alternating voltage (ac) to direct voltage (dc)
ATD analog-to-digital converter
A/D analog-to-digital
AVR automatic voltage regulation
CW CodeWarrior; compilers produced by Metrowerks
DAC digital-to-analog converter
dc direct current
dc/ac converter a converter that converts direct voltage (dc) to alternating voltage (ac)
dc/dc converter converter that converts one level of direct voltage to another level of direct voltage
DT dead time; a short time that must be inserted between turning off one transistor in the
inverter half-bridge and turning on the complementary transistor, to allow for the
limited switching speed of the transistors.
duty cycle the ratio of the time the signal is on to the time it is off. Duty cycle is usually quoted
as a percentage.
EMC electro magnetic compatibility
EMI electro magnetic interference
IC integrated circuit
IDE integrated development environment
IGBT Insulated gate bipolar transistor
input/output (I/O) input/output interfaces between a computer system and the external world. A CPU
reads an input to sense the level of an external signal and writes to an output to
change the level on an external signal.
interrupt a temporary break in the sequential execution of a program to respond to signals
from peripheral devices by executing a subroutine.
logic 1 a voltage level approximately equal to the input power voltage (VDD)
logic 0 a voltage level approximately equal to the ground voltage (VSS)
HCS12 a Freescale Semiconductor family of 16-bit MCUs
MCU microcontroller unit; a complete computer system, including a CPU, memory, a clock
oscillator, and input/output (I/O) on a single integrated circuit

MW Metrowerks Corporation
PC personal computer
PCB printed circuit board
PCM PC master software for communication between PC and system
PFC power factor correction
PI Controller proportional-integral controller
PID Controller proportional-integral-derivative controller
PLL phase-locked loop; a clock generator circuit in which a voltage controlled oscillator
produces an oscillation that is synchronized to a reference signal
PMP FreeMaster software project file
PVAL PWM value register of motor control PWM module of the MC9S12E128
microcontroller; it defines the duty cycle of the generated PWM signal.
PWM pulse width modulation
RESET to force a device to a known condition
RMS root mean square
SCI serial communications interface module; a module that supports asynchronous
communication
SMPS switched mode power supply
software instructions and data that control the operation of a microcontroller
SPI serial peripheral interface module; a module that supports synchronous
communication
SWI software interrupt; an instruction that causes an interrupt and its associated vector
fetch
THD total harmonic distortion
timer A module used to relate events in a system to a point in time
UPS uninterruptable power supply

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Single Phase On-Line

UPS Using MC9S12E128

Designer Reference Manual

by: Ivan Feno, Pavel Grasblum and Petr Stekl

09/2004 0 Initial release N/A

Single Phase On-Line UPS Using MC9S12E128

Single Phase On-Line UPS Using MC9S12E128

4.5.1 PFC Booster Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Single Phase On-Line UPS Using MC9S12E128

Single Phase On-Line UPS Using MC9S12E128

Single Phase On-Line UPS Using MC9S12E128

1-1 Passive Standby UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Single Phase On-Line UPS Using MC9S12E128

5-2 Application State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Single Phase On-Line UPS Using MC9S12E128

2-1 On-Line UPS Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Single Phase On-Line UPS Using MC9S12E128

Freescale Semiconductor Freescale Semiconductor Internal Use Only 11

Draft For Review - September 30, 2004

Single Phase On-Line UPS Using MC9S12E128

12 Freescale Semiconductor Internal Use Only Freescale Semiconductor

Draft For Review - September 30, 2004

1.1 Application Outline

1.2 UPS Topologies and Features

Single Phase On-Line UPS Using MC9S12E128

1.2.1 Passive Standby UPS Topology

Single Phase On-Line UPS Using MC9S12E128

1.2.2 Line-Interactive UPS Topology

LINE FILTER AVR

Single Phase On-Line UPS Using MC9S12E128

1.2.3 On-Line UPS Topology

Single Phase On-Line UPS Using MC9S12E128

1.3 MC9S12E128 Advantages and Features

Single Phase On-Line UPS Using MC9S12E128

Single Phase On-Line UPS Using MC9S12E128

2.1 System Concept

Figure 2-1. System Concept of UPS

Single Phase On-Line UPS Using MC9S12E128

Figure 2-2. UPS Power Stage

Figure 2-3. Input Filter

Single Phase On-Line UPS Using MC9S12E128

Figure 2-4. User Interface

Figure 2-5. MC9S12E128 Controller Board

Single Phase On-Line UPS Using MC9S12E128

Figure 2-6. Overall View of the UPS Demo

2.2 System Specification

Single Phase On-Line UPS Using MC9S12E128

Table 2-1. On-Line UPS Specification

Single Phase On-Line UPS Using MC9S12E128

Single Phase On-Line UPS Using MC9S12E128

3.1 Control Techniques

3.1.1 Battery Charger Control

Single Phase On-Line UPS Using MC9S12E128

Charging Current Limit

AN02 Battery current

Figure 3-1. Battery Charger Algorithm

Single Phase On-Line UPS Using MC9S12E128

3.1.2 Power Factor Correction Control

IOC04 Zero Cross

F AN07 Top DC Bus Voltage

Figure 3-2. PFC Control Algorithm

Single Phase On-Line UPS Using MC9S12E128

Figure 3-3. Hysteresis Control of Input Current

3.1.3 dc/dc Step-Up Converter Control