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Fully Depleted SOI

Designed for low power
Edited Xavier Cauchy-For The SOI Industry Consortium

FULLY DEPLETED SOI is a CMOS silicon technology specifically

designed to operate at very low power while maximizing
performance, manufacturability and reducing the overall cost.

Our Mobile Customers have given us a clear message:

A Balance of Power-Performance, Cost, and Form Factor is critical to

Smart Mobile SOC
Low Power Does Not Mean Low Performance
Battery life between recharge is a critical determinant of user
experience

This White Paper will address :

- Technology Attributes and Implementation Requirements (H.Mendez, SOI Consortium)

- Best CMOS Device for 20nm Low Power Multimedia Applications (T.Skotnicki, STMicro)
- Threshold Voltage in FD-SOI:
Variability Advantage; VT modulation for Low Power (O. Faynot, CEA-LETI)
- FD-SOI Substrate Volume Production (C.Mazure, Soitec)

SOI Industry Consortium | Fully Depleted SOI technology | December 2010 Horacio Mendez Executive Director Page 1/8
Technology Attributes and Implementation Requirements
By Horacio Mendez, Director of the SOI Industry Consortium
Derived from Questions and Answers on Fully Depleted SOI Technology for next generation CMOS,
by X Cauchy (Soitec) and F Andrieu (Leti)
www.soiconsortium.org/pdf/fullydepletedsoi/SOIconsortium_FDSOI_QA.pdf

As the power consumption demands on silicon technology increase exponentially, one thing is clear:
The current path has reached its capability to support it.

At 22nm and below, traditional CMOS on Bulk silicon is highly inefficient to meet the demands of Smart Mobile
Devices. This is because current Bulk planar transistors have reached the physical limit in controlling leakage
current and lack of ability to reduce the operating voltage or dynamic power without compromising performance,
a major source of wasted battery power. T Skotnicki, in this paper, reviews why FD-SOI is a winning option.

Illustration: courtesy ST

Technology attributes
FD-SOI solves, with less process complexity, scaling, leakage and variability issues to further shrink CMOS
technology.
Planar Fully Depleted Silicon on Insulator (FD-SOI) technology relies on an ultra-thin layer of silicon over a
Buried Oxide (commonly called BOx). CMOS transistors built into this top silicon layer are Ultra-Thin Body
devices and have unique, extremely attractive characteristics. Two flavors of buried oxide can be used: standard
thickness (typically 145nm thick as classically in volume production high performance digital chips today which
employ Partially-Depleted SOI), or ultra-thin BOx, for example 10 or 25nm (UTBOx, Ultra-Thin Buried Oxide).
From a physical point of view, the very thin silicon layer enables the silicon under the transistor gate (the body of
the transistor) to be fully depleted of charges.

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FD-SOI Transistors vs. Bulk and PD-SOI Transistors

FD-SOI Starting Wafer

The physical laws that rule the FD-SOI transistor architecture lead to the following key advantages for this
technology:

The excellent electrostatic control of the transistor, intrinsic to FD-SOI, acts as a performance booster and
enables lower VDD (therefore lower power consumption) whilst reaching remarkable performance,
FD-SOI strongly reduces the random dopant fluctuation, thus drastically cutting transistor threshold (VT)
variability. In particular, this enables stable, dense, and high-yielding SRAM, functional at very low VDDmin
(even in near- or sub-threshold mode with a good SNM),
FD-SOI is intrinsically Low Leakage and regains good control of Short Channel Effects.
One consequence is the ability to aggressively shrink the gate length, making it easier to fit devices into
smaller and smaller pitches and therefore increase logic density to continue Moores law.

In addition, FD-SOI transistors (which require no halo/pocket implant) natively offer superior analog behavior.
This comes with other classical advantages of SOI like much-improved Soft-Error Rate, etc.

Cost and Manufacturability Considerations

FD-SOI efficiently solves the equation: Cost of Ownership (CoO) of the finished Integrated Circuit vs. power,
performance, area and manufacturability requirements at the next technology nodes. Some key aspects of the
FD-SOI technology (e.g. regarding process complexity, SRAM area/yield trade-off, etc.) have a beneficial impact
on the CoO. In addition, optimization programs at SOI wafer manufacturers like Soitec are significantly lowering
the cost of SOI as a starting material. It is also worth keeping in mind that the contribution of the finished wafer
cost to the final CoO of an IC is mitigated by other important die-level aspects like cost of IC packaging, etc.

Specifically, benefits of FD-SOI that have an impact on CoO include:

Simplicity of the CMOS fabrication process (reduction in number of masks and process steps).
Plus, lower complexity factor leads to faster yield learning and improved time-to-volume for SoC
products.
Favorable area vs. stability and yield trade-off for SRAMs,
Less design sign-off margins required, owing to reduced variability,

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 Ability to scale gate length aggressively (benefit of low Short Channel Effects) leading to better logic
density and/or less difficulties to fit into a target transistor pitch,
Potentially lower packaging and cooling cost, owing to lower power dissipation needs, etc.

Factoring in these aspects with starting wafer cost and die level costs, the Cost of Ownership of FD-SOI
based ICs is expected to be extremely competitive vs. a (virtual) Bulk counterpart while offering a superior
power/performance/area/manufacturability trade-off in view of the target applications.

Scalability and Integration

All indications are that FD SOI is scalable through multiple generations on technology. Leading papers (VLSI and
IEDM conferences) have shown FD-SOI to be scalable down to the 10nm node, based on projected
requirements in terms of thickness and uniformity of top silicon and BOx for next nodes compared to current
quality of FD-SOI wafers.
Integration of Analog and I/O transistors, with different gate oxides, has been demonstrated on FD-SOI with very
good performance. Regarding non-transistor devices : most of them can be ported to ultra-thin SOI either directly
or with minor adaptations. There is also the option to keep devices on Bulk if wished, by locally etching off the
ultra-thin silicon film and ultra-thin buried oxide.
An alternative candidate transistor architecture to solve the significant scaling challenges of CMOS is FinFET,
which is a vertical rather than planar structure, where the gate wraps around a tall fin. Although very interesting,
FinFET technology is much more challenging in terms of fabrication process and more disruptive at
manufacturing level and at design level.

Implementation requirements
There are essentially no specificities to design on FD-SOI. Design will rely on the same flows as Bulk, updated to
integrate FD-SOI-capable SPICE compact models. Note that FD-SOI does not exhibit the Floating Body Effect
and is free of peculiarities such as history effect (also know as the 1st/2nd switch effect) and kink effect. This
makes the porting of designs from bulk to FDSOI very direct.
Overall, developing an FD-SOI design ecosystem for the 22/20nm node is a fairly transparent task, because FD-
SOI and traditional Bulk design flows are essentially identical.
Additionally, all low power techniques currently employed in classical Bulk CMOS technology can be directly
ported to FD-SOI. One special case is Body Biasing, which can be very efficiently adapted to FD-SOI in the form
of back-plane biasing, using ultra-thin BOx wafers. Besides, VT adjustments are no longer done via doping
adjustments as FD-SOI requires no channel doping (which is very advantageous to solve variability concerns).
Olivier Faynot, in this paper, reports on solutions.

FDSOI design as simple as BULK!!

ARM
FDSOI Workshops Tokyo, Sept. 2010 San Francisco, Dec. 2010

Conclusion
End Products:
FD-SOI brings Low Power and High Performance. Ideal fit with Smart Mobile Applications.
Design and System-on-Chip Architecture:
Continuity of tools and methodologies used on Bulk CMOS.
Technology:
Solves major roadblocks to further shrink CMOS. Non-disruptive planar approach.
Cost of ownership:
Very competitive position on the Consumer IC market.

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Best CMOS Device for 20nm Low Power Multimedia Applications
By Thomas Skotnicki, Fellow and Director of Advanced Devices,STMicroelectronics.
Three flavors in CMOS technologies appeared in response to the impossibility of having Low dynamic Power
(LP), High Performance (HP) and Low Static Power (LSTP) in one. But the rapidly growing Mobile market
pushes us to reconsider this division. The applications such as smart-phones, -PC, tablets, etc, actually require
all three features at the same time. This is impossible with conventional Bulk technologies, today even more than
it was when the three technology flavors were introduced. It is so because today the Bulk MOSFET is running
out of steam. As summarized in the figure below, all traditional speed boosters are not productive any more.

Therefore non-classical device structures (such as FDSOI, FinFET or Nanowires) are seriously considered as
Bulk challengers. Why should they offer more than Bulk ? First of all because they present a much improved
electrostatic integrity with respect to Bulk. The common understanding has been that better electrostatics leads
to reduced leakages and therefore advantages this kind of structures for LSTP applications. This is very much
true, but recently it has been shown that reduced DIBL is also the speed booster, especially when speaking of
LP technologies.
FDSOI offers similar improvement in terms of electrostatics as FinFET and Nanowires, but in addition to that it
offers a very efficient body biasing. This is a very unique feature of FDSOI that is reinforced in case of thin box.
This kind of FDSOI structures called UTBB (Ultra Thin Body and BOX) are cumulating benefits in terms of speed
from both the improved electrostatics and from the forward body biasing. Consequently, if we benchmark the
different technologies in the frame of 20nm LP, the winning solution definitely goes to UTBB SOI. This is shown
in the figure below. Therefore, we believe that the expansion of the multimedia portable electronics will require
FDSOI technology to suit the needs of this kind of applications and bring to this market the best the technology
can offer today.

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Threshold Voltage (VT) in FDSOI: Variability Advantage; Multi-VT and VT modulation
for Low Power
By Olivier Faynot, Director, Innovative Device Laboratory, CEA-Leti

Variability
Due to the reduction of Random Dopant Fluctuations, the use of undoped devices is a significant advantage for
the variability control. Fig.1 reports the benchmarking of the variability recent published data: planar FDSOI
exhibits the best performance compared to Bulk technologies. Global variability is also reduced and Fig.2 reports
the required SOI film thickness non-uniformity to keep a global variability at 3% of VDD as required in the ITRS
roadmap. It has to be noted that already existing SOI wafers are already fulfilling these specifications, meaning
that SOI wafer uniformity is not an issue for this technology.
Lower variability, characterized by the Avt parameter, offers the capability to operate at lower voltage as shown
in Fig. 3, which drives technology scaling and significant reduction in active and leakage power.

Fig.1: Variability benchmarking Fig.2: SOI film thickness uniformity required

for various gate length

Fig. 3: Capability to operate at lower voltage due to lower variability (Avt)

Courtesy: ST Microelectronics

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Multiple VT aspects with FDSOI and Low Power techniques
With undoped channel devices, new solutions are required to offer multi-VT options, since the VT tuning has to be
ensured without channel doping adjustment. The gate material workfunction becomes the main factor that
adjusts the VT value. With thick buried oxide wafers, the use of Mid-gap and Quarter gap metals is mandatory to
achieve both Standard, High and Low VT devices (SVT, HVT and LVT respectively). The use of UTBOX wafers
with a Ground-Plane doping (GP) extends dramatically the possible VT values and reduces the complexity as it
becomes possible to achieve 3 various VTs with only 2-quarter gap metals. Very good values of the Back bias
effect are obtained with UTBOX and it is found that, contrary to Bulk devices, the Back-bias coefficient is not
degraded during the gate length downscaling. This is due to the excellent electrostatic performance. This
enables the use of the Low Power design techniques. Back bias effect of 80mV/V are obtained with a TBOX of
25nm, allowing the modulation of the OFF-state leakage current (Fig.5).

Fig.4: Multiple VT options with thick and thin BOX Fig.5: IOFF leakage modulation with Back
bias for Low Power operation

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FD-SOI Substrate Volume Production
By Carlos Mazur, Chief Technology Officer, Soitec

At wafer level the starting ultra thin Si thickness (FD SOI) has to be matched to the subsequent FD CMOS
processing. Cleans, sacrificial oxidations remove a few Si monolayers of the SOI layer and it has to be taken into
account when specifying the initial ultra thin SOI thickness TSi. The targeted channel Si thickness is typically
between 5nm 7nm, the starting SOI thickness is typically 10nm 15nm.
The SOI thickness is coupled to the VT of the FDSOI device, thus SOI uniformity is a key parameter to avoid
substrate induced VT variability. Uniformity requirements include on-wafer uniformity and wafer-to-wafer
uniformity. Both of them combined are classified as layer total thickness variation (LTTV) and define the overall
manufacturing process window for thickness uniformity. LTTV has to be achieved at the nanometer or sub-
nanometer range for the UTSOI layer for all wafers and all sites in order to meet the FD specifications. The
thickness variation of UTSOI has a direct impact on the device characteristics. Published data of measured VT as
a function of TSi, empirically result in 25mV/nm. From circuit and device considerations the maximum TSi
fluctuation that can be tolerated is 5 with-in-wafer (WiW), total wafer range of the TSi non uniformity, and wafer-
to-wafer (WtW) TSI reproducibility.
Typical WiW TSi range (7 sigma) for 300mm substrates for a target TSi of 12nm is 8-9. UTSOI thickness is
measured by UV ellipsometry to avoid interference of the underlying substrate. Best values for WiW range being
around 6. Fig. 1 shows typical total thickness variation values over a large wafer population.
Thin BOX (<50nm) suppresses the lateral electrostatic coupling between source, drain and channel of the
transistor through the thick BOX. The BOX thickness reduction to 10nm 25nm improves the scalability of the
FDSOI device at almost constant channel silicon thickness down to LG=10nm which corresponds to the targeted
gate length for node 11nm.

Figure 1. Measured TSi total thickness variation for a large wafer population. Target TSi=15nm, total range is 1nm
(min-max).

The BOX thickness TBOX and silicon thickness TSi are independent parameters for the SOI fabrication and can
therefore be adjusted without degrading the properties of the top silicon layer. The oxide quality of ultra thin BOX
10 -2 -1
is very similar to the quality of equivalent gate oxides. The density of interface states is typically 5x10 cm eV
for both BOX interfaces. Intrinsic breakdown for 10nm BOX is typically of 12.5 MV/cm.
Continuous improvement of FD SOI substrate capability for SOI thickness allows for a Wafer-to-Wafer (WtW)
distribution of maximum 5. The target for High Volume Manufacturing (HVM) phase in 2012 is 2.
Main UTSOI substrate development focus is the improvement of the short-range surface roughness. The
improvement achieved through the optimization of the splitting process and surface finishing of the Smart Cut
technology result in 2 RMS roughness measured by AFM in 30x30m scans. At the inspection scale of 2x2
2
m AFM scans, results show that UTSOI and polished bulk silicon surface both exhibit a RMS close to 1.5 .
The volume manufacturing for UTSOI is planed to ramp up in 4Q of 2011. This FD substrate product roadmap
meets the timelines of the 20nm technology platform ramp up.

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