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ADS1278
www.ti.com SBAS367F JUNE 2007 REVISED FEBRUARY 2011
1FEATURES DESCRIPTION
Simultaneously Measure Four/Eight Channels
234
VREFP VREFN AVDD DVDD IOVDD VREFP VREFN AVDD DVDD IOVDD
ADS1274 ADS1278
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 PowerPAD is a trademark of Texas Instruments, Inc.
3 SPI is a trademark of Motorola, Inc.
4 All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. 20072011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS1274
ADS1278
SBAS367F JUNE 2007 REVISED FEBRUARY 2011 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or visit the device product folder at www.ti.com.
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
ELECTRICAL CHARACTERISTICS
All specifications at TA = 40C to +105C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V,
VREFN = 0V, and all channels active, unless otherwise noted.
ADS1274, ADS1278
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Full-scale input voltage (FSR (1)) VIN = (AINP AINN) VREF V
Absolute input voltage AINP or AINN to AGND AGND 0.1 AVDD + 0.1 V
Common-mode input voltage (VCM) VCM = (AINP + AINN)/2 2.5 V
High-Speed mode 14 k
High-Resolution mode 14 k
Differential input impedance
Low-Power mode 28 k
Low-Speed mode 140 k
DC PERFORMANCE
Resolution No missing codes 24 Bits
fCLK = 37MHz 144,531 SPS (3)
High-Speed mode (2) fCLK = 32.768MHz 128,000 SPS
fCLK = 27MHz 105,469 SPS
Data rate (fDATA)
High-Resolution mode 52,734 SPS
Low-Power mode 52,734 SPS
Low-Speed mode 10,547 SPS
Integral nonlinearity (INL) (4) Differential input, VCM = 2.5V 0.0003 0.0012 % FSR (1)
Offset error 0.25 2 mV
Offset drift 0.8 V/C
Gain error 0.1 0.5 % FSR
Gain drift 1.3 ppm/C
High-Speed mode Shorted input 8.5 16 V, rms
High-Resolution mode Shorted input 5.5 12 V, rms
Noise
Low-Power mode Shorted input 8.5 16 V, rms
Low-Speed mode Shorted input 8.0 16 V, rms
Common-mode rejection fCM = 60Hz 90 108 dB
AVDD 80 dB
Power-supply rejection DVDD fPS = 60Hz 85 dB
IOVDD 105 dB
VCOM output voltage No load AVDD/2 V
(9) fCLK = 37MHz max for High-Speed mode, and 27MHz max for all other modes. See Table 7 for DVDD restrictions in High-Speed mode.
AINN5(1)
AINN6(1)
AINP5(1)
AINP6(1)
VREFN
VREFP
VCOM
AINN3
AINN4
AINP3
AINP4
AGND
AGND
AGND
AVDD
AVDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AINP2 1 48 AINN7(1)
AINN2 2 47 AINP7(1)
AINP1 3 46 AINN8(1)
AINN1 4 45 AINP8(1)
AVDD 5 44 AVDD
AGND 6 43 AGND
DGND 7 42 PWDN1
TEST0 8 41 PWDN2
ADS1274/ADS1278
TEST1 9 40 PWDN3
CLKDIV 10 39 PWDN4
SYNC 11 38 PWDN5(1)
DIN 12 37 PWDN6(1)
DOUT8(1) 13 36 PWDN7(1)
DOUT7(1) 14 35 PWDN8(1)
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DOUT1
FORMAT1
DGND
IOVDD
IOVDD
DGND
DGND
DVDD
DOUT3
DOUT2
FORMAT2
DRDY/FSYNC
FORMAT0
DOUT4
CLK
SCLK
(1) Boldface pin names indicate additional pins for the ADS1278; see Table 1.
tCLK
tCPW
CLK
tCD tCPW
tCONV
DRDY
tCLK tCPW
CLK
tCS tCPW
tFRAME
TYPICAL CHARACTERISTICS
At TA = +25C, High-Speed mode, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, and
VREFN = 0V, unless otherwise noted.
OUTPUT SPECTRUM OUTPUT SPECTRUM
0 0
High-Speed Mode High-Speed Mode
-20 fIN = 1kHz, -0.5dBFS -20 fIN = 1kHz, -20dBFS
32,768 Points 32,768 Points
-40 -40
Amplitude (dB)
Amplitude (dB)
-60 -60
-80 -80
-100 -100
-120 -120
-140 -140
-160 -160
10 100 1k 10k 100k 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)
Figure 1. Figure 2.
-40
Amplitude (dB)
-60
15k
-80
-100
10k
-120
-140 5k
-160
-180 0
-35
-28
-21
-14
-7
14
21
28
35
1 10 100 1k 10k 100k
Frequency (Hz) Output (mV)
Figure 3. Figure 4.
Amplitude (dB)
-60 -60
-80 -80
-100 -100
-120 -120
-140 -140
-160 -160
10 100 1k 10k 100k 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)
Figure 5. Figure 6.
Number of Occurrences
Amplitude (dB)
-60
15k
-80
-100
10k
-120
-140 5k
-160
-180 0
-17.5
-10.5
-3.5
3.5
10.5
17.5
-24.5
-21.0
-14.0
-7.0
7.0
14.0
21.0
24.5
1 10 100 1k 10k 100k
Frequency (Hz)
Output (mV)
Figure 7. Figure 8.
Amplitude (dB)
-60 -60
-80 -80
-100 -100
-120 -120
-140 -140
-160 -160
10 100 1k 10k 100k 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)
-60
15k
-80
-100
10k
-120
-140 5k
-160
-180 0
-21
-11
11
21
-32
32
-37
-5
37
0
-26
-16
16
26
Amplitude (dB)
-60 -60
-80 -80
-100 -100
-120 -120
-140 -140
-160 -160
1 10 100 1k 10k 1 10 100 1k 10k
Frequency (Hz) Frequency (Hz)
-60
15k
-80
-100
10k
-120
-140 5k
-160
-180 0
-35
-28
-21
-14
-7
14
21
28
35
0.1 1 10 100 1k 10k
Frequency (Hz) Output (mV)
-40 -40
-60 -60
-80 -80
THD+N THD+N
-100 -100
-60 -60
-80 -80
THD+N
-100 -100 THD+N
-140 -140
10 100 1k 10k 100k -120 -100 -80 -60 -40 -20 0
Frequency (Hz) Input Amplitude (dBFS)
-40 -40
-60 -60
-80 -80
THD+N
-100 -100 THD+N
THD
-120 THD -120
-140 -140
10 100 1k 10k 100k -120 -100 -80 -60 -40 -20 0
Frequency (Hz) Input Amplitude (dBFS)
-40 -40
-60 -60
-80 -80
THD+N
-100 -100 THD+N
THD THD
-120 -120
-140 -140
10 100 1k 10k -120 -100 -80 -60 -40 -20 0
Frequency (Hz) Input Amplitude (dBFS)
Number of Occurrences
300
600
250
500
200
400
150
300
100
200
50 100
Outliers: T < -20C
0 0
-11
-1
1
11
-1
-13
-12
-3
-2
2
3
12
13
-15
-5
15
-10
-8
-9
8
10
-7
7
9
-14
-6
-4
4
6
14
-3
-2
2
3
-5
5
-10
-8
-9
8
-7
9
10
-6
-4
OFFSET WARMUP DRIFT RESPONSE BAND GAIN WARMUP DRIFT RESPONSE BAND
40 40
ADS1278 High-Speed and High-Resolution Modes ADS1274/78 High-Speed and High-Resolution Modes
30 30
Normalized Gain Error (ppm)
20 20
10 10
0 0
-10 -10
-20 -20
ADS1278 Low-Speed Mode ADS1278 Low-Speed Mode
-30 -30
ADS1274 High-Speed and High-Resolution Modes
-40 -40
0 50 100 150 200 250 300 350 400 0 50 100 150 200 250 300 350 400
Time (s) Time (s)
70
Number of Occurrences
30
60
25
50
20
40
15 30
10 20
5 10
0 0
0
-4000
-3600
-3200
-2800
-2400
-2000
-1600
-1200
-800
-400
0
400
800
1200
1600
2000
2400
2800
3200
3600
4000
-1000
-900
-800
-700
-600
-500
-400
-300
-200
-100
100
200
300
400
500
600
700
800
900
1000
Number of Occurrences
Number of Occurrences
70 50
60
40
50
30
40
30 20
20
10
10
0 0
-1500
-1400
-1300
-1200
-1100
-1000
-900
-800
-700
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
- 1500
- 1400
- 1300
- 1200
- 1100
- 1000
- 900
- 800
- 700
- 600
- 500
- 400
- 300
- 200
- 100
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
Channel Gain Match (ppm) Channel Offset Match (mV)
16
Number of Occurrences
Normalized Offset (mV)
0 200
14
-50 150 12
Gain
-100 100 10
-150 50 8
6
-200 0
4
-250 -50 2
-300 -100 0
2.40
2.41
2.42
2.43
2.44
2.45
2.46
2.47
2.48
2.49
2.50
2.51
2.52
2.53
2.54
2.55
2.56
2.57
2.58
2.59
2.60
-40 -20 0 20 40 60 80 100 120 125
Temperature (C)
VCOM Voltage Output (V)
30
1.32 13.2
ADS1278
25
ADS1274 1.30 13.0
20
1.28 12.8
15 High-Speed and
High-Resolution Modes
1.26 12.6
10 Low-Speed Mode
ADS1278
5 1.24 12.4
0 1.22 12.2
50
100
150
200
250
300
350
400
450
500
550
600
650
700
8
145
INL (ppm of FSR)
140 6
135
130 4
125
2
120
115 0
-40 -20 0 20 40 60 80 100 120 125 -40 -20 0 20 40 60 80 100 120 125
Temperature (C) Temperature (C)
4 10 -108
Linearity (ppm)
T = +25C
2 THD
THD (dB)
8 -112
0
6 -116
-2
-4 4 -120
Linearity
-6 T = -40C
T = +125C 2 -124
-8
See Electrical Characteristics for VREF Operating Range.
-10 0 -128
-2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VIN (V) VREF (V)
Noise 8
Low-Speed Mode
8 8
6
6 6
Linearity 4
4 4 High-Resolution Mode
2 2 2
0 0 0
-0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40 -20 0 20 40 60 80 100 120 125
Input Common-Mode Voltage (V) Temperature (C)
THD (dB)
Low-Speed -60 8
6 Noise
-80 6
4 THD
High-Resolution -100 4
2 -120 2
See Electrical Characteristics for VREF Operating Range.
0 -140 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 10k 100k 1M 10M 100M
VREF (V) CLK (Hz)
Figure 45. Figure 46.
-20 -20
-40 -40
-60 -60
AVDD
-80 -80
DVDD
-100 -100
IOVDD
-120 -120
10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M
Input Frequency (Hz) Power-Supply Modulation Frequency (Hz)
60 High-Speed and
20 High-Speed Mode
High-Resolution Modes
50
15
40
High-Resolution Mode
30
10
Low-Power Mode Low-Power Mode
20
5
10 Low-Speed Mode
Low-Speed Mode
0 0
-40 -20 0 20 40 60 80 100 120 125 -40 -20 0 20 40 60 80 100 120 125
Temperature (C) Temperature (C)
350
0.20 High-Speed Mode
Power Dissipation (mW)
300
IOVDD Current (mA)
0.15 250
High-Resolution Mode
High-Speed Mode 200
Low-Power Mode
0.10 150
High-Resolution Mode
100
0.05 Low-Speed Mode
Low-Power Mode Low-Speed Mode 50
0 0
-40 -20 0 20 40 60 80 100 120 125 -40 -20 0 20 40 60 80 100 120 125
Temperature (C) Temperature (C)
100
20
80 High-Resolution Mode
15
60 Low-Power Mode
Low-Power Mode 10
40
20 5
Low-Speed Mode Low-Speed Mode
0 0
-40 -20 0 20 40 60 80 100 120 125 -40 -20 0 20 40 60 80 100 120 125
Temperature (C) Temperature (C)
700
0.4
0.3 500
High-Speed Mode
400 High-Resolution Mode
0.2 300
Low-Power Mode Low-Power Mode
200
0.1
Low-Speed Mode
High-Resolution Mode 100 Low-Speed Mode
0 0
-40 -20 0 20 40 60 80 100 120 125 -40 -20 0 20 40 60 80 100 120 125
Temperature (C) Temperature (C)
OVERVIEW
High-Speed, High-Resolution, Low-Power, and
The ADS1274 (quad) and ADS1278 (octal) are 24-bit, Low-Speed. Table 2 summarizes the performance of
delta-sigma ADCs based on the single-channel each mode.
ADS1271. They offer the combination of outstanding
dc accuracy and superior ac performance. Figure 57 In High-Speed mode, the maximum data rate is
shows the block diagram. Note that both devices are 144kSPS. In High-Resolution mode, the SNR =
functionally the same, except that the ADS1274 has 111dB (VREF = 3.0V); in Low-Power mode, the power
four ADCs and the ADS1278 has eight ADCs. The dissipation is 31mW/channel; and in Low-Speed
packages are identical, and the ADS1274 pinout is mode, the power dissipation is only 7mW/channel at
compatible with the ADS1278, permitting true drop-in 10.5kSPS. The digital filters can be bypassed,
expandability. The converters are comprised of four enabling direct access to the modulator output.
(ADS1274) or eight (ADS1278) advanced, 6th-order,
The ADS1274/78 is configured by simply setting the
chopper-stabilized, delta-sigma modulators followed
appropriate I/O pinsthere are no registers to
by low-ripple, linear phase FIR filters. The modulators
program. Data are retrieved over a serial interface
measure the differential input signal, VIN = (AINP
that supports both SPI and Frame-Sync formats. The
AINN), against the differential reference, VREF =
ADS1274/78 has a daisy-chainable output and the
(VREFP VREFN). The digital filters receive the
ability to synchronize externally, so it can be used
modulator signal and provide a low-noise digital
conveniently in systems requiring more than eight
output. To allow tradeoffs among speed, resolution,
channels.
and power, four operating modes are supported:
Mod 1
R S Mod 2
VCOM Modulator
Output
R VREF
Mod 8
AGND DGND
(1) The ADS1274 has four channels; the ADS1278 has eight channels.
Amplitude (dB)
frequency response in High-Speed, Low-Power, and -4
Low-Speed modes normalized to fDATA. Figure 59 -5
shows the passband ripple. The transition from
-6
passband to stop band is shown in Figure 60. The
overall frequency response repeats at 64x multiples -7
of the modulator frequency fMOD, as shown in -8
Figure 61. -9
-10
0 0.45 0.47 0.49 0.51 0.53 0.55
Normalized Input Frequency (fIN/fDATA)
-20
-80
20
-100 0
-120 -20
-40
-140
Gain (dB)
-100
Figure 58. Frequency Response for High-Speed, -120
Low-Power, and Low-Speed Modes
-140
-160
0.02 0 16 32 48 64
Input Frequency (fIN/fDATA)
0
-0.02
High-Speed, Low-Power, and Low-Speed Modes
-0.04
These image frequencies, if present in the signal and
not externally filtered, will fold back (or alias) into the
-0.06
passband, causing errors. The stop band of the
-0.08
ADS1274/78 provides 100dB attenuation of
frequencies that begin just beyond the passband and
-0.10
continue out to fMOD. Placing an antialiasing, low-pass
0 0.1 0.2 0.3 0.4 0.5 0.6 filter in front of the ADS1274/78 inputs is
Normalized Input Frequency (fIN/fDATA) recommended to limit possible high-amplitude,
out-of-band signals and noise. Often, a simple RC
filter is sufficient. Table 4 lists the image rejection
Figure 59. Passband Response for High-Speed,
versus external filter order.
Low-Power, and Low-Speed Modes
Table 4. Antialiasing Filter Order Image Rejection
IMAGE REJECTION (dB)
(f3dB at fDATA)
ANTIALIASING
FILTER ORDER HS, LP, LS HR
1 39 45
2 75 87
3 111 129
High-Resolution Mode 0
Amplitude (dB)
shows the passband ripple, and the transition from -4
passband to stop band is shown in Figure 64. The -5
overall frequency response repeats at multiples of the
-6
modulator frequency fMOD (128 fDATA), as shown in
Figure 65. The stop band of the ADS1274/78 -7
provides 100dB attenuation of frequencies that begin -8
just beyond the passband and continue out to fMOD. -9
Placing an antialiasing, low-pass filter in front of the -10
ADS1274/78 inputs is recommended to limit possible 0.45 0.47 0.49 0.51 0.53 0.55
high-amplitude out-of-band signals and noise. Often, Normalized Input Frequency (fIN/fDATA)
a simple RC filter is sufficient. Table 4 lists the image
rejection versus external filter order. Figure 64. Transition Band Response for
High-Resolution mode
0
-20
20
-40 0
Amplitude (dB)
-60 -20
-40
-80
-60
Gain (dB)
-100 -80
-120 -100
-120
-140
0 0.25 0.50 0.75 1 -140
Normalized Input Frequency (fIN/fDATA) -160
0 32 64 96 128
Figure 62. Frequency Response for Normalized Input Frequency (fIN/fDATA)
High-Resolution Mode
Figure 65. Frequency Response Out to fMOD for
High-Resolution Mode
0.02
0
Amplitude (dB)
-0.02
-0.04
-0.06
-0.08
-0.10
0 0.1 0.2 0.3 0.4 0.5 0.6
Normalized Input Frequency (fIN/fDATA)
AVDD AVDD
Figure 68. S1 and S2 Switch Timing for Figure 67
ESD
Protection
Table 6. Modulator Frequency (fMOD) Mode
Selection
MODE SELECTION CLKDIV fMOD
High-Speed 1 fCLK/4
High-Resolution 1 fCLK/4 Figure 70. Equivalent Reference Input Circuitry
1 fCLK/8
Low-Power
0 fCLK/4
VREFP VREFN
1 fCLK/40
Low-Speed
0 fCLK/8
ESD diodes protect the reference inputs. To keep As with any high-speed data converter, a high-quality,
these diodes from turning on, make sure the voltages low-jitter clock is essential for optimum performance.
on the reference pins do not go below AGND by Crystal clock oscillators are the recommended clock
more than 0.4V, and likewise do not exceed AVDD by source. Make sure to avoid excess ringing on the
0.4V. If these conditions are possible, external clock input; keeping the clock trace as short as
Schottky clamp diodes or series resistors may be possible, and using a 50 series resistor placed
required to limit the input current to safe values (see close to the source end, often helps.
the Absolute Maximum Ratings table).
Table 8. Clock Input Options
A high-quality reference voltage with the appropriate
drive strength is essential for achieving the best MODE MAX fCLK DATA RATE
SELECTION (MHz) CLKDIV fCLK/fDATA (SPS)
performance from the ADS1274. Noise and drift on
the reference degrade overall system performance. High-Speed 37 1 256 144,531
See the Application Information section for example High-Resolution 27 1 512 52,734
reference circuits. 27 1 512
Low-Power 52,734
13.5 0 256
CLOCK INPUT (CLK) 27 1 2,560
Low-Speed 10,547
5.4 0 512
The ADS1274/78 requires a clock input for operation.
The individual converters of the ADS1274/78 operate
from the same clock input. At the maximum data rate, MODE SELECTION (MODE)
the clock input can be either 27MHz or 13.5MHz for
Low-Power mode, or 27MHz or 5.4MHz for The ADS1274/78 supports four modes of operation:
Low-Speed mode, determined by the setting of the High-Speed, High-Resolution, Low-Power, and
CLKDIV input. For High-Speed mode, the maximum Low-Speed. The modes offer optimization of speed,
CLK input frequency is 37MHz. For High-Resolution resolution, and power. Mode selection is determined
mode, the maximum CLK input frequency is 27MHz. by the status of the digital input MODE[1:0] pins, as
In High-Speed mode, operating conditions are shown in Table 9. The ADS1274/78 continually
restricted depending on the clock input frequency. monitors the status of the MODE pin during
The limitations are summarized in Table 7. operation.
MODE[1:0]
Pins
ADS1274/78 Previous
Mode
New Mode
Mode
tNDR-SPI
SPI
DRDY
Protocol
New Mode
Valid Data Ready
tNDR-FS
Frame-Sync DOUT
Protocol
New Mode
Valid Data on DOUT
(1) If mode change is asynchronous to the FSYNC clock, tNDR-FS varies from 127 to 128 conversions. If the mode change is made
synchronous to FSYNC, tNDR-FS is stable.
tCSHD
CLK
tSCSU
SYNC tSYN
tNDR
DRDY
tCSHD
CLK
tSCSU
tSYN
SYNC
FSYNC
tNDR
(1) If SYNC is asynchronous to the FSYNC clock, then tNDR varies from 127 to 128 conversions, starting from the rising edge of SYNC. If
SYNC is made synchronous to the FSYNC clock, then tNDR is stable.
CLK
tPWDN
PWDN tNDR
(1)
DRDY/FSYNC
DOUT1
(TDM Mode, Fixed Position) Normal Position Data Remains in Position Normal Position
(1) In SPI protocol, the timing occurs on the falling edge of DRDY/FSYNC. Powering down all channels forces DRDY/FSYNC high.
(1) FSYNC clock running prior to the rising edge of PWDN. If PWDN is asynchronous to the FSYNC clock, tNDR-FS varies from 127 to 128
conversions. If PWDN is made synchronous to FSYNC, then tNDR-FS is stable.
DOUT1
CH1 CH2 CH3 CH4 DIN
(ADS1274)
DOUT1
CH1 CH2 CH3 CH4 CH5 CH7 CH8 DIN
(ADS1278)
DRDY
(SPI)
FSYNC
(Frame-Sync)
DOUT1
CH1 CH2 CH3 CH4 DIN
(ADS1274)
DOUT1
CH1 CH2 CH3 CH4 CH5 CH7 CH8 DIN
(ADS1278)
DRDY
(SPI)
FSYNC
(Frame-Sync)
Figure 78. TDM Mode, Fixed-Position Data (Channels 1 and 3 Shown Powered Down)
DOUT1
(ADS1274) CH2 CH4 DIN
DOUT1
(ADS1278) CH2 CH4 CH5 CH7 CH8 DIN
DRDY
(SPI)
FSYNC
(Frame- Sync)
Figure 79. TDM Mode, Dynamic Position Data (Channels 1 and 3 Shown Powered Down)
SCLK 1 2 22 23 24 25 26
DOUT1 CH1
DOUT2 CH2
DOUT3 CH3
DOUT4 CH4
DOUT5 CH5
DOUT6 CH6
ADS1278 Only
DOUT7 CH7
DOUT8 CH8
DRDY
(SPI)
FSYNC
(Frame-Sync)
ADS1274/78 ADS1274/78
SYNC SYNC
U2 SYNC
U1
NOTE: The number of chained devices is limited by the SCLK rate and device mode.
Figure 81. Daisy-Chaining of Two Devices, SPI Protocol (FORMAT[2:0] = 000 or 001)
DRDY
(SPI)
FSYNC
(Frame-Sync)
SYNC
SCLK
FSYNC
NOTE: The number of chained devices is limited by the SCLK rate and device mode.
Figure 83. Segmented DOUT Daisy-Chain, Frame-Sync Protocol (FORMAT[2:0] = 011 or 100)
(1)
DVDD 1V nom DOUT1 Modulator Data Channel 1
DOUT2 Modulator Data Channel 2
IOVDD 1V nom
(1)
IOVDD
AVDD (1)
3V nom DIN
Internal Reset
FORMAT0
CLK FORMAT1 DOUT4/8(1) Modulator Data Channel 4/8(1)
18 FORMAT2 SCLK Modulator Clock Output
2 129 (max)
fCLK tDATA
DRDY (1) The ADS1274 has four channels; the ADS1278 has eight
(SPI Protocol)
channels.
DOUT
(Frame-Sync Protocol) Figure 85. Modulator Output
Valid Data
In modulator output mode, the frequency of the Table 17. Test Mode Pin Map (TEST[1:0] = 11)
modulator clock output (SCLK) depends on the mode TEST MODE PIN MAP
selection of the ADS1274/78. Table 16 lists the
INPUT PINS OUTPUT PINS
modulator clock output frequency and DVDD current
versus device mode. PWDN1 DOUT1
PWDN2 DOUT2
Figure 86 shows the timing relationship of the
PWDN3 DOUT3
modulator clock and data outputs.
PWDN4 DOUT4
The data output is a modulated 1s density data PWDN5 DOUT5
stream. When VIN = +VREF, the 1s density is
PWDN6 DOUT6
approximately 80% and when VIN = VREF, the 1s
density is approximately 20%. PWDN7 DOUT7
PWDN8 DOUT8
Modulator MODE0 DIN
SCLK
Clock Output
MODE1 SYNC
Modulator FORMAT0 CLKDIV
DOUT
Data Output FORMAT1 FSYNC/DRDY
(13ns max) FORMAT2 SCLK
APPLICATION INFORMATION
5. Reference Inputs: It is recommended to use a
To obtain the specified performance from the minimum 10F tantalum with a 0.1F ceramic
ADS1274/78, the following layout and component capacitor directly across the reference inputs,
guidelines should be considered. VREFP and VREFN. The reference input should
1. Power Supplies: The device requires three be driven by a low-impedance source. For best
power supplies for operation: DVDD, IOVDD, and performance, the reference should have less than
AVDD. The allowed range for DVDD is 1.65V to 3VRMS in-band noise. For references with noise
1.95V; (for 32.768MHz < fCLK 37MHz: 2.0V to higher than this level, external reference filtering
2.2V) the range of IOVDD is 1.65V to 3.6V; may be necessary.
AVDD is restricted to 4.75V to 5.25V. For all 6. Analog Inputs: The analog input pins must be
supplies, use a 10F tantalum capacitor, driven differentially to achieve specified
bypassed with a 0.1F ceramic capacitor, placed performance. A true differential driver or
close to the device pins. Alternatively, a single transformer (ac applications) can be used for this
10F ceramic capacitor can be used. The purpose. Route the analog inputs tracks (AINP,
supplies should be relatively free of noise and AINN) as a pair from the buffer to the converter
should not be shared with devices that produce using short, direct tracks and away from digital
voltage spikes (such as relays, LED display tracks. A 1nF to 10nF capacitor should be used
drivers, etc.). If a switching power-supply source directly across the analog input pins, AINP and
is used, the voltage ripple should be low (less AINN. A low-k dielectric (such as COG or film
than 2mV) and the switching frequency outside type) should be used to maintain low THD.
the passband of the converter. Capacitors from each analog input to ground can
2. Ground Plane: A single ground plane connecting be used. They should be no larger than 1/10 the
both AGND and DGND pins can be used. If size of the difference capacitor (typically 100pF)
separate digital and analog grounds are used, to preserve the ac common-mode performance.
connect the grounds together at the converter. 7. Component Placement: Place the power supply,
3. Digital Inputs: It is recommended to analog input, and reference input bypass
source-terminate the digital inputs to the device capacitors as close as possible to the device
with 50 series resistors. The resistors should be pins. This layout is particularly important for
placed close to the driving end of digital source small-value ceramic capacitors. Larger (bulk)
(oscillator, logic gates, DSP, etc.) This placement decoupling capacitors can be located farther from
helps to reduce ringing on the digital lines (ringing the device than the smaller ceramic capacitors.
may lead to degraded ADC performance).
Figure 88 to Figure 90 illustrate basic connections
4. Analog/Digital Circuits: Place analog circuitry and interfaces that can be used with the ADS1274.
(input buffer, reference) and associated tracks
together, keeping them away from digital circuitry
(DSP, microcontroller, logic). Avoid crossing
digital tracks across analog tracks to reduce
noise coupling and crosstalk.
(1)
THS4521 ADS1274/ADS1278 +3.3V TMS320VC5509
CLK
50W
DRDY/FSYNC FSR
U2
DOUT1 0 Q DR
U1 CVDD
SCLK > Q +1.6V
50W (CORE)
DOUT2 CLKR
See
DOUT3 Note (5) 200MHz
IN4/8(+) AINP4/8
DOUT4
IN4/8(-) (3)
AINN4/8
+5V 2.2nF SYNC
PWDN1 I/O
AVDD
+ (2)
10mF (6) PWDN2
+1.8V DVDD
(2)
10mF PWDN3
See
PWDN4
Note (6)
1mF
REF5025 VREFP
+ (2)
10mF 0.1mF CLKDIV +3.3V
VREFN
(High-Speed, Frame-Sync, TDM,
MODE0 and Fixed-Position data selected.)
+5V VCOM
(2) MODE1
0.1mF (4) TEST0
100W TEST1 FORMAT2 +3.3V
Buffered
VCOM OPA350 DIN FORMAT1
Output AGND
DGND FORMAT0
(1) External Schottky clamp diodes or series resistors may be needed to prevent overvoltage on the inputs. Place the THS4521 drivers close
to the ADS1278 inputs.
(2) Indicates ceramic capacitors.
(3) Indicates COG ceramic capacitors.
(4) Optional. For pin test mode.
(5) U1: SN74LVC1G04; U2: SN74LVC2G74. These components re-clock the ADS1274/78 data output to interface to the TMS320VC5509.
(6) If CLK > 32.768MHz, use the REF5020 and DVDD = 2.1V.
Buffered (1)
Buffered (1) +5V
+5V VCOM
VCOM 49.9W
49.9W Output
Output
AINP AINP
VOCM
VOCM THS4521
VIN THS4521 49.9W 49.9W
0.1mF 0.1mF AINN
AINN (3)
(3)
Mold Compound
IC Die (Epoxy)
Leadframe
PowerPAD PCB Layout Considerations The via connections to the thermal pad and internal
ground plane should be plated completely around the
Figure 92 shows the recommended layer structure for
hole, as opposed to the typical web or spoke thermal
thermal management when using a PowerPad
relief connection. Plating entirely around the thermal
package on a 4-layer PCB design. Note that the
via provides the most efficient thermal connection to
thermal pad is placed on both the top and bottom
the ground plane.
sides of the board. The ground plane is used as the
heatsink, while the power plane is thermally isolated
Additional PowerPAD Package Information
from the thermal vias.
Texas Instruments publishes the PowerPAD
Figure 93 shows the required thermal pad etch
Thermally Enhanced Package Application Report (TI
pattern for the HTQFP-64 package used for the
literature number SLMA002), available for download
ADS1274. Nine 13mil (0.33mm) thermal vias plated
at www.ti.com, that provides a more detailed
with 1 ounce of copper are placed within the thermal
discussion of PowerPAD design and layout
pad area for the purpose of connecting the pad to the
considerations. Before attempting a board layout with
ground plane layer. The ground plane is used as a
the ADS1274, it is recommended that the hardware
heatsink in this application. It is very important that
engineer and/or layout designer be familiar with the
the thermal via diameter be no larger than 13mils in
information contained in this document.
order to avoid solder wicking during the reflow
process. Solder wicking results in thermal voids that
reduce heat dissipation efficiency and hampers heat
flow away from the IC die.
Package
Thermal Pad
Component
Traces
13mils (0.33mm)
Component (top) Side
Thermal Via
Ground Plane
Power Plane
Thermal Isolation
(power plane only)
Package
Thermal Pad
(bottom trace)
118mils (3mm)
40mils (1mm)
40mils (1mm)
Package Outline
Thermal Pad
40mils (1mm)
40mils (1mm)
118mils (3mm)
316mils (8mm)
Thermal Via
13mils (0.33mm)
316mils (8mm)
Figure 93. Thermal Pad Etch and Via Pattern for the HTQFP-64 Package
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Added supplemental timing requirements (tDOPD) to SPI Format Timing Specification table ............................................... 8
Added supplemental timing requirements (tDOPD and tMSBPD) to Frame-Sync Format Timing Specification table ................ 9
www.ti.com 10-Jun-2014
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
ADS1274IPAPR ACTIVE HTQFP PAP 64 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS1274
& no Sb/Br)
ADS1274IPAPT ACTIVE HTQFP PAP 64 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS1274
& no Sb/Br)
ADS1274IPAPTG4 ACTIVE HTQFP PAP 64 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS1274
& no Sb/Br)
ADS1278IPAPR ACTIVE HTQFP PAP 64 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 105 ADS1278
& no Sb/Br)
ADS1278IPAPT ACTIVE HTQFP PAP 64 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 105 ADS1278
& no Sb/Br)
ADS1278IPAPTG4 ACTIVE HTQFP PAP 64 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 105 ADS1278
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Sep-2015
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Sep-2015
Pack Materials-Page 2
www.ti.com
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