DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

01UEC903COMPUTER ARCHITECTURE AND ORGANIZATION

SIXTH SEMESTER

Part A
1. What are addressing modes? List different addressing modes.
2. Define instruction format with example.
3. What is meant by little Endian and big-Endian
4. Differentiate direct and indirect addressing mode
5. Give an example of Zero address, one address, two address and three address
instruction
6. Explain the status register and its bits.
7. Define IEEE standard for floating point numbers
8. Explain the design process for a digital system.
9. Write short notes on word gate
10. Write short notes on programmable logic devices
11. What do you mean by instruction format? Explain it with the help of example?
12. Name the functional units of a computer and how they are interrelated?
13. Draw the architecture of Von Neumann architecture
14. Define: Instruction cycle and explain basic instruction cycle with the help of
flowchart.
15. Explain top down design approach.
16. Write short notes on PC and SP.
17. What do you mean by Von Neumann bottleneck?
Part B
1. Explain in detail Von Neumann architecture with neat diagram
OR
Explain the CPU organization with neat diagram.(12)
X=A*B+C*C, explain how the above expression will be executed in one address, two
address and three address processors in an accumulator organization.(4)

2. Write in detail about various addressing modes with suitable examples.

OR
Describe the factors that determine the speed of the processor and explain the
processor level design using prototype structure.

3. Construct the Full Adder outputs sum and carry using multiplexer.
OR
Construct the various Boolean functions using multiplexer based FPGA cell. Develop
the code for the following expression will be executed in one address, 2-address and
3- address processors in an accumulator organization.
X =Ax B + C x C

4. Draw and explain the CPU organization.

OR
 what are the major components types at register level? using a multiplexer implement
a full adder.
Develop the code for the following expression will be executed in one address, 2-
address and 3- address processors in an accumulator organization.
X =Ax B + C x C

5. Explain in detail function of fundamental computer block diagram with neat diagram
Write the code execute the instruction X=A * C+ C * B using 2 address
and zero address processors?
OR
Develop the 8 bit magnitude comparator circuit with suitable example.