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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS
A Self-Powered and Optimal SSHI Circuit
Integrated With an Active Rectifier for
Piezoelectric Energy Harvesting
Liao Wu, Xuan-Dien Do, Sang-Gug Lee, and Dong Sam Ha
Abstract This paper presents a piezoelectric energy harvest-
ing circuit, which integrates a Synchronized Switch Harvesting
on Inductor (SSHI) circuit and an active rectifier. The major
design challenge of the SSHI method is flipping the capacitor
voltage at optimal times. The proposed SSHI circuit inserts an
active diode on each resonant loop, which ensures flipping of
the capacitor voltage at optimal times and eliminates the need
to tune the switching time. The diodes of the SSHI circuit are
also used as a rectifier to further simplify the controller. The key
advantage of the proposed circuit is a simple controller, which
leads to low power dissipation of the proposed circuit to result in
high efficiency. The proposed circuit is self-powered and capable
of starting even when the battery is completely drained. The
circuit was fabricated in BiCMOS 0.25 m technology with a
die size of 0.98 0.76 mm2 . Measured results indicate that the
proposed circuit increases the amount of power harvested from
a piezoelectric cantilever by 2.1 times when compared with a full
bridge (FB) rectifier and achieves a power conversion efficiency
of 85%. The proposed circuit dissipates about 24 W while the
controller alone only 1.5 W.
Index Terms Active rectifier, piezoelectric energy harvesting,
SSHI, vibration energy harvesting.
I. I NTRODUCTION
V IBRATION energy harvesting finds useful applications
such as wireless sensors for wildlife tracking and implant
devices, where replacing or recharging batteries is inconve-
nient, expensive, or impractical. Piezoelectric (PE) transduc-
ers have several advantages for vibration energy harvesting
including high power density, good scalability, and versatile
shape. A general purpose PE energy harvesting circuit requires
rectification, maximum power extraction, and output voltage
regulation. Most existing research on PE energy harvesting
circuits focuses on the first two requirements, rectification
and maximum power extraction, which pose unique design
challenges.
Manuscript received May 13, 2016; revised July 20, 2016 and
September 4, 2016; accepted September 6, 2016. This work was supported in
part by the Center for Integrated Smart Sensors funded by the Korea Ministry
of Science, ICT & Future Planning as Global Frontier Project(CISS-2-3). This
paper was recommended by Associate Editor E. Bonizzoni.
L. Wu is with the College of Computer Science and Electronic Engineering,
Hunan University, Changsha 410082, China.
X.-D. Do and S.-G. Lee are with the Nice lab, Korea Advanced Insti-
tute of Science and Technology, Daejeon 305-732, South Korea (e-mail:
sglee@ee.kaist.ac.kr).
D. S. Ha is with the Department of Electrical and Computer Engineering,
Virginia Tech, (e-mail: ha@vt.edu).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2016.2608999
1549-8328 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1
Intensive research has been conducted on the design of PE
energy harvesting circuits [1][32]. Specifically, the objective
of energy harvesting circuits is to maximize the net energy
flowing into the storage device and/or the load. To meet
this objective, it is necessary for a PE energy harvesting
circuit to extract maximum power from the PE transducer
while minimizing its power dissipation. A PE transducer has a
relatively large capacitive term with a low resonant frequency.
Due to this fact, complex conjugate matching to extract
maximum power requires an impractically large inductor in the
order of tens to hundreds Henry. Many researchers resort to a
suboptimal solution called resistive matching [1], [2]. Since the
optimal resistance changes as the operating conditions change,
maximum power point tracking was adopted for [3][6].
A different method based on a nonlinear technique called Syn-
chronized Switch Harvesting on Inductor (SSHI) was proposed
in [7]. The SSHI method forms a resonant circuit with the
internal capacitor of a PE transducer and an external inductor,
which flips the capacitor voltage instantly to nullify the effect
of the capacitive term. So the energy to charge the capacitor
necessary to conduct the following rectifier diode(s) can be
harvested that would otherwise have been wasted. Extensive
research was conducted to improve the original SSHI method
and/or exploit the potential of the resonant circuit formed by
the internal capacitor and an external inductor [8][24].
Another major research effort for energy harvesting circuit
design for PE transducers lies in low power dissipation of
the harvesting circuits. PE transducers generate AC voltages,
and power loss associated with rectifiers could be substantial
for small-scale energy harvesting. A straightforward solution
is to use active rectifiers, which was considered for [3], [5],
[6], [10], [15], [17], [22], [25][30]. Kwon and Rincn-Mora
proposed a scheme to eliminate a rectifier in conjunction with
a variation of the SSHI method [8]. Garbuio et al. adopted a
transformer rather than an inductor to implement the SSHI
method, which eliminates the rectifier [9]. To reduce the
conduction loss of a diode based rectifier, Xu et al. used a
negative voltage converter (NVC) while adopting a variation
of the SSHI method [10]. Since then, NVCs are adopted in
many designs [15], [17], [22], [24], [30]. For details on various
implementations of the SSHI method and active rectifiers, refer
to a review paper by Rincn-Mora and Yang [33].
Finally, several researchers investigated schemes for PE
transducers to draw more power from vibrations [11][13].
The schemes of [12] and [13] invert a portion of the harvested
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2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS
Fig. 1. Typical SSHI circuit.
energy back to the internal capacitor of a PE transducer,
which strengthens the electrostatic or damping force of the
PE transducer to generate more power.
This paper presents a self-powered SSHI circuit integrated
with an active rectifier, which ensures flipping of the capacitor
voltage at optimal times and eliminates the need to tune the
switching time. The key advantage of the proposed circuit is
a simple controller, which leads to low power dissipation of
the proposed circuit to result in high efficiency. Also, the
circuit is able to cold-start even if the battery is drained.
The paper is organized as follows. Section II describes
the basic operation of an SSHI circuit and analyzes the
effect of the quality factor and insertion of a diode into an
LC resonator. Section III presents the operation of the pro-
posed circuit followed by an output power analysis. Section IV
covers implementation of key building blocks and the cold-
start process. Section V shows measurement results of the
proposed circuit and compares its performance with other
recent circuits. Finally, Section VI concludes the paper.
II. P RELIMINARIES
A. Review of the SSHI Method and Relevant Works
A typical SSHI circuit is illustrated in Fig. 1, in which the
PE transducer is modeled1 as a current source in parallel with
an internal capacitor C P and a resistor R P . The switch is
closed at each zero-crossing point of the current, and then the
inductor L and the capacitor C P form a resonant circuit to
oscillate. The switch is open at the moment when the capacitor
voltage becomes the peak in the opposite polarity to result
in the flipping of the capacitor voltage. The voltage flipping
enables the SSHI circuit to harvest the capacitor charge rather
than it being discharged to waste.
Since introduction of the SSHI method in [7], a variety
of papers investigated to realize the SSHI method efficiently
or explore the potential of an LC resonant circuit [14][24].
The major design challenge for the SSHI method and its
variations lies in the precise timing control to switch off
at the peak voltage with minimal circuit complexity of the
controller. Ramadass and Chandrakasan rely on an external
eight-bit digital control module to tune the timing circuit [14].
Sanchez et al. use a variable resistor to tune a precision
1 It is a simplified model. A simpler model without the resistor R is also
P
commonly used [6], [14], [16]. Refer to [36] for a more general and accurate
model.
timer [15]. To avoid external tuning, a passive diode is
inserted into a resonant loop followed by a full-bridge rectifier
in [16][18]. A diode in a resonant loop makes the loop current
to flow only in one direction, which holds the capacitor voltage
upon reaching its peak in the opposite polarity. This scheme
eliminates the need to switch off at the peak voltage, which is
explained in detail in the following subsection. The method in
[16][18] requires a polarity detection circuit as well as two
diodes, which makes the controller rather complex.
Lefeuvre et al. in [19] use an LC resonant circuit to
transfer the energy stored in the internal capacitor of a PE
transducer to the inductor. Then, the stored inductor energy is
transferred to the load or the storage through a DCDC con-
verter(s). The method is called Synchronous Electrical Charge
Extraction (SECE), and several papers such as [20][24]
further improve the original method. The extracted power of
the SECE method does not depend on the load, and so the
load can vary without affecting the efficiency. The controller
of the SECE method is quite complex. Yuk et al. in [20]
accumulates the internal capacitor charge over several cycles
through capacitor voltage flipping. Then, the capacitor is
connected to the load and transfers its stored energy to the
load at the peak capacitor voltage. The circuit uses several
comparators, op-amps, capacitors, and switches to control
the switch timing and detect the highest tolerable voltage.
Wu et al. in [21] use a transformer with two primary coils
to simplify the controller and rely on a dSPACE to generate
control signals for their prototype. The controllers of [22][24]
include several detectors to generate timing signals.
This paper adopts the method presented in [16][18] which
inserts a diode for each resonant loop. The proposed method,
however, drastically simplifies the controller through integra-
tion of an SSHI circuit and an active rectifier. The diodes
of two resonant loops limit the loop current to flow in
one direction during the SSHI operation and rectify the PE
transducer voltage during the energy transfer. The dual role of
diodes is feasible as the periods for the SSHI operation and
the energy delivery do not overlap in time.
B. Effect of the Q Factor on the Extracted Power
An SSHI circuit forms an LC resonant circuit to flip the
internal capacitor voltage, and the efficiency of the circuit
is sensitive to the flipping time. Fig. 2(a) shows an RLC
resonant circuit, where C denotes the internal capacitor of a
PE transducer and R, the cumulative parasitic resistance along
the loop, including the parasitic resistance of the inductor, the
switch and the diode. Let us consider that the capacitor voltage
is Vrect initially and the switch SW is open. The switch is
closed at t = 0. Lets assume the diode is not present as in the
original SSHI circuit. The capacitor voltage is obtained as
0
v c (t) = Vrect et cos(d t ) (1)
d

where = 2L R
, 0 = 1 , d = 02 2 and =
LC
arccos( d0 ).
Fig. 2(b) shows the waveform of the capacitor voltage v c (t).
Assuming R is very small, is close to 0. The optimal flipping
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WU et al.: A SELF-POWERED AND OPTIMAL SSHI CIRCUIT INTEGRATED WITH AN ACTIVE RECTIFIER FOR PIEZOELECTRIC ENERGY HARVESTING
Fig. 2. SSHI circuit (a) R LC resonator, (b) capacitor voltage.
time topt and its flipping voltage Vopt are obtained as
1 2
topt = = 
2 d 1
R2
LC 4L 2
and
2
Q 41
Vopt = Vrect e 2
where Q is the quality factor of the RLC circuit and given as
 Fig. 4 presents the basic operation of the proposed circuit.
1 L
Q= (4)
R C
As the Q factor increases, Vopt increases. This implies the
SSHI circuit becomes more efficient with a larger L and a
smaller R. As the inductor is typically off-chip for PE energy
harvesting, a large L increases the size of the circuit as well
as the parasitic resistance. As noted earlier, the key design
challenge for the original SSHI circuit is to open the switch
at t = topt .
Now consider an ideal diode is inserted in the loop. When
the capacitor voltage reaches the peak at topt and the loop
current becomes zero, the diode prevents the current from
flowing back to the inductor. This implies the loop becomes
effectively open and hence, it eliminates the need to open the
switch at the precise time of topt . The proposed SSHI circuit
adopts this scheme, in which a diode is also used to rectify the
transducer voltage. The diode voltage drop v d across a non-
ideal diode reduces Vrect to (Vrect - v d ) in (3), which leads to
the reduction of Vopt . The proposed SSHI circuit uses active
diodes to reduce the diode voltage drop. The earlier version of
our paper in [32] presents only simulation results, while this
paper includes measurement results.
III. P ROPOSED SSHI R ECTIFIER
A. Block Diagram
Fig. 3 shows the block diagram of the proposed SSHI circuit
integrated with a rectifier. The circuit consists of two active
diodes D1 and D2 , two switches SW1 and SW2 , and one
inductor L. Note that the topology of the proposed circuit,
when ignoring the inductor, is identical to that of a full-bridge
rectifier with replacement of two left switches with diodes.
3
Fig. 3. Proposed SSHI circuit integrated with an active rectifier.
For simplicity of illustration and analysis, the diodes and
(2) switches are considered ideal in the following, unless stated
otherwise. The load voltage Vrect is assumed constant due to
large load capacitor C L .
(3)
B. Operation
Fig. 4(a) shows the waveforms of the transducer current i p ,
the PE transducer voltage V B A , the inductor current i L , and
the clock signal C L K . Fig. 4(b) -4(g) show the state of the
switches and the diodes for the specified time intervals. During
the time interval of t0 < t < t1 in Fig. 4(b), the transducer
current is positive with SW1 open, and SW2 closed. The
inductor current i L is zero, and the node voltage V B , which is
identical to V B A , is smaller than Vrect . Thus, the two diodes are
turned off to block the current flow into the load. During this
period, the transducer current charges the internal capacitor C P
to increase V B A . At t1 , V B A (= V B ) reaches Vrect , causing D1
to conduct, and the entire transducer current i P starts to flow
into the load as shown in Fig. 4(c). Note that the inductor
current i L increases sharply at t1 , as shown in Fig. 4(a). During
t1 < t < t2 , the transducer delivers energy to the load, while
the diode D1 acts as a rectifier. Note that the inductor current
i L is equal to i P . As i P crosses the zero point to become
negative at t2 , the capacitor C P starts to discharge. As a result,
V B A decreases to set V B < Vrect to turn D1 off at t3 , shortly
after the zero-crossing point, as shown in Fig. 4(d). The C L K
signal sensing D1 turned off or V B < Vrect changes its status
to close SW1 and to open SW2 as shown in Fig. 4(e). So
the state in Fig. 4(d) is transient. Noting the inductor current
is zero at t3 , the switching actions, close of SW1 and open
of SW2 , makes the node voltage V A equal to Vrect instantly.
It causes the node voltage V B to increase by a factor of Vrect
at t3 , thereby turning on the diode D1 again at t3 . Since both
SW1 and D1 are turned on, a resonant loop along A-B-C-D is
created to perform the SSHI operation. The energy stored in
C P transfers to the inductor, and then the inductor energy is
transferred back to the capacitor to flip the capacitor voltage to
Vopt . As the diode D1 in the loop restricts the current to flow
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4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS

Fig. 4. Configurations of the proposed circuit (a) voltage and current waveforms, (b) during t0 < t < t1 , (c) during t1 < t < t2 , (d) during t2 < t < t3
(transient), (e) during t3 < t < t5 , (f) during t5 < t < t6 , (g) during t6 < t < t7 .

only in the direction of B C D A, the loop current The negative transducer current charges C P during t5 < t < t6
becomes zero at t5 and hence the inductor voltage V AD . The as shown in Fig. 4(f). As |V B A | becomes greater than |Vrect |
node voltage V B at t5 is Vopt to turn D1 off, which finishes at time t6 , D2 conducts, and the transducer current flows into
the voltage flipping procedure by itself at the optimal time t5 . the load during t6 < t < t7 as shown in Fig. 4(g). Note D2
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WU et al.: A SELF-POWERED AND OPTIMAL SSHI CIRCUIT INTEGRATED WITH AN ACTIVE RECTIFIER FOR PIEZOELECTRIC ENERGY HARVESTING 5

Therefore, the amount of charge that flows into the load in

each cycle is obtained as
 
Q rect = Q t ot al Q loss = 2C P 2Voc 2Vrect + V f (9)

The harvested power is

 
Pout = 2 f P C P 2Voc 2Vrect + V f Vrect (10)
Vf
Noting F = 2Vrect , Pout can be also expressed as

Pout = 4 f P C P [Voc (1 F ) Vrect ] Vrect (11)

Assuming an ideal rectifier, the power at the load resistor is

2
Vrect
Pout = (12)
RL
From (5), (11) and (12), the output power is expressed as

2
2I P R L
Fig. 5. Transducer current and simplified voltage waveforms. Pout = (13)
(1 + 4 f P C P (1 F ) R L )
acts as a rectifier during the period. The same process repeats Voc
When Vrect = 2(1 F)
= 4 f P CIPP(1 F ) or R L =
for the negative transducer current. 1
Unlike those in [8], [14][15], the proposed circuit does 4 f P C P (1 F ) , Pout becomes maximum. The maximum output
not require a timing circuit to end the voltage flipping at the power is obtained as
optimal times t5 and t10 . Elimination of a complex timing 2
Voc I P2
circuit drastically simplifies the controller to reduce the power Pout,max = f P C P = (14)
dissipation and hence to improve the efficiency. 1 F 4 2 f P C P (1 F )
From (11) and (13), the extracted power depends on the output
C. Extracted Power voltage Vrect , the load resistor R L , and the flip voltage ratio
A PE transducer in Fig. 3 is modeled as a sinusoidal current F , where F depends on the Q factor of the LC resonant
source i P (t) = I P sin(2 f P t) in parallel with an internal loop given in (4).
capacitor C P and a resistor R P , where f P represents the
excitation frequency. Assuming R P is large, the peak open-
circuit voltage of the transducer is given as IV. I MPLEMENTATION OF THE P ROPOSED C IRCUIT
IP Fig. 6 shows the building blocks of the proposed circuit
Voc = (5) consisting of an external inductor L and a capacitor C L .
2 f P C P
Two major design objectives of the proposed circuit are high
Fig. 5 shows the transducer current and the simplified
noise immunity and minimization of power dissipation, and
voltage waveform across the capacitor C P during a voltage
the topologies of the building blocks are chosen toward the
flipping period. Let us define the f li p voltage r ati o F as
objective at the cost of, possibly, speed and bandwidth. The
the ratio of the amount of the capacitor voltage change V f to
PE transducer current and the rectifier voltage Vrect determine
the maximum possible voltage change
the on/off state of the two diodes, D1 and D2 , which in
Vf Vopt + Vrect turn are used to generate the control signals of the two
F = (6)
2Vrect 2Vrect switches.
Note the capacitor voltage changes fromVrect to Vopt or An important design issue of the proposed circuit is accurate
the other way to result in V f = Vopt +Vrect . detection of zero-crossing points of the transducer current i P .
Referring to Fig. 5, the amount of charge lost per cycle is As a diode, either D1 or D2 , turns off at every zero-crossing
obtained as point, the issue is in essence to design high performance
   active diodes. The diode D1 (D2 ) is composed of an op-amp
Q loss = 2C P Vrect V f Vrect (7) OP1 (OP2) and NMOS device M1 (PMOS device M2 ). The
While the total amount of charge available from the transducer op-amp outputs are also applied to the clock generator, which
in one cycle is given as (8) [14] generates control signals, NC L K and PC L K , for the two
 1/ f P  1/ f P switches. The reference current block with a start-up circuit
Q t ot al = |i P | dt = |I P sin (2 f P t)| dt provides the bias current for the op-amps. The load capacitor
0 0 C L is large to maintain the load voltage Vrect nearly constant
2I P during the operation. Implementation of major building blocks
= = 4C P Voc (8)
fP and cold-starting operation are described in the following.
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6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS
Fig. 6. Building blocks of the proposed circuit.
Fig. 7. Op-amps (a) supply compatible OP1, (b) ground compatible OP2.
A. Active Diodes D1 and D2
Active diodes D1 and D2 are composed of MOSFETs and
associated op-amps with a narrow linear region. Specifically,
the op-amps with a narrow linear region behave as typical op-
amps only for a small differential input range, per say from
VT H to VT H + , and as a comparator outside of the input
range.
The op-amp and its associated MOSFET device of the
diode D1 or D2 form a negative feedback loop to improve
the performance for small current across the device. A typical
active diode is based on a Schmitt trigger (or comparators
with hysteresis), which intends to increase noise immunity for
small diode current. However, such noise immunity affects the
proposed circuit negatively. Consider the circuit state shown
in Fig 4(d) right after the zero-crossing point, in which the
diode D1 is turned off. Suppose that the diode is forward-
biased momentarily and turned on due to noise. Then, the
circuit goes back to the previous state in Fig. 4(c), and the
circuit tries to harvest the noise power. In contrast, consider a
typical active diode based on a Schmitt trigger. It makes the
circuit to stay in the same state of Fig. 4(d) by suppressing
the noise, and the noise discharges the capacitor C P to waste
the stored energy.
Fig. 7 shows implementations of the two op-amps,
OP1 and OP2. The op-amp OP1 is supply compatible, while
OP2 is ground compatible. Two pMOS transistors, MP1 and
MP2 of OP1, form a common-gate differential amplifier, and
a pair of low threshold transistors, MP3 and MP4, operating
in the subthreshold region form a current mirror for the
single-ended output [5]. The operation of MP3 and MP4 in
the subthreshold region reduces the power dissipation at the
cost of a reduced bandwidth, which is not an issue for the
vibration energy harvesting application. The four transistors
have relatively large widths and lengths for good matching.
MN1MN6 form two sets of cascode current mirrors to supply
the bias current of the amplifier. A cascode structure reduces
output voltage swing to set a narrow linear region. The
ground compatible op-amp is the reciprocal of the supply
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WU et al.: A SELF-POWERED AND OPTIMAL SSHI CIRCUIT INTEGRATED WITH AN ACTIVE RECTIFIER FOR PIEZOELECTRIC ENERGY HARVESTING
Fig. 8. Schmitt trigger (a) for OP1, (b) for OP2, (c) I/O curve of the Schmitt trigger.
compatible one. Simulation results indicate the dc gain of
the op-amps is around 85 dB, and the unity-gain bandwidth
is around 200 kHz.
Finally, the two transistors, nMOS M1 and pMOS M2 , can
be swapped with the swapping of the two inputs of each
associated op-amp. In fact, such a topology, a pMOS transistor
on the top and an nMOS transistor on the bottom, is typical
for a series connection of two active diodes. We selected the
opposite, as it is more immune to noise at the node connecting
the two diodes. However, our topology results in about two
times higher power dissipation compared with the typical one
and an increased diode voltage drop across the two transistors.
For details, refer to our previous work in [32].
B. Schmitt Trigger
The on/off states of the two diodes, D1 and D2 , are used
to generate the control signals of the two switches. The
Schmitt triggers at the output of two op-amps increase noise
immunity of the clock generator during zero-crossing points
of the transducer current i P . Fig. 8(a) and (b) show two
implementations of the Schmitt trigger based on the one
in [34]. The first stage of the Schmitt triggers is a source
follower, which isolates the Schmitt trigger from its proceeding
op-amp. Fig. (8c) shows the I/O curve of the Schmitt trigger, in
which the proceeding op-amps have the linear region between
VT H and VT H + .
C. Clock Generator
The clock generator block consists of a voltage regulator, a
clock signal generator, and a level shifter. A voltage regulator
in Fig. 9(a) provides a regulated supply voltage V D I G to
the clock signal generator independent of the load voltage
Vrect , which can fluctuate depending on the amount of energy
generated by the PE transducer in real applications. The
current of the three lateral junction diodes D1 through D3
is fixed due to the reference current IB and the associated
current mirror, and they generate a reference gate voltage of
1.8 V for transistor MN2. The rail voltage V D I G is equal to
(1.8 VVG S ), where VG S is the gate-to-source voltage of MN2.
Note that VG S remains constant as long as the power dis-
sipation of the clock signal generator, more specifically the
7
drain current of MN2, remains constant. The simple topology
intends to minimize the power dissipation of the voltage
regulator.
The clock signal generator generates two complementary
control signals for the two switches, SW1 and SW2 , and
the two control or clock signals, NC L K and PC L K , are
non-overlapping for the two switches. Note that NC L K L
corresponds to the C L K signal in Fig. 3 and Fig. 4. The
clock signal generator and its timing diagram are shown in
Fig. 9(c). Two D flip-flops generate the clock signal C L K ,
and the following block introduces a dead time between the
two clock signals, NC L K and PC L K . The last block shown
in Fig 9(b) is a level shifter, which widens the swing voltage
of the two clock signals between Vrect and G N D, so that the
two switches are fully turned on or off. The clock generator
is simple and does not require any tuning circuit.
D. Reference Current Generator With a Start-Up Circuit
The reference current generator intends to provide a
30 nA reference current to the regulator and op-amps even
if the supply voltage Vrect may vary in real applications.
A 30 nA reference current generator with a start-up circuit
is shown in Fig. 10. The topology of the current generator
is rather common and adopted from [35]. The start-up circuit
drives the reference current generator out of the degenerated
bias by injecting current into the node C during the start-up.
As Vrect increases from zero during the start-up, all transistors
are turned off initially. The node A follows Vrect due to
the diode-connected device MP2, and all pMOS transistors
remain turned off. Once Vrect exceeds the threshold voltage of
transistor MN0, MN0 is turned on to charge the capacitor C1.
As W/L of MN0 is small and C1 is relatively large, the node
voltage V B rises slowly compared with Vrect . The transistor
MP6 is eventually turned on, thereby injecting current into the
node C. Once the circuit has started up, the node voltage V A
decreases to turn on the device MP5 with large W/L. As a
result, V B rises close to Vrect to turn off MP6, which finishes
the current injection to the reference current generator.
E. Operation of Cold-Start
As the source terminals of two switches, SW1 and SW2 ,
and two active diodes, M1 and M2 , in Fig. 6 are tied to their
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8 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS

Fig. 9. Clock generator (a) voltage regulator, (b) level shifter, (c) clock signal generator.

Fig. 10. 30 nA reference current generator with a start-up circuit.

substrates, there exist body diodes for these transistors. It can or too low to power active blocks (such as the op-amps, the
be seen easily that the four body diodes form a full bridge clock generator, and the reference current generators) properly.
rectifier for the PE transducer connected in series with the It requires a higher transducer voltage to charge the capacitor
inductor L. The rectifier formed by body diodes rectifies the , when compared with the
to the desired voltage level, say Vrect
transducer voltage and charges up the load capacitor C L during transducer voltage to maintain Vrect during normal operation
a cold-start, where the capacitor voltage Vrect is drained to zero after the start-up. This is because that the piezoelectric energy
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WU et al.: A SELF-POWERED AND OPTIMAL SSHI CIRCUIT INTEGRATED WITH AN ACTIVE RECTIFIER FOR PIEZOELECTRIC ENERGY HARVESTING
Fig. 11. Proposed circuit (a) die photo, (b) layout.
is harvested only through the full bridge rectifier during a cold-
start, while through the SSHI circuit integrated with an active
rectifier during normal operation. Also, a rectifier realized by
body diodes performs poorer to dissipate larger power when
compared with an active rectifier.
V. M EASUREMENT R ESULTS
The proposed circuit was implemented and fabricated in
0.25 m silicon-only BiCMOS technology. Off-chip compo-
nents of the circuit are the inductor L, the load resistor R L ,
and the load capacitor C L . A microphotograph and its layout
of the chip are shown in Fig. 11, and the die area of the
proposed circuit is 980 m 760 m. We also implemented
our previous piezoelectric energy harvesting circuit on the
same die for comparison, which resets the internal capacitor
voltage (instead of flipping) at zero-crossing points [31].
A piezoelectric cantilever (MIDE, model V22B) was used
for the measurements described below. The cantilever with a
tip mass of 1 gram was placed on a thick aluminum plate,
which was mounted on a electrodynamic shaker as shown
in Fig. 12. An accelerometer attached to the shaker was
used to measure the acceleration. We characterized the PZT
cantilever to obtain the simplified equivalent circuit model
shown in Fig. 1. The resonant frequency of the cantilever
is 144 Hz, C P is 19 nF, and R P is 66 k. The off-chip
components are set to L = 220 H2 , R L = 100 k, and
C L = 6.7 F in the experiments, unless stated otherwise.
The first experiment was to verify the operation of the
proposed circuit. The shaker was oscillating in 144 Hz with
RMS acceleration of 0.7 g. The peak open-circuit voltage
of the cantilever is observed as 4.9 V, and the load voltage
Vrect is 3.9 V. A 10  resistor3 is inserted in series with the
inductor to measure the inductor current for this set up only,
which intends to show up the charging process clearly after
a capacitor voltage flipping. Fig. 13 shows the voltage V B A
across the PE cantilever and the inductor current i L . As the
current i P of the PE cantilever changes its direction from
negative to positive, the cantilever or the capacitor voltage
V B A flips from about - 3.9 V to 1.2 V instantaneously in
Fig. 13(a). Then, the capacitor voltage rises slowly toward
3.9 V or Vrect . Fig. 13(b) and (c) show the close-up views of
2 The minimum operable inductor size which we tried is 22 H
3 The series 10  resistor reduces the flipping voltage. The resistor was
replaced with a current sensor to measure the performance of the proposed
circuit reported hereafter.
9
Fig. 12. Experiment setup.
the waveforms during rising- and falling-edge transitions, in
which the waveforms of the inductor current i L match to the
expected ones.
Next, we tested the ability to cold-start, i.e., the circuit
is able to start even if the load capacitor C L is completely
discharged. When the RMS acceleration is 1.73 g, Fig. 14(a)
shows that the voltage Vrect increases steadily toward 5 V,
which is the clamp voltage of the ESD circuit of the pad.
However, when the acceleration is reduced to 1.67 g, the
voltage fails to reach the steady state value or equally fails
to cold-start. It should be noted that the circuit can operate
correctly well below 1.67 g once it has started due to the
reason stated in Section IV-E. When the load resistor R L
(= 100 k) is removed, the circuit is able to cold-start under
0.71 g as shown in Fig. 14(b). However, when the acceleration
is reduced further to 0.63 g, the cold-start operation becomes
unstable and fails to charge up the load capacitor C L steadily.
Fig. 15 shows the power delivered to the load resistor
ranging from 30 k to 310 k under RMS acceleration of
0.7 g with the vibration frequency of 144 Hz. A current
sensor instead of a series 10  resistor is used to measure
the input current (equally the inductor current) to the circuit
for the rest of the experiments, and it reduces power loss for
the current measurement and hence improves the efficiency.
The peak open-circuit voltage of the PE cantilever is observed
as 4.9 V. The figure also shows the power delivered by our
previous design in [31] (which resets the internal capacitor
voltage) called Synchronous Switching (SS) and that for a
full-bridge (FB) rectifier implemented with Schottky diodes.
The power delivered to the load resistor increases as the load
resistor increases initially for the three circuits and then starts
to decrease after R L for about 90 k. As analyzed in [2], the
result verifies existence of an optimal resistance value for the
three circuits.
Among the three circuits, the proposed circuit achieves the
highest power for the entire load range. The proposed circuit
harvests maximum power of 136 W under R L around 90 k.
The maximum powers of the SS circuit and the FB rectifier
are 118 W and 63.5 W, respectively. So the proposed
circuit increases the maximum power harvested by 1.2 and
2.1 times, respectively, when compared against those of the
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

10 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS

Fig. 13. Measured waveforms of the PE cantilever voltage and the inductor current (a) voltage V B A across the PE cantilever and the inductor current i L ,
(b) close up of the rising edge, (c) close up of the falling edge.

Fig. 14. Cold-start of the circuit (a) measured voltage Vrect with the load resistor R L = 100 k, (b) measured voltage Vrect without a load resistor.

generator and the reference current generator blocks) alone is

Fig. 15. Power delivered to the load for three different types of circuits,
proposed one, the synchronizing switching (SS) circuit [31], and the full-
bridge (FB) rectifier.
SS circuit and the FB rectifier. Increase of the power is due
to the adoption of the SSHI method with the optimal flipping
time and a simple controller.
The measured power dissipation of the entire circuit is about
24 W, while power dissipation of the controller (the clock
only 1.5 W in simulation. The two active diodes, i.e., M1
and M2 and the two associated op-amps, cause major power
dissipation of on average 22.4 W in simulation. As noted
in the previous section, adoption of the typical topology for
connection of the two active diodes, i.e., the pMOS transistor
on the top and the nMOS transistor on the bottom, can reduce
the power dissipation to about half (precisely 11.5 W) at the
cost of potentially lower reliability. In fact, the topology is
adopted for our previous design in [31].
The power conversion efficiency of the proposed circuit
is defined as the ratio of output power delivered to the
load R L to the input power to the circuit (or the power
delivered from the PE cantilever) in this paper. Fig. 16
depicts the power conversion efficiency of the proposed circuit
under RMS acceleration of 0.7 g with the vibration frequency
of 144 Hz.
As R L increases from 20 k, the power conversion effi-
ciency also increases and reaches the maximum of 85% at
R L = 60 k. It is interesting to note that the load resistance
for the highest conversion efficiency does not coincide with
that of the maximum power delivered to the load. This
may be due to increased power losses across the two active
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
WU et al.: A SELF-POWERED AND OPTIMAL SSHI CIRCUIT INTEGRATED WITH AN ACTIVE RECTIFIER FOR PIEZOELECTRIC ENERGY HARVESTING
TABLE I
C OMPARISONS OF R ECENT PE E NERGY H ARVESTING C IRCUITS
Fig. 16. Measured power conversion efficiency of the proposed circuit.
diodes and the two switches under the delivery of maximum
power.
Table I summarizes performance and characteristics of
recent, state-of-the-art PE energy harvesting ICs whose focus
is efficient implementation of the SSHI method or its vari-
ations. The figure of metric (FoM) in (15) compares the
measured power Pout delivered to the load of a circuit under
consideration against the theoretical power delivered to the
optimal resistive load connected to the PE transducer through
an ideal full-bridge rectifier [13], [14]
Pout
FoM = 2
(15)
f P C P Voc
Power conversion efficiency is another metric whose reference
power is the measured power delivered from the PE cantilever
to the circuit. The efficiency of the proposed circuit shown
11
in Fig. 16 adopts the latter metric. Whichever metric one
may adopt, it is difficult to make a fair comparison of the
performance due to differences such as processing technology,
PE transducer type, inductor size, power level, and amplitude
and frequency of input and output voltages. For example, when
the inductor size increases from 22 H to 820 H in [14], the
FoM increases from 130 to 300 as shown in Table 1.
Among the five designs shown in Table 1, Ramadass and
Chandrakasan considered an inductor (= 22 H) smaller than
the one (= 220 H) used for the proposed circuit in [14], and
the proposed circuit achieves a higher FoM among the two.
Only [17] and the proposed circuit do not require an external
adjustment for optimal flipping times. The proposed circuit
achieves a higher FoM than [17]. It is interesting to note that
the inductor size of [17] is larger than that for the proposed
circuit. Only [13] and the proposed circuit report the power
conversion efficiency of the entire circuit, and the proposed
one has a far higher efficiency than [13]. As noted earlier,
the two active diodes, M1 and M2 and the two associated
op-amps shown in Fig. 6, cause the major power dissipation
for the proposed circuit and an increased diode voltage drop
across the active diodes. Swapping the two diodes for the
proposed circuit reduces the power dissipation substantially
and the diode voltage drop, which would lead to a higher
FoM and the conversion efficiency for the proposed circuit at
the cost of potentially lower noise immunity. In summary, the
key advantage of the proposed design is a simple controller
through integration of an SSHI circuit and an active rectifier,
which reduces the power dissipation of the circuit.
VI. C ONCLUSION
This paper presents a self-powered piezoelectric energy
harvesting circuit, which integrates an SSHI circuit and an
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
12
active rectifier. The proposed SSHI circuit inserts an active
diode in each resonant loop, which ensures flipping of the
capacitor voltage at optimal times and eliminates the need
to tune the switching time. The diodes of the SSHI circuit
are also used as a rectifier to further simplify the con-
troller. The dual role of the diodes exploits the fact that
the SSHI operation and rectification do not occur at the
same time. The key advantage of the proposed circuit is a
simple controller, which leads to low power dissipation to
result in high efficiency. The circuit was fabricated in silicon-
only BiCMOS 0.25 m technology with the die size of
0.98 0.76 mm2. Measurements on the operation and per-
formance of the proposed circuit were performed with a PE
cantilever and an electrodynamic shaker. Measured results
indicate that the proposed circuit increases the maximum
power harvested by 1.2 and 2.1 times, respectively, when com-
pared against those of the synchronous resetting (SS) circuit
and a full-bridge (FB) rectifier. It achieves power conversion
efficiency of 85% and output power of 136 W. The proposed
circuit dissipates about 24 W, while the controller alone only
1.5 W.
ACKNOWLEDGMENT
The authors greatly appreciate the reviewers, whose feed-
back was invaluable to improve the technical quality, as
well as the presentation, of this paper. Although they remain
anonymous, the authors would like to give due credit for their
contributions to this paper, of which they deserve most.
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Liao Wu received the M.S. degree in computer sci-
ence and technology from Hunan University, Chang-
sha, China, in 2010, where he is currently working
toward the Ph.D. degree in computer application
technology. From 2013 to 2015, he was a Reserach
Scholar with the Multifunctional Integrated Circuits
and Systems Group, Virginia Tech, VA, USA.
From 2010 to 2012, he was an Engineer with
the Jingjia Mirco Corporation, China. His current
research interests include low power circuit design
and energy harvesting circuits.
Xuan-Dien Do was born in Vietnam, in 1985.
He received the B.S. degree from Hanoi Univer-
sity of Science and Technology (HUST), Hanoi,
Vietnam in 2008 and the M.S. and Ph.D. degrees in
electrical engineering from Korea Advanced Institute
of Science and Technology (KAIST), South Korea,
in 2015. He is now with Siliconworks, Daejeon,
South Korea, where he is engaged in CMOS analog
and power management integrated circuit design.
13
Sang-Gug Lee (M09) Sang-Gug Lee was born
in Gyungnam, Korea in 1958. He received
the B.S. degree in electronic engineering from
Gyungbook National University, Daegu, South
Korea, in 1981, and the M.S. and Ph.D. degrees
in electrical engineering from University of Florida,
Gainesville, FL, USA, in 1989 and 1992, respec-
tively. In 1992, he joined Harris Semiconductor,
Melbourne, FL, USA, where he was engaged in
silicon-based RF IC designs. From 1995 to 1998,
he was with Handong Global University, Pohang,
South Korea, as an Assistant Professor in the School of Computer and
Electronic Engineering. From 1998 to 2009, he was with Information and
Communications University, Daejeon, South Korea as an Assistant, Associate,
and Professor in the School of Engineering. Since March 2009, he is with
KAIST, Daejeon, as a Professor in the Department of Electrical Engineering.
His research interest is the silicon technology-based (especially in CMOS)
radio transceiver designs, lately focusing on ultra-low power and extreme
high frequencies (that is, terahertz) implementations. In the past few years,
his research interests also include other analog integrated circuit designs such
as display semiconductors, power management ICs, and automotive ICs.
From 2005 to 2009, he served as a Technical Committee Member of IEEE
ISSCC in the Wireless Communication Technology Committee. From 2005
to 2010, he served as a Research Director of Auto-ID Lab Korea. In 2007,
his laboratory was selected as a National Research Laboratory. Since 2012,
he is serving as a director of Future Promising Fusion Technology Pioneer
Center, leading a research group in the area of silicon technology based THz
IC design.
Dong Sam Ha (M86SM97F08) received a
B.S. degree in Electrical Engineering from Seoul
National University, Seoul, South Korea, in 1974,
and M.S. and Ph.D. degrees in electrical and com-
puter engineering from the University of Iowa, Iowa
City, IA, USA, in 1984 and 1986, respectively.
Since Fall 1986, he has been a faculty member
with the Bradley Department of Electrical and Com-
puter Engineering, Virginia Polytechnic Institute and
State University (often called Virginia Tech), Blacks-
burg, VA, USA, where he is a Professor and Director
of the Multifunctional Integrated Circuits and Systems (MICS) Group com-
posed of five faculty members and about 30 graduate students. Along with
his students, he has developed four computer-aided design tools for digital
circuit testing and CMOS standard cell libraries. The source code for the four
tools and the cell libraries have been distributed to about 380 universities and
research institutions worldwide each.
His research interests include analog and RF circuits and systems. Currently,
his group focuses on power management circuits for energy harvesting and
high-temperature RF circuits and systems for down hole communications.