Assignment 2: RFIC

1) The negative resistance LC oscillator is shown in Fig below. The component

values are L=5Nh, C=2.5Pf, Q=5 and nCOX=110.A/v2.

a) Calculate the frequency of oscillation.[10]

b) Calculate the value of negative resistance provided by the cross-coupled
NMOS transistor pair to support oscillation.[10]
c) What is the W/L ratio of M1 and M2 to achieve the required negative
resistance?[10]
2) A single-transistor inductor-feedback oscillator is shown in figure below. Find
the expression for the frequency of oscillation and the value of gmRLnecessary
for oscillation. Assume that output resistance of the transistor is negligible.[20]
3) In general any LC oscillator can be modeled for noise using resistance approach
as shown infigure below.
a) Derive the expression for the phase noise assuming that oscillator is a linear
time invariant system (LTI).[15]

b) The real oscillator phase noise looks like as shown in figure below. Suggest
themodification in the above expression to take 1/f 3 slope and the flat noise
part intoaccount.[15]

c) Why the modified formula is not directly applicable to real oscillators to

practically calculate the noise?[10]
4) Which of the following (a), (b), (c) and (d) circuit oscillates? State the reason in
terms offrequency dependent phase shift and DC phase shift.[30]

5) A linear model of a PLL with an active loop filter is shown in figure below.
a) Derive an expression for the transfer function of the VCO (i.e. out/vout,
where voutand outare the control voltage and the output phase of the VCO,
respectively).[10]
b) Derive the noise transfer function of the VCO (i.e. out/vnoise).[10]
c) The block diagram of a charge pump PLL is shown in Fig. 5(b). S1 and S2are
idealswitches and I1 and I2 are ideal current sources, where I1=I2=IP. Does
this PLLoperate correctly? If your answer is yes, discuss how it works and
explain thefunction of each block, and if your answer is no, just explain
the reason and give asolution to make it functional.[10]

Fig. 5a.A linear model of a PLL.

Fig. 5b.A charge-pump PLL.

6) What are the different layout techniques :
a) To reduce mismatch problem in the Analog layout.[5]
b) To reduce parasitic capacitance and noise in the RF layout.[5]
7) Draw the layout and write the pattern of the below figure.

Fig. 7(a,b). Transistor schematic.

a) Assume transistor A have 16 fingers and transistor B have 4 fingers (W

and L of both the transistors are same). So make the layout of both the
transistors in the interdigitated format and write the pattern.[10]
b) Assume transistor A have 18 fingers and transistor B have 18 fingers
(W and L of both the transistors are same). So make the layout of both the
transistors in the common centroid format and write the pattern (placement
of the transistors should be in 4 rows).[10]
c) Draw the capacitor layout of the below figure, where C5=12pf,
C4=6pf,C3=4pf,C2=2pf, and C1=1pf. The unit capacitance size in layout
should be 1pf.[20]

Fig. 7(c).Transistor schematic.