GEETANJALI INSTITUTE OF TECHNICAL STUDIES

BRANCH: ELECTRICAL ENGINEERING

SUBJECT :DIGITAL ELECTRONICS(4EE2)
YEAR/SEMESTER : II YEAR / IV SEM.
SECOND INTERNAL EXAM
TIME: 1:30 Hr MM: 20

Note: Attempt three questions selecting one from each unit.

UNIT - I
6
Q.1 Simplify the Boolean function
F(A,B,C,D) = m(1,3,7,11,15) + d(0,2,5)
Or

Simplify Y = m(3,6,7,8,10,12,14,17,19,20,21,24,25,27,28) using

Q.2 the K-map method
6

UNIT II
Draw the circuit symbol and truth table for a four-input OR gate.
Draw the circuit symbol and truth table for a four-input OR gate. 7
Q.3
Explain the parameters used to characterize logic families?
Or

Q.4
Explain RTL with circuit diagrams? 7

UNIT III
Q.5
Explain using truth tables a full subtractor ? 7
Or

Q.6 What is a multiplexer ? Explain 8:1 multiplexer with neat diagrams? 7

 GEETANJALI INSTITUTE OF TECHNICAL STUDIES
BRANCH: ELECTRICAL ENGINEERING
SUBJECT :DIGITAL ELECTRONICS(4EE2 )
YEAR /SEMESTER : II YEAR / IV SEM.
SECOND INTERNAL EXAM

TIME: 1:30 Hr MM: 20

Note: Attempt three questions selecting one from each unit.

UNIT I

Q.1 Explain a five variable K map? 6

Or

Q.2 What do you mean by dont care combinations? 6

UNIT II

Q.3 Explain a TTL NAND Gate with ckt diagrams? 7

Or

Q.4 What are the characteristics of CMOS? 7

UNIT III

Q.5 What is demultiplexer? Explain 1:16 Demux with truth tables and 7
diagrams?
Or
Q.6 Explain a full Adder? 7
 GEETANJALI INSTITUTE OF TECHNICAL STUDIES
BRANCH: ELECTRICAL ENGINEERING
SUBJECT :DIGITAL ELECTRONICS(4EE2 )
YEAR /SEMESTER : II YEAR / IV SEM.
SECOND INTERNAL EXAM

TIME: 1:30 Hr MM: 20

Note: Attempt three questions selecting one from each unit.

UNIT I

Q.1 Obtain the minimal SOP expression for the function 7

Y=m(1,5,7,13,14,15,17,18,21,22,25,29)
Or
Q.2 Explain a half adder? 7

UNIT II

Q.3 Explain 4:1 multiplexer? 7

Or

Explain DTL with diagram? 7

Q.4

UNIT III

Q.5 Write short notes on any three 6

(i) Noise immunity
(ii) Fan out
(iii) Fan in
(iv) Transition times
(v) Propagation delays