Electronic Equipment Testing

Prof.dr.eng. Radu Vasiu

radu.vasiu@cm.upt.ro
radu.vasiu@etc.upt.ro
 Administrative Problems
Contact: room A210
Laboratory: B227
For lab.:
Asist.dr.eng. Andrei Ternauciuc, andrei@cm.upt.ro,
lect.dr.eng. Mugur Mocofan, mugur@cm.upt.ro
Laboratory works
Small project: signature analyzer
Activity: 40%
Examination: written (theory 50% and problems 50%)
60% to the final mark
Exam pass: minimum 5 to theory and minimum 5 to
problems
 Content
General remarks regarding the testing process
Testing at the level of digital integrated circuit chip:
parametric testing, functional testing
Testing at the level of electronic board: test stimulus
vectors generation, test sequences generation
Testing at the level of equipment
Testing digital communication networks
Automatic test equipment (autotest)
Fault tolerant equipment design
Fault location on communication cables
Nonlinearity in communication systems
 References
Vasiu R., Testarea echipamentelor electronice, Ed. Orizonturi
Universitare, Timisoara, 2001
Abramovici M., Breuer M. A., Friedman A. D., Digital Systems
Testing and Testable Design, IEEE Press, New York, 1990
Catuneanu V. M., Bacivarof A., Structuri electronice de inalta
fiabilitate. Toleranta la defectari, Ed. Militara, Bucuresti, 1989
Vladutiu M., Tehnica testarii echipamentelor de calcul si evaluarea
performantelor, Institutul Politehnic Traian Vuia Timisoara, 1986
Witte R. A., Electronic Test Instruments. Theory and Applications,
Prentice Hall, Englewood Cliffs, New Jersey, 1993
 Ch.1. GENERAL REMARKS REGARDING THE
TESTING PROCESS

Necessity of the testing process

Testing and inspection procedures

Specificity of electronic equipment, especially digital
large electronic systems are divided on smaller electronic
boards, mainly from mechanical reasons imposible to identify
a single function for each electronic board
digital systems: outputs checking doesnt give relevant
information - necessity for testing methods that are able to
correlate the output signal wave to the functioning status of the
circuit
focus on the ellaboration of methods for data generation, so that
applied to the circuits input(s) will facilitate testing it: test
stimulus vectors generation
 Ch.1. GENERAL REMARKS REGARDING THE
TESTING PROCESS

Place of the testing procedures in the production process

tests are done at the level of the electronic components producer, as
well as at the level of the user

DISCRETE COMPONENTS Component level testing (Test 1)

EQUIPPED ELECTRONIC BOARD

Board level testing (Test 2)
(components + connections)

EQUIPMENT Equipment level testing (Test 3)

Ch.1. GENERAL REMARKS REGARDING THE
TESTING PROCESS
 Ch.1. GENERAL REMARKS REGARDING THE
TESTING PROCESS

Architecture of the automatic test equipment

BM
UT Unit under Test
TSG Test Stimuli Generator
REB Responses Evaluation
I/O D Computer
Block
CM Connection Matrix
I/O D Input/Output
TSG CM REB
Devices
BM Back-up Memory
UT
 Ch.1. GENERAL REMARKS REGARDING THE
TESTING PROCESS

Tester with connection through nail bed

connectors
Tester with connection through the external
connector of the tested unit

Parametric testers and logical testers

Component testers

Economic implications
 Ch.1. GENERAL REMARKS REGARDING THE
TESTING PROCESS

Testability design
implementation of special features for testing
the concept of design for testability is applied starting
with the initial designing phase of the i.c. up to the
design of the complex electronic equipment
includes concepts as:
signalisation of the status of some signal lines or indicators
breack-up of the reaction lines in order to facilitate separate
testing for each block, without the possibility of an error to be
propagated back through many blocks due to the reaction
conditioning of the input of some component blocks in order to
facilitate the use of some special test signals
Electronic Equipment Testing

2. Integrated circuit level testing

2.1. Parametric testing
2.1.1. Static parameters testing
 2.1.1. Static parameters testing
General structure of an IC automated tester
 2.1.1. Static parameters testing
TSG - Test Stimulus Generator
CM - Connection Matrix
TC - Tested Chip
REB - Responses Evaluation Block
CU - Control Unit
IP - Input Pins
OP - Output Pins
TS - Test Stimulus
R - Responses
C - Commands
 2.1.1. Static parameters testing
The static parameters of an IC are:
- Input and output voltages
- Input and output currents
They are stable during the test. A time should be given from
powering the IC, in order to allow stabilisation of the transition
factors.
Test should be carried out under the less favorable conditions:
power supply value, circuits charge, etc.
TSG is formed by a number of Programmable Voltage Sources
(PVS) and Programmable Constant Current Generators (PCCG)
 2.1.1. Static parameters testing
Testing the logic "1 at the output:

0.8 V = maximum value accepted as logic 0 at the input

4.75 V = minimum value accepted for the power supply voltage
The PCCG simulates the maximum of 10 equivalent TTL charges
 2.1.1. Static parameters testing
Testing the logic "0 at the output:

2 V = maximum value accepted as logic 1 at the input

4.75 V = minimum value accepted for the power supply voltage
The PCCG simulates the maximum of 10 equivalent TTL charges
 2.1.1. Static parameters testing
PVS realization:

RR programms the numerical value of the voltage

Ri programms the domain of the voltage
 2.1.1. Static parameters testing
Structure of the RR:

RR serves for programming the value of the programmed voltage

Ex: for KH3, KH1, KH0, KT3, KU3, KU1 switched on, we have
RR = 475 R
 2.1.1. Static parameters testing
Structure of the Ri:

Ri serves for programming the domain of the programmed voltage.

 2.1.1. Static parameters testing
The value of a Programmable Voltage Source is set-up through
programming a register, called Status Word Register (SWR).
For each Source, it has a part for the numerical value (12 bits
units, tens and hundreds) and one for the domain (one bit). In
total, a SWR could have about 100 bits.
Each range of the register is commanding (directly or through a
transistor) a micro-relay, having the contacts as part of the RR
or Ri resistors.
2.1.1. Static parameters testing
 2.1.1. Static parameters testing
Normally, 7 stimulus sources (voltage and currents) are enough.
Exemple for the allocation of the stimulus devices to the pins of
a 32 pin IC.
A numerical code is given to each stimulus device, 3 bits are
programmed into a register for each pin. The decoded value
shows wich device is attached to each pin.
The Evaluation Device is singular, so the code of the pin where
it should be attached has to be decoded.
For the 32 pin IC, a decoder 1 : 32 (5 bits code) has to be used.
 2.1.1. Static parameters testing
Programming the stimulus devices:
 2.1.1. Static parameters testing
REB allocation to a pin:
 2.1.1. Static parameters testing
Exemple for a the realisation of the Connection Matrix for a 32 pins
Integrated Circuit:
Electronic Equipment Testing

2. Integrated circuit level testing

2.1. Parametric testing
2.1.2. Dynamic parameters testing
 2.1.2. Dynamic parameters testing
Dynamic parameters:
Transition time: ttLH, ttHL
Propagation time: tpLH, tpHL
2.1.2. Dynamic parameters testing
 2.1.2. Dynamic parameters testing
Test stimuli generator:
use of digital programmable pulse generators: fronts, length,
amplitude, polarity, filling factor, etc

Test conditions:
evaluation in the worst functional case:
minimum power supply
maximum charge, etc
precision in determining the moment when a voltage arrives
to a certain threshold (voltage discriminators)
precision in determining the stable values of the voltages on 0
or 1 logic (sample and hold circuits)
 2.1.2. Dynamic parameters testing
VOLTAGE DISCRIMINATORS
Determination of the moment when the input or output voltage of the circuit is
passing through a predetermined value defined as fixed or percentage

- PVS = Programmable voltage source

- UT = Threshold voltage
- V0 = Voltage to be discriminated
- C = Comparator
- FFC = Flip-flop circuit
- Val = Validation input
- V0D = Discriminated voltage
 2.1.2. Dynamic parameters testing
SAMPLE AND HOLD CIRCUITS
Precise determination of some fixed values (i.e. 0% or 100% of the pulse
value)

S = Sampling impulse
NIG = Needle impulse generator
SG = Sampling gate
V0 = Sampling voltage
IEC = Impulse extension circuit
ADC = Analogue-digital converter
 2.1.2. Dynamic parameters testing
Exemple of a schematic diagram for testing ttLH
 2.1.2. Dynamic parameters testing

Discussions:

Key factors for precision (counter frequency,

discriminators, etc)
Modifications according to how the thresholds are
defined
Modifications for testing: ttHL, tpLH, tpHL
 2.1.2. Dynamic parameters testing
Quick determination of the tpHL characterization testing,
circuits selection
Electronic Equipment Testing

2. Integrated circuit level testing

2.2. Functional testing
2.2.1. Memory chips functional testing
 2.2. Functional testing
Purpose: to determine if the logical output value of an IC
doesnt correspond to the function of the circuit
- verification of the truth table
- many combinations to be used
- not all are relevant in order to put in evidence a fault
A B Y Exemple: NAND gate, A-s.a.1
0 0 1
0 1 1 - Only the second combination is
1 0 1 able to locate the fault
1 1 0
 2.2.1. Memory chips functional testing
Types of faults:
- simultaneous writing in several cells
- impossibility to write into some locations
- incorrect access to some memory locations
- increase of the access time
- loose of data between two successive regeneration commands for MOS
dinamic memories
- pattern sensitivity: differences between the written and read information, only
on specific content of the memory
Exhaustive testing of all combinations is difficult and time consuming
Memory refresh is an important parameter to be taken into consideration
Refresh interval for RAM dynamic memories has to be calculated
Worst case is that of a memory organized as a single column, due to the fact
that each refresh impulse refreshes only one location, not the whole raw
Bit models have to be generated.
2.2.1. Memory chips functional testing

The MASEST model

Mem charging Loc.0 testing Loc.1 testing ... Loc.N-1 testing Sequential testing

Loc N-1 1 1 1 1 1

Loc N-2 0 0 0 0 0
. . . . .
. . . . .
. . . . .

...
Loc 2 0 0 0 0 0

Loc 1 1 1 1 1 1

Loc 0 0 0 0 0 0

N m.c. 3 m.c. 3 m.c. 3 m.c. N m.c.

Total duration: Dt=2(N+3N+N)=10N m.c.

Refresh interval: Dmax=3N-5 m.c.
 2.2.1. Memory chips functional testing
The MASEST model
Steps:
I. Memory write with alternant 0, 1, 0, 1, succession
- duration: N memory cycles (N m.c.)
II. Iterative testing of each location, by:
- read current location
- read complementary location
- read current location
- duration: 3N m.c.
III. Successive read of all memory locations
- duration: N m.c.
IV. Procedure repeating for the complementary succession written initially in
the memory: 1, 0, 1, 0,
- duration: 5N m.c.

Advantages: easy to realize the BER (response evaluation block) of the

automatic test equipment.
2.2.1. Memory chips functional testing
The MARCH model
Memory charge Read, test, write complement Read, test, write complement

Loc N-1 0 0 01 10 0

Loc N-2 0 0 1 1 0

. . . . .
. . . . .
. . . . .

...
Loc 2 0 0 1 1 0

Loc 1 0 0 1 1 0

Loc 0 0 01 1 1 10

N m.c. 2 N m.c. 2 N m.c.

Total duration: Dt=2(N+2N+2N)=10N m.c.

Refresh interval: Dmax=4N-4 m.c.
 2.2.1. Memory chips functional testing
The MARCH model
Steps:
I. Memory write with initial 0, 0, 0, 0, succession
- duration: N memory cycles (N m.c.)
II. Iterative testing of each location, from 0 to N-1 by:
- write 1 into the current location
- read current location
- duration: 2N m.c.
III. Iterative testing of each location, from N-1 to 0 by:
- write 0 into the current location
- read current location
- duration: 2N m.c.
IV. Procedure repeating for the complementary succession written initially in the
memory: 1, 1, 1, 1,
- duration: 5N m.c.
2.2.1. Memory chips functional testing
The WAKPAT model
Memory charge Test loc. 0 Test loc. (N-1)

Loc N-1 0 0 0 01
10
Loc N-2 0 0 0 0
0
. . . .
. . .
. .
. . .
. .
.
...
Loc 2 0 0 0 0
0
Loc 1 0 0 0 0
0
Loc 0 0 01 10 0
0

N m.c. (N+2) m.c. (N+2) m.c.

Total duration: Dt=2[N+N(N+2)]=2N2+6N m.c.

Refresh interval: Dmax=N-1 m.c.
 2.2.1. Memory chips functional testing

The WAKPAT model

Steps:
I. Memory write with initial 0, 0, 0, 0, succession
- duration: N memory cycles (N m.c.)
II. Iterative testing of each location, from 0 to N-1 by:
- write 1 into the current location
- read all locations successively, starting with the one after the
current location and finishing with the current location
- re-write 0 into the current location
- duration: N(N+2) m.c.
III. Procedure repeating for the complementary succession written
initially in the memory: 1, 1, 1, 1,
- duration: N+N(N+2) m.c.
Remarks: duration long test
2.2.1. Memory chips functional testing
The GALPAT model
Memory charge Test loc. 0 Test loc. (N-1)

Loc N-1 0 0 0 01 10

Loc N-2 0 0 0 0 0
. . . . .
. . . . .
. . . . .

...
Loc 2 0 0 0 0 0

Loc 1 0 0 0 0 0

Loc 0 0 01 10 0 0

N m.c. 2N m.c. 2N m.c.

Total duration: Dt=2(N+2N2)=4N2+2N m.c.

Refresh interval: Dmax=2N-2 m.c.
 2.2.1. Memory chips functional testing
The GALPAT model
Steps:
I. Memory write with initial 0, 0, 0, 0, succession
- duration: N memory cycles (N m.c.)
II. Iterative testing of each location, from 0 to N-1 by:
- write 1 into the current location
- read all locations successively, inserted with the current location
- re-write 0 into the current location
- duration: 2N m.c.
III. Procedure repeating for the complementary succession written
initially in the memory: 1, 1, 1, 1,
- duration: N+2N2 m.c.
Remarks: duration long test
 2.2.1. Memory chips functional testing

Other memory test models:

- GALCOL (Galpat on columns)
- DIAPAT (sequences on diagonal)
- GALTDIA (Galpat on diagonal)
- WAKCOL (Wakpat on columns)
- HAFCOL (test on half of columns)
- CHECKCOL (checking on columns)
- ROM memory testing
- EPROM memory testing
- RAM static memory testing
Electronic Equipment Testing

2. Integrated circuit level testing

2.2. Functional testing
2.2.2. Microprocessors, microcontrollers,
signal processors functional testing
 2.2.2. Processors functional testing
An automatic tester for processors should contain the
minimum structure of a microsystem
The diversity of the processors make it impossible to
build a tester for all processors: number of pins, supply
voltage, functions, etc
Possible faults:
Incorrect function at the level of instructions
Faults at the level of registries
Instruction pattern sensitivity
The first two can be checked by running all instructions
The third can only be detected by knowing the detailed
internal scheme, available only for the producer of the
processor.
The user can only check if such a fault doesnt appear in a
typical application program.
2.2.2. Processors functional testing

Testing methods:
1. Make use of standardized processor (known as
being functionally correct)
- Comparing method
- Bit model recognition method
1. Do not make use of standardized processor
- Simulation method
- Modular activation method
 2.2.2. Processors functional testing

Comparing method
- Simultaneously activates a standard processor and
the tested one, using the same test program
Advantage: very simple
Disadvantages:
- very dependent on the capacity of correct
functioning of the standard processor
- low flexibility
2.2.2. Processors functional testing
Bit model recognition method
Minimizes the dependence on the functioning
capacity of the standard processor
The test program is running once on the
standard processor, the results are memorized
and the results on the test processor are
compared to the memorized one
2 steps:
- Bit model generation
- Bit model recognition
2.2.2. Processors functional testing
Bit model generation

CU CM SP
S-P
PROM

DM
CU Control Unit
CM Connecting matrix
SM Standard processor
DM Data memory
2.2.2. Processors functional testing
Bit model recognition
CU CM TP
PT
REB

DM

TP Tested processor
REB Response evaluation block
 2.2.2. Processors functional testing
Simulation method
- Supposes to know the detailed internal electronic
scheme of the processor, at transistor level
- Simulates all possible internal faults or
combination of faults
- Determines processors behaviour for each fault /
combination of faults
- Can only be applied at the producer end
 2.2.2. Processors functional testing
Modular activation method
- The processor is devided on hierarchical levels (both
functional and hardware)
- The test is done based on a self-test program
- The program starts with the basic level
- Each tested level can be used for testing superior levels
- In order to start, a minimum level of components and
functions should be correct! - KERNEL
- The kernel should include: initialization circuits, program
counter, address bus, data bus, instruction decoder, clock
circuit
 2.2.2. Processors functional testing

A possible testing strategy:

Test CARRY

Test registers

Test ACCU

Test ALU

Test subroutines

Test pile
 2.2.2. Processors functional testing

Test of the kernel:

Code
NOP
P Counter Comparator

Data bus 8/16 bit 16/20 bits

10/20 bits

CLOCK
LED

Address
bus
 2.2.2. Processors functional testing
If the kernel test is passed, the following circuits are
functionally corrects:
- Clock circuit
- Initialization circuit
- Program counter
- Address bus
- Data bus partially
- Instruction decoder partially
- Instruction register partially
Electronic Equipment Testing

4. Equipment level testing

4.1. Digital telecommunication networks
testing
 4. Generalities
When all components of an equipment are physically
located in the same place, the faults are to be checked at
the connection level: wires between electronic boards,
connectors, etc
If connections are ok, then the test on electronic board
level should be repeated
When the equipment is distributed from a physical point
of view, checks are more difficult to be carried out
Sometimes it is necessary to have teams of technicians
in different places, able to discuss through a separate
communication technology, performing separate tests
and interpreting results together
It is a great benefit if a method can be found, in order to
perform at least part of the test on the whole equipment
from a single place
Ex.: telecom networks
 4.1. Digital telecommunication
networks testing
General block diagram of a digital telecom network:

Coax cable
Primary Transmission Optical fibre Transmission
MUX MUX TERMINAL Microwave TERMINAL
(emission) (terestrial, (reception)
space)
 4.1. Telecom network testing
Bit Error Rate BER
- Ratio between the number of errored bits and the
total number of transmitted bits
BER estimation:
- in-service
- out-of-service
The test signal is a pseudorandom binnary
sequence, standardized through the 0.151 CCITT
recommendation
 4.1. Telecom network testing

Testing principle:
 4.1. Telecom network testing
Test generator:
+

SHIFTING REGISTER
PRS
CODER transmission line

clock

Tact Gen.

PRS Pseudo-Random Sequence

2N-1 symbols, according to Rec. 0.151
- for low speed networks N=15
- for high speed networks N=23
 4.1. Telecom network testing
Avoiding the lock on 0 of the shifting register:

1
. 2
.
N

SHIFT REGISTER

... . .
1 2 N
 4.1. Telecom network testing
Error detector:

+
Clock

DECODER SHIFTING REGISTER

Data
+

ERROR COUNTER

- use of the same clock

 4.1. Telecom network testing
Synchronization:

Data
SERIAL/PARALLEL CONV.

1 2 N
.. .

SINCRO WORD DETECTION

SINCRONIZATION LOGIC

Clock
PRS GENERATOR
 4.1. Telecom network testing
Transmissions quality appreciation:

UNACCEPTABLE
log BER
transm.
10-3

DEGRADED
transm.
10-6

ACCEPTABLE
transm.
10-10
EXCELLENT
t transm.
 4.1. Telecom network testing

Regenerators testing:

TRANSM. TRANSM.
TERM. REG REG TERM.

TEST ERROR
GEN. DETECTOR
 4.1. Telecom network testing
Diaphony:

TEST LINE Cable sim.

GEN. CODER
REGE LINE ERROR
NERA DEC DETECTOR
NOISE TOR ODE
GEN. FILTER
I R
 4.1. Telecom network testing
Simulation of the phase errors:

SINCRO

Cable sim.
Clock PHASE TEST REG. OSC.
MODULATOR GEN.

OSC.
L.F.
Electronic Equipment Testing

Prof.dr.eng. Radu Vasiu

radu.vasiu@cm.upt.ro
radu.vasiu@etc.upt.ro
 Autotesting Equipment
General problems:
rapid development of the VLSI circuits
increase of complexity
large amounts of data are transferred and processed
current tendency is to include testing facilities on the
chip or module, so that testing functions are taken by the
testing hardware itself
autotesting methods
use of error detecting and error correcting codes
Examples:
Signature analysis
BILBO (Built-in Logic Block Observation)
 Signature Analyser
Principle: data information flow compression
use of pseudorandom sequences
long sequences are compressed into a fix length
information
compression result = signature
easy to recognize
easy to interpret by comparing it with a control signature, that
corresponds to proper functionning
according to how the data flow is collected:
Serial signal analysers
Parallel signal analysers
Block scheme Signature Analyzer
UT = Tested Unit (Unitate Testata)
BSD = Data Probes Block (Blocul Sondelor de Date)
MT = Temporary Memory (Memorie Tampon)
BSC = Control Probes Block (Blocul Sondelor de Control)
BSF = Front Selection Block (Bloc Selectie Front)
BCF = Window Control Block (Bloc Control Fereastra)
GSPA = Pseudo-Random Signal Generator (Genertor de Secvente
Pseudo-Aleatoare)
RMSC = Current Signature Memorization Register (Registru de
Memorare a Semnaturii Curente)
BDA = Decoding and Display Block (Bloc Decodificare si Afisare)
RMSA = Previous Signature Memorization Register (Registru de
Memorare a Semnaturii Anterioare)
BDSI = Unstable Signature Detection Block (Bloc de Detectie a
Semnaturii Instabile)
BASI = Unstable Signature Display Block (Bloc de Afisare a Semnaturii
Instabile)
BA = Autotesting Block (Bloc de Autotestare)
Signature
generated after processing collected data into the Pseudo-
Random Signal Generator
fixed length: generally 16 bits, decoded in groups of 4
bits, displayed as alphanumeric characters on 7 segment
LEDs
small alphabet letters are avoided: b, c, d.
ambiguous capital letters avoided: B, D, G, I.
usually used instead: C, E, F, H, P, T, U.
Signature should be simple to be recognized from the
distance, un-ambiguous and Stable
stability is given by the repetitivness of the autotesting
program, i.e. repetitivness of the WINDOW and collected
sequence of information
 Signature generation:
after processing within the GSPA shifting
register with reaction

based on the polynom G (x) = x4 + x3 + 1

implementation of a cyclic code, able to
detect and correct errors, irreductible
polynomial, minimum number of terms (as
each term means a reaction)
 Signature generation:

its serial

- Longer streams (16 bits) = use of a 16 degree polynomial, i.e.

G (x) = x16 + x12 + x9 + x7 + 1

its parallel
 Signature analysis testing:

based on comparing the generated signature to the

correct signature
correct signature can be calculated or obtained on
a standard board
 Advantages:
small costs;
fast processing, practically real-time;
simple programming, if the tested unit is
designed for testability;
automated detection of faults such as:
shortcircuits, breakings;
no need for pulse analysis;
adapted for serial production.
 Disadvantages:
costs are increasing too much for circuits
without design for testability;
costs are small for fault detection, but are
increasing a lot if needing fault location;
high volume of work and costs for
describing types of fault corresponding to
each erroneous signature;
difficulties in obtaining the correct
signature.
Electronic Equipment Testing

5. Fault tolerant systems

 5. Generalities

Fault tolerance is an architectural attribute of a

system, making possible for the system to
function properly even when one or more faults
appear in its structure.
Implementation is done through redundancy.
The price to be paid is the high cost
The use is in very critical applications: nuclear,
military, aero-spatial, etc.
 5. Concepts and definitions

Fault = physical problem of one of the systems

elements, taking to the permanent, temporary or
intermittent erroneous function of the system
Error = symptom of a fault
Strategies:
- Fault diagnosis and faulty elements replacement
- Fault masking
- Mixed strategies
 5. Concepts and definitions
Testing methods used:
- Initial testing: before normal operation
- On-line testing: during normal operation
- Off-line testing: for error detection and diagnosis
- Redundant modules testing: in order to see if the
redundant modules are able to replace the modules
that have been detected as faulty
Redundancy is used in order to reconfigure the
system: totally or partially.
 5. Redundant structures
Triple redundancy:

Protection to: shortcircuit, interruption, shortcircuit

and interruption
 5. Redundant structures
Large system redundancy:

Unit B1 Unit B2

Memory Memory 1 Memory 2

Verificare

Unit A1 Unit A1 Unit A2

Processor Processor 1 Processor 2

 5. Majority logic redundant structures
Electronic voter structures:

A1 A B

A2 V A V B V

A3 A B

A B
 5. Majority logic redundant structures
Multiple voter configuration:

Module
V1
M1

Module
V2
M2

Module
V3
M3
 5. Majority logic redundant structures

Detection of the faulty module:

Module
M1

Module V
M2

Module
M3
Electronic Equipment Testing

6. Cable faults detection

 6. Generalities
- Most of the faults are due to the quality of the cable
isolation
- Shortcut to the ground
 6. Fault detection methods

1. Visual checks
2. Instrumental checks
3. Bridge measurements
4. Pulse methods
 6. Bridge measurements
Murray bridge:
 6. Bridge measurements
Murray bridge:

where:
l1 is the distance to the fault place,
S1 is the cable section,
is the cable resistivity.
 6. Bridge measurements
Murray bridge (influence of the connection
cable):
 6. Bridge measurements
Murray bridge (with calibrated wire):
 6. Bridge measurements
Murray bridge (with calibrated wire):

If ON =1000 divizions, and OM =a divizions, then:

 6. Bridge measurements
Murray bridge (with auxiliary wire):
 6. Bridge measurements
Murray bridge (with auxiliary wire):
- Determination of the auxiliary resistance
 6. Bridge measurements
Varley bridge:
 6. Bridge measurements
Graf bridge:
 6. Bridge measurements
Graf bridge:
 6. Pulse methods
Reflection factor:
where:
ZS = load impedance
ZC = characteristic impedance
Homogeneous line: ZS = ZC, r = 0
For non-homogeneous line: ZC ZS, r 0, there is reflection!

Correct line: Uin

 6. Pulse methods
Shortcircuited line:
ZS < ZC, ZS 0 then r -1:
Uin

Ur

Interrupted line:
ZS > ZC, ZS then r 1:
Uin
Ur