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EXISTING SYSTEM:
In Existing System Performs the 8-bit Galois field inversion of the S-box using subfields
of 4 bits and of 2 bits. This work describes a refinement of this approach that minimizes the
circuitry, and hence the chip area, required for the S-box but compare to our proposed system
this values is very high. For applications using larger chips.
Low speed
Fig. ANF-CFA AES S-box with seven stages fine-grained pipelining for Case III
The optimality that we seek for is one with the shortest possible critical path while
preserving the minimum area of occupancy.
SOFTWARE REQUIREMENTS:
ModelSim 6.4c
Xilinx 13.2
HARDWARE REQUIREMENTS:
Image Encryption
Network security
Satellite communication
FUTURE ENHANCEMENT:
Apart from AES S-box, the methodologies proposed in this work are also applicable for
development of any similar cryptographic circuits that involved finite field arithmetic.
Specifically the ANF representation along with a strategic fine-grained registers insertion is an
effective method to overcome the drawback of complicated CFA architecture. Our future works
will focus on constructing composite field with field polynomials in multi-level representation as
well as the exploitation of direct computation of GF (28) in CFA.