EE216 L1 Intro - Winter2017

Welcome to EE216!
Web Site
https://canvas.stanford.edu/courses/55784
Time:
Tuesday, Thursday 1:30 2:50
Location:
Hewlett 102
Credit:
3 units, letter grade
Instructors:
Eric Pop (epop@stanford.edu)

Roger Howe (rthowe@stanford.edu)
Course Assistant:
Ching-Ying Lu (lu18@stanford.edu)
Office Hours:
Roger: Wednesdays 11:00 12:30, Allen 114

Eric: Tuesdays 3:00 4:00, Allen 335X
Ching-Ying: Wednesday afternoons, Packard (TBD)
Stanford EE 216 Winter 2017
Profs. E. Pop and R. T. Howe
Textbooks
Required: R. S. Muller, T. I. Kamins, and M. Chan, Device Electronics for Integrated

Circuits, 3rd ed., Wiley, 2003.
Recommended: D. A. Neamen, Semiconductor Physics and Devices, 4th ed., McGraw
Hill, 2012.
More references:
1 S. M. Sze and K.K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, 2007.
2 Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, 2nd ed., Cambridge, 2009.
3 C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Prentice Hall, 2009.
https://people.eecs.berkeley.edu/~hu/Book-Chapters-and-Lecture-Slides-download.html
4 R. F. Pierret and G. W. Neudeck, Modular Series on Solid State Devices, Volumes I IV.
5 B. G. Streetman, Solid State Electronics Devices, Prentice Hall, 1995.
6 B. van Zegbroek, Principles of Semiconductor Devices
http://ecee.colorado.edu/~bart/book/contents.htm
Grading
30% Homework*
30% Midterm
40% Final
* Homework is due at Thursdays lecture or at the latest, at 5:00 pm Thursday outside
Allen 329X. No late homeworks are accepted, but your lowest score will be dropped.
Tentative Schedule
Jan 10:
Introduction
Jan 12, 17:
Semiconductors in equilibrium
Jan 19, 24, 26:
Semiconductors in non-equilibrium
Jan 31, Feb. 2:
p-n junctions and circuit models
Feb 7:
p-n junctions as opto-electronic devices
Feb 9, Feb. 14
1st half review; mid-term examination Hewlett 102
Feb 16, 21:
Metal-semiconductor contacts
Feb 23, 28, Mar. 2: MOS capacitor

March 7, 9:
MOSFET
March 14, 16:
JFET, BJT, HBT (time permitting)
March 20:
Final Examination (3/20, 12:15 3:15, room TBA)
Specific Course Goals

1. To gain a solid foundation* in semiconductor devices and
an exposure to important applications
*without
assuming a background in quantum mechanics or

solid-state physics
2. To prepare for more advanced device courses, such

EE316 and EE327, as well as to provide background for
research in semiconductor devices
3. To face with confidence device questions in the
Electrical Engineering Ph.D. Qualifying Examination.
Early Electronics History

1839-40's first commercial telegraphs. Digital transmission.
1850's and 60's: first submarine cables.
1870's telephone. Analog transmission. First solid state 'device
the carbon granule microphone
1900 Wireless ('radio') transmission. Digital. Second wave of solid-state
device(s): coherer, point contact metal semiconductor junction
('crystal rectifier').
1906 The audion vacuum tube by Lee de Forest
1st (Bipolar Junction) Transistor
1st Integrated Circuit
Christmas Eve 1947
By Kilby,
Nobel Laureate in Physics 2000
and
Robert Noyce
By Bardeen, Brattain, and Shockley,

Nobel Laureates in Physics 1956
1947
1958
(http://www.bellsystemmemorial.com/belllabs_transistor.html)
(Courtesy of TI and Huff, SEMATECH)
Semiconductor Industry: $333B (est. 2017)

Chemical Engineering
Nuclear Physics
Chemistry
Material Science
Electrical Engineering
Applied Physics
Mechanical Engineering
Truly multi disciplinary field

Semiconductor Devices in Action
Diode: Applications ?
MOS Capacitor: Applications ?
10
HBT: Applications ?
11
Devices: components that do interesting things

Diode: rectifies:
I
V
I
Parameters: Rforward
Rreverse
V
Vturnon
0
speed
also can detect/emit light and can convert optical to electrical energy
Triode: amplifies (signal power out > signal power in)

Parameters:
Transconductance g m
Threshold Voltage VT
Subthreshold current
Gate current Ig
Speed
Noise
and many more
Ig
Vg
= VI
g V
I
VT
Vg
Vg
V
12
Very basic principle of operation of (virtually) all amplifying devices:

(Gate-controlled diode)
Carrier Energy
qV
Gate at Vg
N (V) dV= N0exp(-qV/kT)dV
qVb
0
Source
Collector
Distance
- qV
b
# carriers escaping over barrier per unit time x q = I = I0 exp(
)
kT
(approximate)
13
At best, a change in gate voltage DVg will bring about a change in barrier height
DVb = DVg
In which case
DI
DVg
-qVb
q
q
= g m = - kT I0 exp( kT ) = - kT I
So the best transconductance we can achieve is q/kT x I

In a bipolar junction transistor Vg=Vb and this limit is achieved!
Even vacuum tubes came close.
For many years MOSFETs lagged because the oxide layer
separating the gate electrode from the semiconducting channel
but this layer is now so thin (e.g. 1-2 nm instead of 100 nm 30
years ago) that even MOSFETs are approaching this limit.
14
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11
keys to the electronics REVOLUTION
by P
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Saddl
dd
Uppe
Si is at best, a mediocre semiconductor

SiO2 is the foundation of Si technology!
15
Moores Law
The Chips are Down for Moores Law, Nature 530, 144147 (11 February 2016)
16
One Impact of Moores Law
17
Another Impact: Computation Cost
18
The Cost of Moores Law:

Rockss Law
cost of a semiconductor chip fabrication plant doubles every four years
10,000
2x every 4 years
1000
cost of a modern
wafer fab
100
($ million)
2x every 3 years
1.47x every 2 years
10
1960
1970
1980
1990
2000
We need to understand how the devices function to ensure proper performance, reliability
and economic implications. For many generations, scaling was relatively straightforward.
Today, it also involves new materials and increased complexity, greatly increasing cost.
Today, a new fab can put a large company at risk

19
EUV Lithography
Price: $75M and you need 15 of them for a large fab.

20
Technology Transitions
The first transistor was a bipolar transistor, as were the first ICs
Initial MOS only had incremental advantages over bipolar until CMOS
III-V technology is largely optoelectronics--a complement to CMOS
Is there anything beyond CMOS?
21
Why Silicon?
Si is easily purified and grown as a defect free single crystal

Si has reasonably good electronic properties which produce a
variety of devices with excellent performance
Si and SiO2 are tolerant to a variety of harsh environments used
in fabrication and is highly manufacturable
Si has excellent mechanical properties which facilitate handling
and manufacturing
Si is readily available and very plentiful in nature
SiO2 is a Remarkable Material
SiO2 passivates the Si surface

SiO2 is an excellent insulator
SiO2 is an excellent barrier against impurity diffusion
SiO2 has very high etch selectivity to Si
Limitations of Si
o
o
Indirect bandgap -- poor optoelectronic properties

Moderate carrier mobility
22
Material Complexity Has Been Increasing
+4 Elements
+45 Elements
11 Elements
Source: Terrence J. McManus, Intel

23
Electronics vs. Photonics

Si/SiO2/PolySi
Si/SiO2/PolySi
Electronics
Si/SiO2/PolySi
Si/SiO2/PolySi
Si/SiO2/PolySi
Si/SiO2/PolySi
Si/SiO2/PolySi
Si electronics is a processing based technology
Photonics
GaAs, GaP, GaSb, InP, InAs, InSb, AlAs, GaN, AlN

GaAsxP1-x, AlxGa1-xAs, InxGa1-xP, InxGa1-xAs, AlxGa1xSb, AlxGa1-xN, GaxIn1-xN--Ternary Alloys
InxGa1-xAsyP1-y, AlxInyGa1-x-yAs, InxGa1-xAsySb1-y,
InxGa1-xNyAs1-y--Quaternary Alloys
InxGa1-xNyAs1-y-zSbz--Quinary Alloy
Photonics is a materials based technology
24
Photonics require a different material for each

wavelength (band gap)
25
Taking the cover off a microprocessor.

Packaged die
Cross-section
Single transistor
Full wafer (100s of dies)
modern wafers: 300-450 mm
diameter (12-18 inches)
26
Ultimate CMOS Scaling (Intel)
27
What is a technology node anyway?

Intel 22 nm node transistors have L
35 nm, tfin 8 nm, pitch 90 nm
Rule of thumb, pitch 3-4*LG at the
moment, but
Pitch
Half-pitch
Contact
LC
Source
Channel
Channel
Thickness
Drain
source: IEEE Spectrum
Qualcomm 28 nm Snapdragon (TSMC)
Gate LG
28
we must scale contacts too, not just the gates!

1000
Pitch
Half-pitch
old pitch scaling

relying on LG
Contact
today
100
Gate Pitch (nm)
LC
Source
Gate LG
Channel
Channel
Thickness
Drain
Gate Pitch is key metric of

device scaling
Must scale both LG and LC
LG + LC scaling?
20 nm
May be possible ONLY with

atomically thin channels
10
90 65 45 32 22 16 10 7
5
Tech. Node (nm) LG
source: IEEE Spectrum, Intel

29
20th century transistors carved out of bulk

3D materials (like Si) using patterning,
etching
As 3D materials shrink, they have dangling
bonds and surface states these, plus
quantum mechanics limit minimum
dimensions to ~10 nm
Will 21st century transistors be made of 1D
(carbon nanotube) or 2D (graphene, MoS2)
materials? These have ~1 nm thickness.
1 nm
2D materials like
MoS2, WTe2, ZrSe2
carbon
nanotubes (1D)
<1 nm
30
Skyscraper Nanosystems built Layer-by-Layer
Stanford Report, Dec. 10, 2015

Skyscraper digital systems architecture enabled by
aligned CNT transfer and low-temperature RRAM processes.
Max Shulaker, S. Mitra and P. Wong groups, IEEE IEDM 2014, 2015
31
Technology Transitions
Transistors areBeyond
getting very
small ...
CMOS
100 m
conventional devices work
well in classical region
10 m
1 m
0.1 m
transition region
0.01 m
quantum devices
0.001 m
atomic dimensions
1960
1980
2000
2020
2040
Jim Plummer, 1989.
Devices are getting very small. Will they reach quantum or

even atomic dimensions? What principles will they operate on?
Still charge or is spin or something else possible?
32
Communications Challenge
Broadway, New York City, 1887
Intel Microprocessor, 2005
33
Integration of Photonics and Electronics

Two principal drivers that seemed unimaginable a decade ago
Requirements for smart optical networks, greater bandwidths and
lower cost are pushing the integration of electronics and photonics
Interconnect bottleneck for CMOS operating above 10GHz is
pushing for integration of photonics into electronics for timing and
possibly signal channels
This is creating tremendous new challenges for both technologies
because of materials incompatibility--photonics requires a different
material for every different wavelength (application), CMOS is Si.
The near term solution has been hybrid integration (fabrication of
separate devices and bonding them together). The ultimate solution
will either be Si Photonics or finding barrier materials and
temperatures where we achieve epitaxy for monolithic integration.
34
What's enabling these?
35
Micro (and Nano) Electromechanical Systems

MEMS: ~ $14B market in 2017, growth through 2021 at ~ 10%/year
Bulk acoustic wave MEMS

gyroscope; close up of
drive electrode
Qualtre
Direct-write lithography
engine based on 8192 grating
light valve on CMOS
Silicon Light Machines
Silicon resonator simulation and

MEMS chip bonded directly onto
CMOS timing chip
SiTime
36
Nano-CMOS Deficiences
A nano electromechanical switch has several
advantages compared with nanoscale CMOS
transistors:
very high on current
zero leakage
infinite subthreshold slope
high temperature operation
radiation-hard operation
compatible with other substrates glass, plastics
and just a few problems:

reliability (stiction, contact degradation, wear, )
slow speed
low density
37
The NEMFET
Nano-electromechanical gate
(anchors not shown)
Accumulation-mode design:
> 105 X less gate leakage
p+
Source
n+
Gate is doubly clamped

nano-mechanical beam
n+
Work-function difference:
gate down with Vg = 0V.
Buried Oxide
Si Substrate
H. Kam, D. T. Lee, T.-J. King, and R. T. Howe
IEEE Int. Electron Devices Meeting, Dec. 2005
H. Kam, IEDM 2009 demonstrated!
38
What about Photovoltaics?
crystalline silicon
solar cells
Issues: matching of silicon photon absorption to our local light

solar source; cost ($, carbon, energy, environment) of
production; lifecycle costs
Massive investments: 1970s, 2000s. Likely to play a niche role, in
a huge and ever-growing part of the world economy.
39
Semiconductor Devices and Technology

Prospects after the End of the Roadmap*
Asymptotically diminishing increases in performance for
conventional electronic devices (Moore)
Many More than Moore functions: photonics, new
memories, MEMS, biosensing
Advantage in the market for most applications wont be driven
by computing or even communication performance.
Challenge: financial return on (huge) investment in IC fabs
will probably limit rate of mainstream electronics advance;
new heterogeneous integration technologies will progress
rapidly with much higher return on (smaller) investments
*The
International Technology Roadmap for Semiconductors (ITRS)

http://www.itrs2.net/
40

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Welcome to EE216!

Tuesday, Thursday 1:30 2:50

3 units, letter grade

Eric Pop (epop@stanford.edu)

Roger: Wednesdays 11:00 12:30, Allen 114

Stanford EE 216 Winter 2017

Profs. E. Pop and R. T. Howe

Required: R. S. Muller, T. I. Kamins, and M. Chan, Device Electronics for Integrated

Profs. E. Pop and R. T. Howe

Jan 12, 17:

Jan 19, 24, 26:

Jan 31, Feb. 2:

p-n junctions and circuit models

p-n junctions as opto-electronic devices

1st half review; mid-term examination Hewlett 102

Feb 16, 21:

Feb 23, 28, Mar. 2: MOS capacitor

March 14, 16:

JFET, BJT, HBT (time permitting)

Final Examination (3/20, 12:15 3:15, room TBA)

Stanford EE 216 Winter 2017

Profs. E. Pop and R. T. Howe

Specific Course Goals

assuming a background in quantum mechanics or

2. To prepare for more advanced device courses, such

Stanford EE 216 Winter 2017

Profs. E. Pop and R. T. Howe

Early Electronics History

Stanford EE 216 Winter 2017

Profs. E. Pop and R. T. Howe

1st (Bipolar Junction) Transistor

1st Integrated Circuit

Christmas Eve 1947

By Bardeen, Brattain, and Shockley,

Profs. E. Pop and R. T. Howe

Semiconductor Industry: $333B (est. 2017)

Truly multi disciplinary field

Profs. E. Pop and R. T. Howe

Semiconductor Devices in Action

Stanford EE 216 Winter 2017

Profs. E. Pop and R. T. Howe

Stanford EE 216 Winter 2017

Profs. E. Pop and R. T. Howe

MOS Capacitor: Applications ?

Stanford EE 216 Winter 2017

Profs. E. Pop and R. T. Howe

Stanford EE 216 Winter 2017

Profs. E. Pop and R. T. Howe

Devices: components that do interesting things

Triode: amplifies (signal power out > signal power in)

Profs. E. Pop and R. T. Howe

Very basic principle of operation of (virtually) all amplifying devices:

N (V) dV= N0exp(-qV/kT)dV

Profs. E. Pop and R. T. Howe

So the best transconductance we can achieve is q/kT x I

Profs. E. Pop and R. T. Howe

Si is at best, a mediocre semiconductor

Profs. E. Pop and R. T. Howe

Profs. E. Pop and R. T. Howe

One Impact of Moores Law

Profs. E. Pop and R. T. Howe

Another Impact: Computation Cost

Stanford EE 216 Winter 2017