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M12L2561616A (2A)
SDRAM
4M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
y
y
y
y
y
y
y
y
y
y
ORDERING INFORMATION
Product ID
Max Freq.
Package Comments
M12L2561616A-5TG2A
200MHz
TSOP II
Pb-free
M12L2561616A-5BG2A
200MHz
BGA
Pb-free
M12L2561616A-6TG2A
166MHz
TSOP II
Pb-free
M12L2561616A-6BG2A
166MHz
BGA
Pb-free
M12L2561616A-7TG2A
143MHz
TSOP II
Pb-free
M12L2561616A-7BG2A
143MHz
BGA
Pb-free
GENERAL DESCRIPTION
The M12L2561616A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V SS
DQ15
V S SQ
DQ14
DQ13
VDDQ
DQ12
DQ11
V S SQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ15
DQ14
VSSQ
VDDQ
DQ0
VDD
DQ13
VDDQ
VSSQ
DQ2
DQ1
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
DQ8
NC
VSS
VDD
LDQM
DQ7
UDQM
CLK
CKE
CAS
RAS
WE
A12
A11
A9
BA0
BA1
CS
A8
A7
A6
A0
A1
A10
VSS
A5
A4
A3
A2
VDD
ESMT
M12L2561616A (2A)
BLOCK DIAGRAM
CKE
Clock
Generator
Bank D
Bank C
Bank B
Address
Mode
Register
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
CLK
Bank A
CAS
WE
Address
L(U)DQM
Column Decoder
Buffer
&
Counter
RAS
Column
Latch Circuit
CS
Control Logic
Command Decoder
Sense Amplifier
DQ
PIN DESCRIPTION
PIN
NAME
CLK
System Clock
CS
Chip Select
INPUT FUNCTION
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
A0 ~ A12
Address
BA1, BA0
RAS
Latches row addresses on the positive going edge of the CLK with
CAS
WE
Write Enable
L(U)DQM
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ0 ~ DQ15
VDD / VSS
Power and ground for the input buffers and the core logic.
VDDQ / VSSQ
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
NC
No Connection
ESMT
M12L2561616A (2A)
Symbol
Value
Unit
VIN, VOUT
-1.0 ~ 4.6
VDD, VDDQ
-1.0 ~ 4.6
TA
0 ~ +70
TSTG
-55 ~ +150
Power dissipation
PD
IOS
50
mA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70 C )
Parameter
Supply voltage
Symbol
Min
Typ
Max
Unit
VDD, VDDQ
3.0
3.3
3.6
Note
VIH
2.0
3.0
VDD+0.3
VIL
-0.3
0.8
VOH
2.4
IOH = -2mA
VOL
0.4
IOL = 2mA
IIL
-5
IOL
-5
Note:
Symbol
Min
Max
Unit
CIN1
1.5
pF
CCLK
pF
CIN2
1.5
4.5
pF
COUT
4.5
pF
Input capacitance
(CKE, CS , RAS , CAS , WE & L(U)DQM)
Data input/output capacitance (DQ0 ~ DQ15)
ESMT
M12L2561616A (2A)
DC CHARACTERISTICS
Symbol
ICC1
Precharge Standby
ICC2P
Current in power-down
mode
ICC2PS
Precharge Standby
Current in non
power-down mode
ICC2N
ICC2NS
Active Standby
ICC3P
Current in power-down
ICC3PS
mode
Version
Test Condition
Unit Note
-5
-6
-7
80
70
60
mA
mA
mA
15
mA
mA
mA
mA
28
mA
20
mA
1,2
ICC3N
ICC3NS
Operating Current
(Burst Mode)
ICC4
Refresh Current
ICC5
tRFC tRFC(min)
ICC6
CKE=0.2V
tCCD = 2 CLKs
90
80
70
120
110
100
mA
1,2
mA
mA
ESMT
M12L2561616A (2A)
Value
Unit
2.4/0.4
1.4
tr/tf = 1/1
ns
1.4
See Fig. 2
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Unit
Note
20
ns
ns
1
1
18
20
ns
42
45
ns
-5
-6
-7
tRRD(min)
tRCD(min)
10
12
14
15
18
tRP(min)
tRAS(min)
15
40
tRAS(max)
us
100
@ Operating
tRC(min)
55
60
63
ns
@ Auto refresh
tRFC(min)
55
60
63
ns
1,5
CLK
CLK
CLK
CLK
ms
2
2
2
3
6
ea
Version
Symbol
tCDL(min)
tRDL(min)
tBDL(min)
tCCD(min)
tREF(max)
1
2
1
1
64
CAS latency = 3
CAS latency = 2
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given tRFC after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with tRFCmin) can be posted to any given SDRAM, and the
maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x7.8 s.)
ESMT
M12L2561616A (2A)
-5
Symbol
Min
CAS latency = 3
CAS latency = 2
CLK to valid
output delay
CAS latency = 3
Output data
hold time
CAS latency = 3
CAS latency = 2
CAS latency = 2
CAS latency = 3
CAS latency = 2
tCC
5
10
tSAC
tOH
tCH
tCL
tSS
tSH
tSLZ
tSHZ
-6
Max
1000
Min
6
10
-7
Max
1000
Min
7
10
1000
5.4
5.4
5.4
5.4
5.4
2.5
2.5
2
2
2
1.5
0.8
1
2.5
2.5
2.5
1.5
0.8
1
2.5
2.5
2.5
1.5
0.8
1
Unit
Note
ns
ns
1,2
ns
ns
ns
ns
ns
ns
3
3
3
3
2
Max
4.5
5.4
5.4
5.4
5.4
5.4
ns
ESMT
M12L2561616A (2A)
CKEn-1 CKEn
Refresh
Write &
Column Address
A12~A11,
BA0,
Note
A10/AP
BA1
A9~A0
OP CODE
H
X
L
H
X
H
H
X
H
X
X
X
L
H
L
Entry
Exit
Entry
Clock Suspend or
Active Power Down
DQM
Burst Stop
Precharge
X
H
L
WE
CS RAS CAS
DQM
No Operating Command
X
X
1,2
3
3
3
3
X
Row Address
Column
L
Address
H
(A0~A8)
Column
L
Address
H
(A0~A8)
X
4
4,5
4
4,5
6
X
X
X
X
X
X
V
ESMT
M12L2561616A (2A)
BA0~BA1
A12~A10/AP
A9
Function
RFU
RFU
W.B.L.
Test Mode
A8
A7
A6
TM
CAS Latency
A5
A4
A3
CAS Latency
A2
BT
A1
A0
Burst Length
Burst Type
Burst Length
A8
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1
A0
BT = 0
BT = 1
Reserved
Sequential
Reserved
Reserved
Interleave
Reserved
Reserved
Reserved
Reserved Reserved
Length
Reserved
Reserved Reserved
Burst
Reserved
Reserved Reserved
Single Bit
Reserved
Note:
1. RFU (Reserved for future use) should stay 0 during MRS cycle.
2. If A9 is high during MRS cycle, Burst Read single write function will be enabled.
ESMT
M12L2561616A (2A)
Sequential
Interleave
A1
A0
Sequential
Interleave
A2
A1
A0
ESMT
M12L2561616A (2A)
DEVICE OPERATIONS
CLOCK (CLK)
POWER-UP
CLOCK ENABLE(CKE)
The clock enable (CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time same
as other inputs), the internal clock suspended from the next
clock cycle and the state of output and burst address is frozen
as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When all banks
are in the idle state and CKE goes low synchronously with
clock, the SDRAM enters the power down mode from the next
clock cycle. The SDRAM remains in the power down mode
ignoring the other inputs as long as CKE remains low. The
power down exit is synchronous as the internal clock is
suspended. When CKE goes high at least 1CLK + tSS before
the high going edge of the clock, then the SDRAM becomes
active from the same clock edge accepting all the input
commands.
CS
high.
CS
BANK ACTIVATE
The bank activate command is used to select a random
ESMT
M12L2561616A (2A)
BURST READ
The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active bank.
The burst read command is issued by asserting low on CS
and RAS with WE being high on the positive edge of the
clock. The bank must be active for at least tRCD(min) before the
burst read command is issued. The first output appears in CAS
latency number of clock cycles after the issue of burst read
command. The burst length, burst sequence and latency from
the burst read command is determined by the mode register
which is already programmed. The burst read can be initiated
on any column address of the active row. The address wraps
around if the initial address does not start from a boundary
such that number of outputs from each I/O are equal to the
burst length programmed in the mode register. The output
goes into high-impedance at the end of burst, unless a new
burst read was initiated to keep the data output gapless. The
burst read can be terminated by issuing another burst read or
burst write in the same bank or the other active bank or a
precharge command to the same bank. The burst stop
command is valid at every page burst length.
BURST WRITE
The burst write command is similar to burst read command
and is used to write data into the SDRAM on consecutive clock
cycles in adjacent addresses depending on burst length and
burst sequence. By asserting low on CS , CAS and WE
with valid column address, a write burst is initiated. The data
inputs are provided for the initial address in the same clock
cycle as the burst write command. The input buffer is
deselected at the end of the burst length, even though the
internal writing can be completed yet. The writing can be
complete by issuing a burst read and DQM for blocking data
inputs or burst write in the same or another active bank. The
burst stop command is valid at every burst length. The write
burst can also be terminated by using DQM for blocking data
and precharge the bank tRDL after the last data input to be
written into the active row. See DQM OPERATION also.
DQM OPERATION
The DQM is used mask input and output operations. It
works similar to OE during operation and inhibits writing
during write operation. The read latency is two cycles from
DQM and zero cycle for write, which means DQM masking
occurs two cycles later in read cycle and occurs in the
same cycle during write cycle. DQM operation is
synchronous with the clock. The DQM signal is important
during burst interrupts of write with read or precharge in
the SDRAM. Due to asynchronous nature of the internal
write, the DQM operation is critical to avoid unwanted or
incomplete writes when the complete burst write is
required. Please refer to DQM timing diagram also.
PRECHARGE
The precharge is performed on an active bank by
asserting low on clock cycles required between bank
activate and clock cycles required between bank activate
and CS , RAS , WE and A10/AP with valid BA0~BA1
of the bank to be procharged. The precharge command
can be asserted anytime after tRAS(min) is satisfy from the
bank active command in the desired bank. tRP is defined
as the minimum number of clock cycles required to
complete row precharge is calculated by dividing tRP with
clock cycle time and rounding up to the next higher
integer. Care should be taken to make sure that burst
write is completed or DQM is used to inhibit writing before
precharge command is asserted. The maximum time any
bank can be active is specified by tRAS(max). Therefore,
each bank has to be precharge with tRAS(max) from the
bank activate command. At the end of precharge, the
bank enters the idle state and is ready to be activated
again. Entry to power-down, Auto refresh, Self refresh and
Mode register set etc. is possible only when all banks are
in idle state.
AUTO PRECHARGE
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the
timing to satisfy tRAS(min) and tRP for the programmed
burst length and CAS latency. The auto precharge
command is issued at the same time as burst write by
asserting high on A10/AP, the bank is precharge command
is asserted. Once auto precharge command is given, no
new commands are possible to that particular bank until
the bank achieves idle state.
ESMT
M12L2561616A (2A)
SELF REFRESH
ESMT
COMMANDS
M12L2561616A (2A)
CLK
CKE
CS
RAS
The M12L2561616A has a mode register that defines how the device operates.
In this command, A0~A12, BA0 and BA1 are the data input pins. After power on, the
mode register set command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state.
During 2CLK following this command, the M12L2561616A cannot accept any
other commands.
CAS
WE
BA0, BA1
A10
Add
Fig. 1 Mode register set
command
CLK
Activate command
( CS , RAS = Low, CAS , WE = High)
The M12L2561616A has four banks, each with 8,192 rows.
This command activates the bank selected by BA1 and BA0 (BS) and a row
address selected by A0 through A12.
This command corresponds to a conventional DRAMs RAS falling.
CKE
CS
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
Row
Add
Row
Precharge command
( CS , RAS , WE = Low, CAS = High )
This command begins precharge operation of the bank selected by BA1 and BA0
(BS). When A10 is High, all banks are precharged, regardless of BA1 and BA0.
When A10 is Low, only the bank selected by BA1 and BA0 is precharged.
After this command, the M12L2561616A cant accept the activate command to
the precharging bank during tRP (precharge to activate command period).
This command corresponds to a conventional DRAMs RAS rising.
CLK
CKE
CS
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
(Precharge select)
Add
Fig. 3 Precharge command
ESMT
Write command
( CS , CAS , WE = Low, RAS = High)
If the mode register is in the burst write mode, this command sets the burst start
address given by the column address to begin the burst write operation. The first
write data in burst can be input with this command with subsequent data on following
clocks.
M12L2561616A (2A)
CLK
CKE
CS
RAS
CAS
WE
BA0,BA1
(Bank select)
A10
Add
Col.
CLK
Read command
( CS , CAS = Low, RAS , WE = High)
Read data is available after CAS latency requirements have been met.
This command sets the burst start address given by the column address.
CKE
CS
RAS
CAS
WE
BA0,BA1
(Bank select)
A10
Add
Col.
CLK
CKE
CS
RAS
CAS
WE
BA0,BA1
(Bank select)
A10
Add
Fig. 6 Auto refresh command
ESMT
Self refresh entry command
( CS , RAS , CAS , CKE = Low , WE = High)
After the command execution, self refresh operation continues while CKE
remains low. When CKE goes to high, the M12L2561616A exits the self refresh
mode.
During self refresh mode, refresh interval and refresh operation are performed
internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
M12L2561616A (2A)
CLK
CKE
CS
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
Add
Fig. 7 Self refresh entry
command
CLK
CKE
CS
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
Add
Fig. 8 Burst stop command
No operation
CLK
CKE
CS
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
Add
Fig. 9 No operation
ESMT
M12L2561616A (2A)
CLK
CMD
WR
RD
CKE
Masked by CKE
Internal
CLK
DQ(CL2)
D0
D1
D2
D3
DQ(CL3)
D0
D1
D2
D3
Q0
Q1
Q2
Q3
Q1
Q2
Q3
Not W ritten
Q0
2. DQM Operation
2)Read Mask (BL=4)
CLK
CMD
RD
WR
DQM
Ma s k e d b y D Q M
Ma s k e d b y D Q M
DQ(CL2)
D0
D1
D3
DQ(CL3)
D0
D1
D3
Q0
Hi-Z
Hi-Z
DQ M t o D at a- i n M as k = 0
Q2
Q3
Q1
Q2
Q3
DQ M to D at a- ou t M ask = 2
*Note2
3)DQM with clcok su sp end ed (F ull Page Read )
CLK
CMD
RD
CKE
Internal
CLK
DQM
DQ( CL2 )
DQ(CL3)
Q0
Hi- Z
Hi-Z
Q2
Q1
Hi- Z
Hi-Z
Q4
Q3
Hi- Z
Hi-Z
Q6
Q7
Q8
Q5
Q6
Q7
ESMT
M12L2561616A (2A)
*N ote1
1)R ea d i nt er ru pt ed by R ead (B L =4)
CL K
C MD
RD
RD
ADD
DQ ( C L 2 )
QA0
D Q ( CL 3 )
QB0
QB1
QB2
QB3
QA0
QB0
QB1
QB2
QB3
t C CD
*N ot e 2
2) Wr i t e i n t er ru pt e d b y W ri t e (B L= 2)
3 )W ri t e in t er rup t ed b y R e ad (B L=2 )
CLK
C MD
WR
WR
t CC D
A DD
DQ
WR
tC CD
* No t e 2
DA0
DB 0
A
D B1
tC D L
* No t e 3
DQ ( C L 2 )
DA0
D Q ( CL 3 )
DA 0
RD
*N ote 2
B
DB0
DB1
DB 0
DB1
tC D L
* No t e 3
*Note:
1. By interrupt is meant to stop burst read/write by external before the end of burst.
By CAS interrupt , to stop burst read/write by CAS access ; read and write.
2. tCCD: CAS to CAS delay. (=1CLK)
3. tCDL: Last data in to new column address delay. (=1CLK)
ESMT
M12L2561616A (2A)
( a) CL =2 , B L= 4
CLK
i)CMD
RD
WR
DQM
DQ
ii)CMD
D0
RD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
DQM
Hi-Z
DQ
iii)CMD
D0
WR
RD
DQM
Hi-Z
DQ
iv)CMD
D0
WR
RD
DQM
DQ
Q0
HHi -i -ZZ
D0
D3
*Note1
ESMT
M12L2561616A (2A)
(b) CL =3 ,B L= 4
CLK
i)CMD
WR
RD
DQM
DQ
D0
ii)CMD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
RD
DQM
DQ
D0
iii)CMD
RD
WR
DQM
D0
DQ
iv)CMD
WR
RD
DQM
Hi-Z
DQ
v)CM D
D0
RD
WR
DQM
DQ
Q0
Hi-Z
D0
D3
*Note1
*Note: 1. To prevent bus contention, there should be at least one gap between data in and data out.
WR
PRE
*Note2
DQM
DQ
D0
D1
D3
tRDL(min)
*Note:
*Note3
Masked by DQM
1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of four banks operation.
ESMT
M12L2561616A (2A)
6. Precharge
2) Norm al Read (B L= 4)
CLK
CLK
CMD
WR
DQ
D0
PRE
CMD
RD
PRE
CL=2
Q2
Q3
*Note2
D1
D2
DQ( CL2)
D3
tRDL
Q0
Q1
PRE CL= 3
CMD
*Note1
*Note2
DQ ( CL 3 )
Q0
Q1
Q2
Q3
7. Auto Precharge
CLK
CMD
DQ
CLK
CMD
WR
D0
D1
D2
D3
DQ( CL 2)
tRDL
RD
D0
D1
D2
D3
D0
D1
D2
(min )
DQ(CL3)
D3
*Note3
*Note:
ESMT
M12L2561616A (2A)
CLK
CLK
CMD
CMD
STOP
WR
DQM
* Note3
WR
tRDL
PRE
*Note4
DQM
DQ
D0
D1
D2
D3
D4
tBDL
D5
DQ
D0
D1
Mask Mask
*Note1
CLK
C LK
CMD
RD
CMD
STOP
RD
PRE
*Note5
*Note2
DQ(CL2)
Q0
DQ (CL2)
Q1
Q0
Q1
Q2
Q3
Q0
Q1
Q2
*Note2
DQ(CL3)
Q0
Q1
DQ(CL3)
Q3
9. MRS
1) Mo d e Re g is te r S e t
CLK
*Note4
CMD
PRE
tRP
*Note:
ACT
MRS
2CLK
ESMT
M12L2561616A (2A)
CLK
CLK
CKE
Inter nal
CLK
tSS
CKE
tSS
Internal
CLK
*Note1
CMD
*Note2
CMD
RD
NOP AC T
*Note3
CLK
*Note4
CMD
*Note5
PRE
AR
CMD
CKE
tRP
2)Self Refresh
tRFC
*Note6
CLK
*Note4
CMD
SR
PRE
CMD
CKE
tRP
*Note:
tRFC
ESMT
M12L2561616A (2A)
Interleave Counting
Basic
MODE
Every cycle Read/Write Command with random column address can realize Random
Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
Basic
MODE
Full Page
Special
MODE
BRSW
Random
MODE
Burst Stop
Interrupt
MODE
RAS Interrupt
(Interrupted by
Precharge)
CAS Interrupt
ESMT
M12L2561616A (2A)
IDLE
Row
Active
Read
Write
Read with
Auto
Precharge
Write with
Auto
Precharge
CS
RAS
CAS
WE
BA
ADDR
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
L
L
X
H
H
H
L
L
X
H
H
L
H
H
L
L
X
H
H
L
L
H
H
L
X
H
H
L
L
H
H
L
X
H
H
L
L
H
H
L
X
H
H
L
H
L
X
H
H
L
H
L
X
H
L
X
H
L
H
L
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
X
X
X
X
H
L
X
X
X
X
X
X
BA
BA
BA
X
OP code
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
X
X
X
X
BA
BA
X
X
X
X
CA, A10/AP
RA
A10/AP
X
OP code
X
X
X
CA, A10/AP
CA, A10/AP
RA
A10/AP
X
X
X
X
CA, A10/AP
CA, A10/AP
RA
A10/AP
X
X
X
X
CA, A10/AP
CA, A10/AP
RA
A10/AP
X
X
X
X
CA, A10/AP
RA, RA10
X
X
X
X
CA, A10/AP
RA, RA10
X
ACTION
NOP
NOP
ILLEGAL
ILLEGAL
Row (&Bank) Active ; Latch RA
NOP
Auto Refresh or Self Refresh
Mode Register Access
NOP
NOP
ILLEGAL
Begin Read ; latch CA ; determine AP
Begin Write ; latch CA ; determine AP
ILLEGAL
Precharge
ILLEGAL
NOP (Continue Burst to End Row Active)
NOP (Continue Burst to End Row Active)
Term burst Row active
Term burst, New Read, Determine AP
Term burst, New Write, Determine AP
ILLEGAL
Term burst, Precharge timing for Reads
ILLEGAL
NOP (Continue Burst to End Row Active)
NOP (Continue Burst to End Row Active)
Term burst Row active
Term burst, New Read, Determine AP
Term burst, New Write, Determine AP
ILLEGAL
Term burst, Precharge timing for Writes
ILLEGAL
NOP (Continue Burst to End Row Active)
NOP (Continue Burst to End Row Active)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Continue Burst to End Row Active)
NOP (Continue Burst to End Row Active)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Note
2
2
4
5
5
2
2
3
2
3
3
2
3
ESMT
Current
State
Read with
Auto
Precharge
Row
Activating
Refreshing
Mode
Register
Accessing
Abbreviations:
*Note:
M12L2561616A (2A)
CS
RAS
CAS
WE
BA
ADDR
ACTION
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
X
H
H
H
L
L
L
X
H
H
H
L
L
L
X
H
H
L
L
X
H
H
H
L
X
H
H
L
H
H
L
X
H
H
L
H
H
L
X
H
L
H
L
X
H
H
L
X
X
H
L
X
H
L
X
X
H
L
X
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
BA
BA
BA
X
X
X
X
BA
BA
BA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CA
RA
A10/AP
X
X
X
X
CA
RA
A10/AP
X
X
X
X
X
X
X
X
X
X
X
RA = Row Address
NOP = No Operation Command
BA = Bank Address
CA = Column Address
Note
2
2
2
4
2
2
2
2
AP = Auto Precharge
1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.
2. Illegal to bank in specified state; Function may be legal in the bank indicated by BA, depending on the state of the bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
ESMT
M12L2561616A (2A)
Self
Refresh
All
Banks
Precharge
Power
Down
All
Banks
Idle
Any State
other than
Listed
above
CKE
( n-1 )
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
H
H
L
L
CKE
n
X
H
H
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
L
H
L
H
L
CS RAS CAS
X
H
L
L
L
L
X
X
H
L
L
L
L
X
X
H
L
L
L
L
L
L
L
X
X
X
X
X
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
X
H
H
H
L
L
L
L
X
X
X
X
X
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
X
H
H
L
H
H
L
L
X
X
X
X
X
WE
ADDR
X
X
H
L
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RA
X
X
OP Code
X
X
X
X
X
ACTION
INVALID
Exit Self Refresh Idle after tRFC (ABI)
Exit Self Refresh Idle after tRFC (ABI)
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Self Refresh ABI
Exit Self Refresh ABI
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Low Power Mode)
Refer to Table1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
Row (& Bank) Active
NOP
Enter Self Refresh
Mode Register Access
NOP
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
Note
6
6
7
7
8
8
9
9
ESMT
M12L2561616A (2A)
Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 3, Burst Length = 1
tCH
10
11
12
13
14
15
16
17
18
19
CLOCK
tCL
tCC
HIGH
CKE
tRAS
tRC
tS
H
*Note1
CS
tSH
tRCD
tRP
tSS
RAS
tSS
tCCD
tSH
CAS
tSH
ADDR
Ra
tSS
*Note2
BA0,BA1
BS
A10/AP
Ra
tSS
Ca
Cb
*Note2,3
Cc
*Note2,3
*Note2,3
BS
*Note3
*Note4
* Note2
BS
BS
BS
BS
*Note3
*Note3
*Note4
Rb
tSH
tSAC
Qa
DQ
Rb
Db
tSLZ
Qc
tSS
tOH
tSH
WE
tSS
tSS
tSH
DQM
Row Active
R ead
W rite
Row Active
Read
Prec ha rge
:Don't Care
ESMT
Note:
M12L2561616A (2A)
1. All input expect CKE & DQM can be dont care when CS is high at the CLK high going edge.
2. Bank active @ read/write are controlled by BA0~BA1.
BA0
BA1
Bank A
Bank B
Bank C
Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command
A10/AP
BA0
BA1
Operating
BA0
BA1
Precharge
Bank A
Bank B
Bank C
Bank D
All Banks
ESMT
M12L2561616A (2A)
Power Up Sequence
ESMT
M12L2561616A (2A)
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
*Note 1
RC
CS
tRCD
RAS
*Note2
CAS
ADDR
Ra
Ca
Rb
Cb
BA0
BA1
A10/AP
Ra
Rb
CL =2
Qa0
Qa1
Qa2
Db0
Qa3
Db1
Db2
Db3
*Note3
DQ
CL =3
Qa0
Qa 1
Qa2
tRDL
D b0
Qa3
Db1
*No te 3
Db2
Db3
tRDL
WE
DQM
Row Active
( A - Bank )
Read
( A - Bank )
Precharge
( A - Bank )
Row Active
( A - Bank )
Write
( A - Bank )
Precharge
(A - Bank)
:Don't Care
*Note:
ESMT
M12L2561616A (2A)
Note: 1. To Write data before burst read ends. DQM should be asserted three cycles prior to write command to avoid bus
contention.
2. Row precharge will interrupt writing. Last data input, tRDL before row precharge , will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
ESMT
M12L2561616A (2A)
Note: 1. CS can be dont cared when RAS , CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
ESMT
M12L2561616A (2A)
*Note:
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
ESMT
M12L2561616A (2A)
*Note:
ESMT
M12L2561616A (2A)
ESMT
M12L2561616A (2A)
Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4
ESMT
M12L2561616A (2A)
Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page
*Note:
1. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of Full page write burst stop cycles.
2. Burst stop is valid at every burst length.
ESMT
M12L2561616A (2A)
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page
*Note:
1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by
AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
2. Burst stop is valid at every burst length.
ESMT
M12L2561616A (2A)
10
11
12
13
14
15
16
17
18
19
CLOCK
*Note2
tSS
CKE
tSS
*Note1
tSS
*Note3
CS
RAS
CAS
ADDR
Ra
Ca
BA0
BA1
A10/AP
Ra
tSHZ
DQ
Qa0
Qa1
Qa2
WE
DQM
Prec harge
Power-Down
En try
Row Active
Prech arge
Power-Down
Exit
Active
Power-d own
Entry
Read
Precharge
Active
Power-down
Exit
: Don't care
*Note:
1. All banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tSS prior to Row active command.
3. Can not violate minimum refresh specification.
ESMT
M12L2561616A (2A)
10
11
12
13
14
15
16
17
18
19
CLOCK
*Note4
*No te 2
t RFC min
*Note1
*Note6
CKE
*No te 3
tSS
CS
*Note5
RAS
*No te 7
CAS
ADDR
BA0,BA1
A10/ AP
DQ
Hi -Z
Hi-Z
WE
DQM
Auto Refresh
: Don't care
*Note:
TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be dont care except for CKE.
3. The device remains in self refresh mode as long as CKE stays Low.
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
ESMT
M12L2561616A (2A)
10
CLOCK
HIG H
HIGH
CKE
CS
tRFC
*Note2
RAS
*Note1
CAS
*Note3
ADDR
Key
Ra
HI-Z
HI-Z
DQ
WE
DQM
MRS
New
Command
New Command
Auto Refresh
:Don't Care
All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
*Note:
1. CS , RAS , CAS , & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
ESMT
M12L2561616A (2A)
PACKING DIMENSIONS
54-LEAD TSOP(II) SDRAM (400mil) (1:3)
A
A2
see detail A
28
54
B
L
E
E1
A1
L1
DETAIL "A"
Pin 1 identifier
27
c1
c
BASE METAL
b
b1
WITH PLANTING
-C-
Seating plane
Symbol
Min
A
A1
A2
b
b1
c
c1
D
E
E1
L
L1
e
Y
0.05
0.95
0.30
0.30
0.12
0.10
0.40
SECTION B-B
Dimension in mm
Norm
Max
1.20
0.10
0.15
1.00
1.05
0.45
0.35
0.40
0.21
0.127
0.16
22.22 BSC
11.76 BSC
10.16 BSC
0.50
0.60
0.80 REF
0.80 BSC
0.1
8
Min
0.002
0.037
0.012
0.012
0.005
0.004
0.016
Dimension in inch
Norm
Max
0.047
0.004
0.006
0.039
0.041
0.018
0.014
0.016
0.008
0.005
0.006
0.875 BSC
0.463 BSC
0.400 BSC
0.020
0.024
0.031 REF
0.031 BSC
0.004
8
ESMT
M12L2561616A (2A)
PACKING
DIMENSIONS
54-BALL
SDRAM ( 8x8 mm )
Symbol
Dimension in mm
Min
Norm
Max
A
1.00
A1
0.20
0.25
0.30
A2
0.61
0.66
0.71
b
0.30
0.35
0.40
D
7.90
8.00
8.10
E
7.90
8.00
8.10
D1
6.40
E1
6.40
e
0.80
Controlling dimension : Millimeter.
Dimension in inch
Min
Norm
Max
0.039
0.008
0.010
0.012
0.024
0.026
0.028
0.012
0.014
0.016
0.311
0.315
0.319
0.311
0.315
0.319
0.252
0.252
0.031
ESMT
M12L2561616A (2A)
Revision History
Revision
Date
0.1
2010.12.10
1.0
2011.01.05
Delete Preliminary
1.1
2012.06.07
Modify Page 42
=10 to 8
b,b1=0.25 to 0.3mm
1.2
2012.08.24
Description
Original
ESMT
M12L2561616A (2A)
Important Notice