Low Power LDO with Fast Load Transient

Response Based on Quick Response Circuit

Socheat HENG

Weichun TUNG

Cong-Kha PHAM

University of Electro-Communications
Tamkang University
The University of Electro-Communications
Chofu-shi, 182-8585, Japan
Taiwan
Chofu-shi, 182-8585, Japan
Email: socheat@vlsilab.ee.uec.ac.jp Email: 494350050@mail.tku.edu.tw
Email: pham@ee.uec.ac.jp

Abstract In this work, we propose a design technique of low

power fully CMOS low-dropout voltage regulator (LDO) based
on quick response (QR) circuit to improve the load transient
response. Implemented in 0.18m CMOS technology, the LDO
with proposed QR circuit can achieve a fast load transient
responses with less transient overshoot or undershoot when
driving a large load current. For 1F decoupling capacitor and
0.1mA-150mA load current change, the output undershoot and
overshoot are 196mV and 172mV while the settling time is
approximately 60s and 65s respectively . The proposed circuit
dissipates a very low static power, with only 8.5A for light load
and 35A for heavy load for output voltage V OU T = 1.2V and
input voltage V DD = V OU T +1.0V . This includes the reference
circuit, the over current protection circuit as well as the feedback
network.

I. I NTRODUCTION
The explosive proliferation of battery-operated equipments
such as cellular phones, notebook computers, and palmtop
computers in the past decade have accelerated the development
and usage of LDO and low quiescent current linear regulators.
LDOs are widely built into all electronic appliances by all
means not only for portable electronic devices. Recently, in
order to save power consumptions, a system that was originally
supplied by one LDO is divided into many blocks and supplied
by a plurality of LDO. So this means that the power is
supplied only to an operating block and unused blocks are
made into a standby mode. As a result, the power consumption
can be saved for a full system. This method is achieved by
stopping partly the internal clock for an inactive block to lower
consumed current and restarting the operation according to
the need. Lets see from LDOs side in this condition, the
load changes instantaneously from un-loaded to full loaded
states. Hence, the high-speed load transient response of LDO
is required.
In this paper, we present the design method of low power
LDO with high-speed load transient response. It can catch
instantaneous load fluctuation even though from low-power
operating condition. Furthermore, no matter how fast the load
changes, safe mechanism is proposed to prevent the LDO from
falling into unstable state.
II. R ELATIONSHIP BETWEEN Q UIESCENT C URRENT AND
L OAD R ESPONSE AND T HE C ONVENTIONAL P ROBLEMS
In LDO design, large gate capacitance of power transistor
degrades the loop-gain bandwidth and the slew rate at the gate

978-1-4244-3828-0/09/$25.00 2009 IEEE

Fig. 1. Completed Circuit of the Proposed Circuit

drive of the LDO in low-power condition. Both low quiescent

current and high-speed load transient response, therefore,
cannot be achieved simultaneously by using the generic LDO
structure[1]. The recent application requires the high-speed
load transient response less than 0.5S for load variation. This
clearly shows that the conventional method reported in [3] can
not reach the above requirement since its boosting method is
available for low speed load variation.
To obtain a high driving capability, power MOSFET is
designed in a very big size resulted in a very large gate
capacitance which is up to 250pF for 30, 000m power
MOSFET size in order to drive 300mA load current. When
load suddenly changes, the output voltage is first supplied by
decupling capacitor. Responding to that, error amplifier lowers
power MOSFET gate potential in order to raise up the output
voltage. But this builds up the time constant to charge the
gate capacitance of power MOSFET. In other words, the load
transient response of the LDO voltage regulator is originally
limited by the slew rate time to drive the gate of the power
MOSFET.
Imagine the output impedance of error amplifier is 10k (at
3V supply voltage and 333A bias current), the time constant
of power MOSFET gate becomes more than 2s. This means
that the 0.5s of load transient response can not be achieved.
To obtain the time constant below 0.5s, thus, the bias current
must be above 1mA. So low power consumption LDO can not
be realized.
Until recently, in order to keep the output voltage drop
at minimum value, a big decoupling capacitor is used. But

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big isnt appropriate to small size portable device due to it

demands more chip area and cost. The purpose of this work
is to achieve a low operating current LDO with high-speed
load transient current but without utilizing big capacitor.
III. Q UICK R ESPONSE C IRCUIT FOR I MPROVEMENT OF
L OAD T RANSIENT R ESPONSE
So far, there were many reports described on how to fasten
the speed of power MOSFET in order to achieve the highspeed load transient response. For example, a method reported
in [2] is to insert a voltage buffer driver between the error
amplifier and the power MOSFET. The voltage buffer should
improve both the loop-gain bandwidth and slew rate at the gate
drive of the power MOSFET, while the buffer dissipates small
quiescent current in the static state. However, it is difficult
to realize a good voltage buffer to meet the requirements
perfectly in practice [2]. It means, we need to make sure that
the driver wont make the LDO fall into unstable state at any
load condition.
In this work we proposed a quick response circuit to charge
and discharge the capacitor which contains in the gate capacitance of power MOSFET. Fig. 1 shows the main structure of
the proposed quick response circuit and its implementation to
generic LDO.
The proposed circuit works as following. At load stable
stage, the output voltage of the regulator is memorized by the
memory circuit. When load immediately changes, the output
voltage V OU T sharply fluctuates due to the late response of
low power error amplifier. At this moment, the next stage
comparators compare the level of memorized voltage and
fluctuation V OU T ,and then decide whether the load current
changes from small to big or in the reverse. If the load current
changes from small to big, then the PD-DISCHARGE circuit
will respond immediately to discharge power MOSFET gate.
By doing this way, power MOSFET will become more ON, so
that the output voltage drop can be minimized at the smallest
drop level. At the same consideration, if the load current
changes from big to small, then the PD-CHARGE circuit will
respond immediately to charge up the power MOSFET gate.
At the same time, the VOUT-DISCHARGE circuit works to
pull down the output voltage. By doing this way, the power
MOSFET will become more OFF, so that the output voltage
overshoot can be minimized at the smallest overshoot level.
A. The generic LDO structure
Fig. 2 shows the structure of the generic LDO used to
evaluate the proposed circuit. It is the LDO regulated by 1
stage amplifier with NMOS input stage. Capacitor Cp1 and
resistance Rp are working together as the phase compensation
circuit to stabilize the LDO. We design the bias current of the
error amplifier to the lowest value because we will not expect
its transient response to help regulating V OU T when load
current immediately change.
B. Memory Circuit
The memory circuit is formed by transistor M D1, M D12,
M D13 and capacitor CD1 like shown in Fig. 4(a). Lets make

Fig. 2. The generic LDO structure

the current of M D1 as Ib. CD1 works to memorize V OU T

at static state. The charge or discharge time of V OU T into or
out from this capacitor are defined by Ib and V OU T itself.
Generally, its the time constant of CD1 and ON resistance
of M D12. Since M D12 and M D13 are formed in current
mirror, then current flow through M D12 is also Ib. So we got
the ON resistance of M D12 and the charge time of V OU T
as following.
V OU T
CD1
(1)
Ib
We knows that the load current fluctuation time is less than
0.5s. In order to makes it possible to memorize V OU T ,
the time constant must be designed to be more than 0.5s.
An example in this work, we set CD1 to 10pF and Ib to
100nA. So we got = V OU T 100s which is big enough
to memorize VOUT.
= RonM D12 CD1 =

C. Comparator Circuit
The comparators utilized in the proposed circuit are the
open-loop comparators shown Fig. 3. The special features of
these kind of comparators are the high gain stage and the
variable offset of the input voltage.

Fig. 3. The Comparator used in the Proposed Circuit

We know the performance of this kind of comparator

should be similar to the uncompensated two-stage
operational amplifier. Since the circuit is not necessary
to be operated in high frequency range, we abbreviated

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the discussion on poles as well as frequency characteristic.

Now lets make V CO as the output of the comparator
(M H1, M H2, M H7, M H9, M H10, M H11, M H13). The
minimum and maximum output voltage of this comparator
are approximately V COL V SS and V COH V DD
respectively. The small-signal voltage transmission can be
expressed as the following equation.
V CO

VG9 gmM H9 VG10 gmM H10

)
gdsM H1 + gdsM H10
gmM H11
(
)
gdsM H11 + gdsM H13

COM 2 completely got into operating condition. This current

occurs especially when V DD starting up. At load stable stage
COM 3=L and M D10 turns OFF.

= (

(2)

Small-signal voltage transmission reached the above equation is because we set the (W/L)M H9 and (W/L)M H10 to
different value. By doing this we obtain the flexible offset voltage of comparator just adjusting the size these two transistors.
So, the out stage of this new comparator can be decided by
the following condition.
If VG9 gmM H9 < VG10 gmM H10 Then, V CO V SS
If VG9 gmM H9 > VG10 gmM H10 Then, V CO V DD
Now lets implement the above comparator to the proposed
LDO. As shown in Fig. 3, we used two comparators COM 1
and COM 2 to detect the load current by monitoring the
memorized output voltage V M E and the present output
voltage V OU T . Consider the offset voltage of COM 1 and
COM 2 as and respectively. Then we got,
If V OU T < V M E Then, COM 1= L to H
If V OU T + > V M E Then, COM 2 = H to L
as well as COM 3 = L to H
Hence, we can obtain two signals for charge and discharge
circuit to charge and discharge power MOSFET gate which
we are going to mention in the next subsection.

Fig. 4. The Charge and Discharge circuit used in proposed QR circuit

IV. M EASUREMENT R ESULT

The measurement was done with the following conditions.
The output voltage of LDO is set to V OU T = 1.2V with
1F decoupling capacitor at input node and 1F , 4.7F
decoupling capacitors at output node. The load current varies
from 0.1A to 150mA with 0.5s raise and fall time.

D. Charge and Discharge Circuit

The charge and discharge circuit are shown in Fig. 4(b)
and Fig. 4(c). As shown in Fig. 4(b), the PD-DISCHARGE
circuit is formed by transistor (M D2, M D7, M D8, M D9)
and capacitor CD3. At load stable stage COM 1=L and
M D7, M D9 turn OFF. CD3 is charged to V DD by the drain
current of M D2. When the current changes from small to big,
COM 1= L to H. The power MOSFET gate is discharged to
ground by current Id. The discharge time is defined by CD3
and RdsM D7 of M D7.
As shown in Fig. 4(b), the PD-CHARGE circuit is formed
by transistor (M D6, M D3, M D4, M D5) and capacitor CD2.
At load stable stage COM 2=H and M D3, M D5 turns OFF.
CD2 is charged to V SS by the drain current of M D6. When
the current changes from big to small, COM 2=H to L. The
power MOSFET gate is charged to VDD by current Ic. The
charge time is defined by CD2 and RdsM D3 of M D3.
The VOUT-DISCHARGE circuit is formed by transistor
M D10, M D11. It functions as discharge circuit to pull down
V OU T when PD-CHARGE circuit turns OFF the power
MOSFET by current Ie. M D11 is added in diode connection
to avoid the inrush current flow through M 10 drain before

Fig. 5. Load Transient Response at IOUT=0.1-150mA and COUT=1F

Fig. 6. Load Transient Response at IOUT=0.1-150mA and COUT=4.7F

Fig. 5 and Fig. 6 are the measurement results of load trasient

response of the proposed LDO with QR circuit adopted. From
Fig. 5, the output drop and overshoot are only 196mV and
172mV while the settling time is approximately 60s and

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V OU T is not included in the comparison table since the

previous reports discussed mainly on only the drop voltage.
IOU T (max)
Current Effeciency Ief f = IOU T (max)+ISS(max)
CoutV OU T
TR = IOU T (max)
T Iss
F OM = IOURT (max)
where ISS, IOU T are the quiescent current and load
current respectively.
TABLE I
T HE P ERFORMANCES C OMPARISON W ITH P REVIOUS R EPORTED LDO S

Year
CMOS [m]
IOUT [mA]
ISS [mA]
Ief f [%]
V OU T [mV ]
TR [s]
Cout [F ]
ESR Required
FOM [ns]

Fig. 7. The Input Output and PSRR Characteristic

65s respectively for 0.1mA to 150mA load change and 1F

output decoupling capacitor. For 4.7F output capacitor, as
shown in Fig. 6, the the output drop and overshoot are only
116mV and 104mV while the settling time is approximately
65s and 45s respectively.
Fig. 7(a) shows DC characteristics of LDO by changing
V DD from 0.5V to 2.5V at load current 0mA to 150mA.
The LDO is regulating V OU T properly without any effects
of the proposed the QR circuit. From the figure, the current
consumption of the completed LDO is not more than 8.5A
for light load and 35A for heavy load at V OU T = 1.2V
and V DD = V OU T + 1.0V .
Fig. 7(b) shows the power supply rejection ratio (PSRR)
characteristic of the proposed LDO with QR circuit. The PSSR
at 10Hz is 74dB while at 1KHz is 61.8dB for power supply
ripple voltage AC = 200mV peak to peak and IOU T =
50mA as well as V DD = V OU T + 1.0V .
Fig. 8 is the micrograph of the fabricated chip. The die
area is 634m489m. It includes the reference circuit, over
current protection circuit as well as feedback network.
V. PERFORMANCE COMPARISON
Comparing to the LDOs which are reported in [4], [5], [6],
[7], we got the comparison shown in Table 1. To be fair in
comparison, we define the following characteristics the same
as those in [4]. However, the overshoot of the output voltage

[4]
2000
1.0
200
0.030
NA
220
1.1
1
Yes
0.165

[5]
2003
0.6
100
0.038
99.96
130
2
10
Yes
4.9

[6]
2005
0.09
100
6
94.3
90
0.00054
0.00060
No
0.035

[7]
2006
0.35
200
0.020
99.8
54
0.27
1
No
0.027

This Work
2008
0.18
150
0.0085
99.99
196
1.3
1
No
0.073

From the table, the current efficiency of the proposed circuit

is improved comparing to the past reports.
VI. C ONCLUSION
We have demonstrated a new design technique to improve
the load transient response of low-dropout linear regulator using a 0.18m CMOS technology. Compared to other designs,
the proposed LDO achieves a fast response time and low
output fluctuation but low power dissipation with only 8.5A
for light load and 35A for heavy load at V OU T = 1.2V and
V DD = V OU T + 1.0V . This includes the reference circuit,
over current protection circuit as well as feedback network. For
1F decoupling capacitor and 0.1mA-150mA load current
change, the output undershoot and overshoot are 196mV and
172mV respectively while the settling time is approximately
60s and 65s respectively . The PSRR of the proposed LDO
can be maintained at 61.8dB for 1KHz frequency.

Fig. 8. Micrograph of the LDO Voltage Regulator.

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R EFERENCES
[1] P.Hazucha, T.Karnik, A. Bloechel, C.Parsons, D.Finan, S.Borkar, AreaEfficient Linear Regulator With Ultra-Fast Load Regulation, IEEE J.
Solid-State Circuit, Vol.40, No.4, pp.933-940, Apr. 2005.
[2] Hoi Lee, T.Karnik, Philip K. T. Mok and Ka Nang Leung, A Design
of Low-Power Analog Drivers Based on Slew-Rate Enhancement Circuits for CMOS Low-Dropout Regulators, IEEE J. Solid-State Circuit,
Vol.52, No.9, pp.563-567, Sep. 2005.
[3] Yen-Shyung SHYU and Jiin-Chuan WU, A 60A Quiescent Current, 250mA CMOS Low Dropout Regulator, IEICE Trans Electron,
Vol.E84-C, No.5, pp.693-703, May 2001.
[4] G. A. Rincon-Mora, Active capacitor multiplier in Miller-compensated
circuits, IEEE J. Solid-State Circuits, Vol.35, No.1, pp.26-32, Jan. 2000.
[5] K. N. Leung and P. K. T. Mok, A capacitor-free CMOS low-dropout
regulator with damping-factor-control frequency compensation, IEEE
J. Solid-State Circuits, Vol.38, No.10, pp.1691-1701, Oct. 2003.
[6] P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan and S.
Borkar, Area-efficient linear regulator with ultra-fast load regulation,
IEEE J. Solid-State Circuits, Vol.40, No.4, pp.933-940, Apr. 2005.
[7] MohammadAl-Shyoukh, Raul A. Perez and Hoi Lee, ATransientEnhanced 20LA-Quiescent 200mA-Load Low-Dropout Regulator With
Buffer Impedance Attenuation, IEEE 2006 Custom Intergrated Circuits
Conference (CICC), pp.1731-1734, Jul. 2006.