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APPLICATION NOTE
AN1035
Design Considerations for a Ku-Band DRO
in Digital Communication Systems
ABSTRACT
the parts for the DRO and mechanical assembly will be presented. While the design proposed might not yield the optimum design solution for all DBS applications, it does introduce a few important DRO design techniques that can be applied to other high frequency communication systems.
This application note will review the process by which Dielectric Resonator Oscillator (DRO) designers choose their
oscillators topology and devices based on performance requirements, real estate constraints and manufacturing yields
concerns. DROs are attractive microwave sources because of
their high Q, low phase noise, good output power and high
stability versus temperature. They represent a good compromise of costs, size, and performance compared to alternative
signal sources such as cavity oscillators, microstrip oscillators or multiplied crystal oscillators.
SPECIFICATIONS
In a DDBS system application, the DRO must exhibit low
phase noise in order to meet the digital modulation scheme
and Bit Error Rate (BER) requirements. It also must have
minimal frequency drift over temperature to keep the receiver
locked into the selected channel and should provide enough
output power to directly drive the mixer downconverter (usually a diode ring or an active GaAs FET mixer). Because the
DC supply is usually supplied through the IF feed from an
indoor unit, voltage requirements are usually not a constraint
with as much as 8 V available from the system. However,
current draw remains a limitation and needs to be set to the
lowest value that will allow meeting the output power specifications. Finally, DBS applications drive the need for a design that is both compact and light since the LNB will be a
small outdoor unit located at the focal point of an antenna
through a light supportive pole. These last needs were met by
using 0603 (60 mils by 30 mils components) SMT technology components and by laying out the components within a
tightly enclosed cavity. These choices resulted in a .950" by
0.750" by 0.500" final design that also includes the metal
UNITS
SPECIFICATION
SIMULATION
(V)
(mA)
(GHz)
(dBm)
(dBC/Hz)
(dBC/Hz)
(dBC/Hz)
(dBC/Hz)
(dBC/Hz)
(KHz)
(MHz)
(dBC)
(dBC)
N/A
8 0.25
20 2.5
11.25
7 2.5
-58
-80
-90
-100
-120
800 max
2
-40 min
-80 min
VSWR 2.0:1
6.0
18
11.25
7.2
-61.3
-91.3
-120.4
-131.2
Not simulated
Not simulated
-20 min
N/A
Not simulated
(C)
(MHz)
-55 to +80
2
Not simulated
Not simulated
MEASURED
PERFORMANCE
6.0 0.25
18
11.25
6.5
-62.8
-89.4
-97.6
-112.3
-130.0
200
1
-50 min
-80 min
VSWR 1.5:1
(With Buffer)
-55 to +80
700 KHz
AN1035
cavity, the tuning screw and output connectors. The enclosed
Table 1 summarizes the design goals, simulated performance
and final laboratory results.
AN1035
1.0
CGD_PKG
LD
Q1
LG_PKG
LG
0.55nH
0.5nH
LD_PKG
DRAIN
0.76nH
0.1nH
CDS_PKG
CGX
0.15pF
5.0
0.2
GATE
CGS_PKG
0.15pF
2.0
0.5
0.003pF
LS
0.25nH
0.15pF
CDX
0.02pF
LS_PKG
0.05nH
SOURCE
0.0 0.0
0.2
1.0
0.5
2.0
5.0
INF
-5.0
-0.2
-2.0
-0.5
-1.0
Frequency 0.5 to 18.0 GHz
72218_multi_ac_tb
measured_S11
72218r58_multi
S(3, 3)
72218_multi_ac_tb
modeled_S11
72218r58_multi
S(1, 1)
PARAMETER
VALUE
-1.8065
0
2.5
0.0396
0.072
0.03
1.8
0.3
1
1e-14
1.3
0
0
4e-12
0.27e-12
5000
1e-10
0.85e-12
0.055e-12
0.3
0.3
0.5
Infinity
4
10
4
0
2e-10
1.5
3
1.43
0
0
1
DEFINITION
Nonscaleable portion of the threshold voltage
Scaleable portion of the threshold voltage
Current saturation parameter
Transconductance parameter or coefficient
AC drain pull coefficient
DC drain pull coefficient
Power law exponent
Output feedback coefficient
Built-in gate potential
Gate junction reverse saturation current
Gate junction ideality factor
Source end channel resistance
Drain end channel resistance
Transit time under gate
Drain-source capacitance
Dispersion source output impedance
Dispersion source capacitance
Zero bias gate-source junction capacitance
Zero bias gate-drain junction capacitance
Capacitance saturation transition voltage parameter
Capacitance threshold transition voltage parameter
Coefficient for forward bias depletion capacitance
Gate-drain junction reverse bias breakdown voltage
Drain ohmic resistance
Gate ohmic resistance
Source ohmic resistance
Gate metal resistance
Flicker noise coefficient
Flicker noise exponent
Temperature exponent for saturation current
Energy gap or band gap voltage
VTO temperature coefficient
BETA exponential temperature coefficient
Flicker noise frequency exponent
Table 2. Triquint's own model (TOM) parameters for the NE72218 nonlinear model
AN1035
-100
1.0
2.0
0.5
5.0
0.2
0.0 0.0
0.2
1.0
0.5
2.0
5.0
INF
-5.0
-0.2
-2.0
-0.5
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
-155
-160
-165
-170
-175
-180
-185
-190
100K
VDS = 3 V
ID = 30 mA
VG = 0.957 V
1K
-1.0
Frequency 0.5 to 18.0 GHz
120
60
30
2
1
180
-150
-30
-60
-90
72218_multi_ac_tb
measured_S21
72218r58_multi
S(4, 3)
90
0.4
60
150
30
0.2
0.1
180
-150
-30
-60
-90
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
-155
-160
-165
-170
-175
-180
-185
-190
100K
VDS = 3 V
ID = 40 mA
VG = 0.946 V
1K
10K
100K
1M
10M 40M
72218_1_fnoise2_tb
v_noise_out
72218_1_fnoise
OUT_EQN
Re: 3 V, 40 mA
0.3
-120
Frequency MHz
10M 40M
-100
3
150
-120
1M
72218_1_fnoise1_tb
v_noise_out
72218_1_fnoise
OUT_EQN
Re: 3 V, 30 mA
100K
Frequency MHz
72218_multi_ac_tb
modeled_S22
72218r58_multi
S(2, 2)
72218_multi_ac_tb
measured_S22
72218r58_multi
S(4, 4)
10K
72218_multi_ac_tb
modeled_S12
72218r58_multi
S(1, 2)
AN1035
CHOICE OF TOPOLOGY
There are essentially four different classes of DROs that can
be designed: Reaction, transmission, parallel-feedback and
reflection DROs. A reaction DRO is a free running oscillator
with enough appropriate feedback to oscillate in the desired
frequency range. The frequency of oscillation is then stabilized with a Dielectric Resonator (DR) on the output. Because of the design method, this oscillator usually has a high
spurious content and does not provide low phase noise [4].
The parallel-feedback and the transmission DRO uses the DR
between two transmission lines to provide the frequency selective loop feedback between the input and the output of an
amplifier design. Usually, these two configurations do not
allow too much adjustment during on-the-bench tuning and
are generally complex to model with a simulator. Because of
the tight enclosure required in LNB designs, most DROs display some level of feedback within the cavity. In most cases,
however, that effect is both undesired and rarely simulated.
Finally, the reflection type DRO uses the concept of negative
resistance in which the resonator is placed near a terminated
microstrip line connected to the input port of an unstable
amplifier. Near its resonant frequency, the dielectric resonator reflects power back to the amplifier, causing an oscillation build-up between the two components that can be tapped
into. In this configuration, the coupling between the resonator and the transmission line is easier to model and spurious
oscillations are more readily avoided. Figure 7 shows the
topology that will be used for this DRO design.
VDD
DS
DR
R3
C1
C2
SS1
SS2
R1
U1, NE72218
Output
R2
C3
loading effects.
Choose a device with a low flicker noise. The 1/f noise characteristic of the NE72218 (Figure 6) makes this device a prime
choice for the application.
Maximize the power at the input of the oscillator (High Pavs).
A light coupling of the DR will ensure that most of the circuits
available power is stored in the DR and available at the FETs
gate.
In addition, the phase noise is also dominated by Signal to
Noise Ratio at the input (SNRI) which depends on the noise
figure of the active device and on the Pavs (power available
from the source). Consequently, design rules that make good
Low Noise Amplifiers (LNAs) also apply to low phase noise
oscillators. Usually, a typical oscillator runs at about 20%
efficiency, however, this achievement also depends on how
much output power is tapped out of the circuit. A higher output power means higher efficiency, however, this will reduce
the circuits loaded Q, which in turn degrades the phase noise
performance. A light output coupling will increase phase noise
but reduce the power available to drive the rest of the system.
With this trade-off in mind, this particular circuit was set to
achieve 5% efficiency to provide a minimum of 6 dBm output power over temperature.
Negative Resistance Amplifier
The most common use of GaAs FET amplifiers at Ku-Band
is in the common source configuration. However, without
feedback elements, the common source FET transistor does
not make a very good oscillator because of its small feedback
capacitance from input to output (CGD0=0.055 pF) when compared to other capacitance values in the FET.
Therefore, to generate the required output to input feedback,
the design will use a common drain configuration. This structure is very unstable and makes excellent oscillators by using
the internal capacitance feedback of the transistor (CGS0= 0.85
pF) instead of external feedback. This configuration will reverse the normal output with respect to ground since the drain
will provide the RF grounding and all signals will be referenced to that port. By choosing the appropriate drain open
stub length (DS in Figure 7), the designer will determine the
frequency at which the series negative resistance will be generated on the gates reflection port. That port should be set to
a quarter wavelength at the desired frequency of oscillation.
Selecting the correct reactance at the source (Ss1) maximizes
the magnitude of the reflection coefficient at the gate terminal. Adjusting these two parameters will provide the required
amount of negative resistance at the needed frequency. Adjusting the output matching network and the amount of output coupling (C3) will drive the output power and loaded Q
(and therefore the phase noise) of the oscillator. As the amplitude of the oscillation increases, the active devices start
saturating, and magnitude of the negative resistance decreases
until it is equal to the equivalent resistance presented by the
DR at the resonant frequency. For a steady state oscillation to
occur, the following condition needs to be met in the input
reference plane of the active device:
AN1035
in * R = 1
(1)
ure 7). The position of the resonator relative to the transmission line determines the oscillators stability, output power
and phase noise. As will be seen in the next sections, optimum positioning can be tricky but is greatly aided by linear
and nonlinear simulations. Adjusting d increases or decreases
the amount of coupling. A higher coupling provides more
output power and robustness of oscillation build-up, however, it reduces the loaded Q and therefore the phase noise
performance. A lower coupling will improve phase noise but
reduces the output power, and under certain circumstances,
the oscillator could fail to start oscillating. Therefore, when
designing a low noise oscillator, the compromise will be to
set the distance d small enough that the oscillator will always
start (under both quick and slow turn-on and at all temperatures) and provides enough power, but large enough to get
high loaded Q and low phase noise. Finally, as more energy
is stored in the DR, the temperature characteristics of the DRO
more closely follow that of the DR. Consequently, a lighter
coupling will also provide more control of the LO drift over
temperature. The phase relationship of the puck to the active
device is as equally critical to efficiently creating an oscillation build-up. The electrical length ( ) (Figure 7) representing the physical distance between the FET and the pucks
plane of reference will determine how fast and stable the buildup will occur, driving both output power and phase noise performance.
Mechanical Considerations
In a DRO, the electrical layout is only one aspect of the oscillator design. Mechanical interests also highly influence the
local oscillators performance. The cavitys size and height
have loading effects on the LO which can reduce the phase
noise performance and create an unwanted frequency drift
over temperature. Under best conditions, the DR would be
free to resonate in free space, but because of obvious real
estate consideration, the LO needs to be constrained within a
shielded cavity. References [4] and [7] analyze in depth the
effects of enclosed cavities, and rules-of-thumb dictate that
in order for the cavity to have a reasonable thermal and loading effects, the cavity should be at least three pucks high and
three pucks diameter wide. This height requirement is one
reason most DRO designers prefer to set their DR on a standoff, so that the housing or PCB on which the DR usually rests
does not affect the resonators performance. The PCB
materials mechanical integrity also needs careful consideration because of LO drift over temperature and long term
aging effects, especially if the cavity is resting on the PCB.
For example, Rogers 4003 material is hard enough to allow
only minimum frequency aging while providing a low tangent loss at 12 GHz. This low insertion loss provides for a
low noise figure performance as well as a high Q for the circuit. However, other low loss materials such as Teflon mesh
compound do not have the same mechanical integrity and the
PCB thickness has a tendency to change over time. Although
this has little bearing in an amplifier design, in an oscillator,
the cavity and ground plane relations will slowly change over
AN1035
time, providing a slow LO drift or aging effect that could
obsolete the LNB after a few years. Finally, the fine tuning
and adjustment of the DRO will be set through a tuning screw
that will increase the DRs resonant frequency as it closes the
electrical field above the puck. This should provide as much
80 MHz of tuning range. However, it is important to notice
that tuning the frequency with a tuning screw is achieved at
the cost of reduction in both unloaded Q and temperature stability. This increase in temperature stability is due to the increasing slope of the tuning curve as the metal plate gets closer
to the DR surface. Therefore, if no more than about 10 MHz
of loading can be achieved, the design will provide a good
compromise between adjustment for manufacturing variations
and high performance.
TP
TP1
TP
MLIN
TP2 S2P
TL2
SNP1
W= 46
FILE = 722r581
L = 51
MSUB = MSUB1
TP
TAND = TAND1
TP3
MTEE
TEE1
W1 = 20
W2 = 46
W3 = 8
MSUB = MSUB1
var
Eqn
DATA
MSUB
MSUB1
ER = 3.38
H = 20
T = 0.70
RHO = 0.71
RGH = 4.00e-03
COND1 = cond
COND2 = cond2
VAR
VAR
source stub = 80
drain stub = 82
n=3
DIEL1 = diel
DIEL2 = diel2
HOLE = hole
RES = resi
DATA
TAND
TAND1
TAND = 2.50e-03
MLIN
TL1
W = 46
L = 80
MSUB=MSUB1
TAND=TAND1
AMMETER
AMM1
MLIN
TL D1
W=8
L = 170
MSUB=MSUB1
TAND=TAND1
MTEE
TEE2
W1 = 8
W2 = 8
W3 = 46
MSUB = MSUB1
MTEE
TEE3
W1 = 35
W2 = 8
W3 = 35
MSUB = MSUB1
MLIN
TL D2
W = 10
L = 175
MSUB=MSUB1
TAND=TAND1
DCVS
SRC1
DC = 6
0603 Cap Mod
X8
W1 = 10
W2 = 35
C1 = 1000
V2
COND2 LAYER = cond2
D1 = 25
D2 = 25
H = 20
T = 0.70
W = 35
COND1 LAYER = cond
HOLE LAYER = hole
gate
PRLC
PRLC1
R = 5000
RES
L = 5.00e-03
R3
R = 1000000000 C = 40.00
0 XFER
1 XFER2
4 N=n
0
MLIN
OSCTEST2
TL6
OSC1
W = 62
L = 50
MSUB = MSUB 1
TAND = TAND 1
PORT
P2
PORT
port = 2 P1
port = 1
0603 Res Mod
X1
W1 = 35
W2 = 35
R1 = 101
MLEF
TL7
W = 25
L = 30
MSUB = MSUB1
TAND = TAND1
VIA
COND2 LAYER = cond2
V1
D1 = 25
D2 = 25
H = 20
T = 0.70
W = 35
COND1 LAYER = cond
HOLE LAYER = hole
AN1035
4
M1
2
0
The resonator is modeled as a parallel resistor-inductor-capacitor where the value of L and C are adjusted to provided
the proper resonant frequency (11.25GHz) and Q factor (Figure 8).
M2
-2
-4
-6
-8
-10
0 =
-12
-14
2 LC
-16
-18
-20
10
12
14
16
Q0 = 2
res_tb
modeled_S11
72218_res_tb
s(1,1)dB
Q0 =
res_tb
modeled_S22
72218_res_tb
s(2,2)dB
0 d
2 d
1.0
2.0
0.5
0.2
0 = 2
0 and is the phase of the resonator impedance.
0.0 0.0
d
2R
Q0 = R because
=
d
0
L
L
1.0
0.5
2.0 M1
M2
INF
S11 Resonator
at resonance.
-5.0
-0.2
-2.0
-0.5
-1.0
Frequency 11.0 to 11.5 GHz
res_tb
S11_inv
72218_res_tb
OUT_EQN
res_tb
modeled_S22
72218_res_tb
S(2, 2)
AN1035
Negative Resistance Modeling
From the negative resistance amplifier section, we know that
the common drain amplifier should be set so that:
Its drain will be AC shorted at the frequency of interest
providing the required feedback to unstabilize the FET. This
is done through TL8, an open stub on the drain that is close to
a /4 length. The stub is also isolated from the DC supply
with a high impedance /4 line (TL D1) followed by another
/4 open stub (TL4). Adjusting TL8 will mostly move the
negative resistance peak up and down in frequency. Its length
was adjusted so that the maximum negative resistance occurred at 11.25 GHz (Figure 11).
The source reactance will define the amount of negative
resistance at the gate. This is achieved by adjusting TL3 in
conjunction with the oscillator output network (matched to
50 ) and the self-biasing network (X4). TL3 was adjusted
to provide about +3 dB gate reflection coefficient but could
be increased to provide a higher return gain. However, too
much return gain could provide unwanted spurious oscillation due to the non-perfect return loss of the 50 load shorting the gate beyond the DRs placement. The short open stub
TL7 models the second source pin of the four pin FET device.
It will provide a negative resistance on the gate port and a
good output match into 50 Ohms.
The phase delay of the transmission line needs to be set to
0 so that (1) condition is respected and a steady state oscillation occurs.
In actuality and for a better understanding of the simulation,
designers will consider the parameter 1/S11 of the active device, since we are interested in in * R 1 and therefore in
making sure that
in
1
S11
180
160
140
120
100
80
60
40
20
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
240
210
180
150
120
90
60
30
0
-30
-60
-90
-120
-150
-180
-210
-240
-270
-300
M1
M2
8
10
12
14
16
res_tb ZI1
72218_res_tb
Z1
Re: Ohm
AN1035
Using the schematic of Figure 12, the simulator predicted
the results shown in Figures 13 and 14. Compared to the
measured performance (Table 1), it can be seen the simulation was useful in predicting actual circuit behavior.
MLEF
TL7
W = 25
L = 30
MSUB = MSUB1
TAND = TAND1
TP
TP1
gate
TP
MLIN
TP2 72218 sch
TL2
X2
W= 46
L = 51
MSUB = MSUB1
TP
TAND = TAND1
TP3
MLIN
TL1
W = 46
L = 80
MSUB=MSUB1
TAND=TAND1
MTEE
TEE1
W1 = 20
W2 = 46
W3 = 8
MSUB = MSUB1
var
Eqn
VIA
V6
D1 = 25
D2 = 25
H = 20
T = 0.70
W = 35
COND1 LAYER = cond
HOLE LAYER = hole
DATA
VAR
VAR
source stub = 80
drain stub = 100
n = 1.50
DIEL1 = diel
DIEL2 = diel2
HOLE = hole
RES = resi
AMMETER
AMM1
MLIN
TL D1
W=8
L = 170
MSUB=MSUB1
TAND=TAND1
MTEE
TEE2
W1 = 8
W2 = 8
W3 = 46
MSUB = MSUB1
MLIN
TL D2
W = 10
L = 175
MSUB=MSUB1
TAND=TAND1
DATA
VIA
COND2 LAYER = cond2
V1
D1 = 25
D2 = 25
H = 20
T = 0.70
W = 35
COND1 LAYER = cond
HOLE LAYER = hole
-40
-50
M1
M1
-60
M2
-70
M3
-80
M2
-50
-90
-110
-120
-130
V2
COND2 LAYER = cond2
D1 = 25
D2 = 25
H = 20
T = 0.70
W = 35
COND1 LAYER = cond
HOLE LAYER = hole
DCVS
SRC1
DC = 6
TAND
TAND1
TAND = 2.50e-03
-100
PORT
P source
port = 1
MTEE
TEE3
W1 = 35
W2 = 8
W3 = 35
MSUB = MSUB1
MSUB
MSUB1
ER = 3.38
H = 20
T = 0.70
RHO = 0.71
RGH = 4.00e-03
COND1 = cond
COND2 = cond2
PRLC
PRLC1
R = 5000
RES
L = 5.01e-03
R3
R = 1000000000 C = 40.00
0 XFER
1 XFER2
4 N=n
0
MLIN
OSCTEST2
TL6
OSC1
W = 62
L = 50
MSUB = MSUB 1
TAND = TAND 1
VIA
V4
D1 = 25
D2 = 25
H = 20
T = 0.70
W = 35
COND1 LAYER = cond
HOLE LAYER = hole
-140
100
-100
M3
M4
-150
1000000
Offset Frequency Hz
72218_osc_calamp_tb
OSCPHNZ1
72218_osc_ca
OSCPHNZ
dBc/Hz
10
20
30
40
50
60
70
AN1035
CIRCUIT TESTING
Upon achieving satisfying results with the simulation and
choosing the appropriate circuit values for the different components, a prototype board was constructed and tested for
compliance with the proposed specifications. When turned
on, the DRO exhibited a lower than expected output power
(+2 dBm) and the tuning range (via the tuning screw) was
less than the preferred 100 MHz minimum range, even after
optimizing the puck placement. This was due to non-optimal
length of the two tuning stubs (Source and Drain). Decreasing the length of the drain stub by about 20 mils brought back
the oscillators center frequency to 11.25 GHz, slightly increased the output power and provided the required tuning
range. Decreasing the source stub granted the expected output power (6.5 dBm). During that process, no tuning element
values (capacitor or resistors) had to be modified and it was
also verified that the oscillator would not have spurious oscillations at undesired frequencies by removing the puck. If
an oscillation occurs without the resonator, it means that the
FET provides too much gain or the circuit has too much indirect feedback. Such spurious oscillation has a loading effect
on the circuit and seriously reduces the DROs phase noise
performance. Self-oscillation problem can also result from a
poor 50 termination on the gate. If at any frequencies, the
return loss of the termination is less than the devices reflection gain, a spurious oscillation will occur. Therefore, it is
important to ensure a good match throughout the frequency
range where the device exhibits high reflection gain. In the
presented design, this was achieved in reducing the inherent
parasitics of the SMT resistors by paralleling two 100 . For
a more comprehensive testing, all spurious oscillation testing
also has to be run at low temperatures, since under such thermal conditions, GaAs devices have more gain and a higher
propensity to self-oscillate.
RL
RDC
C1
VCC
RS
L.O.OUT
ATTEN 20 dB
RL 10.0 dBm
10 dB/
D
S
MKR
100.1 K Hz
-109.4 dB/Hz
SPAN 220.0 K Hz
SWP 5.50 sec
AN1035
ATTEN 30 dB
RL 20.0 dBm
10 dB/
MKR
10.01 K Hz
-93.39 dB/Hz
D
S
ATTEN 30 dB
RL 20.0 dBm
SPAN 22.00 K Hz
SWP 8.80 sec
MKR
1.000 K Hz
-63.36 dB/Hz
D
S
10 dB/
SPAN 3.000 K Hz
SWP 2.28 sec
-50
-60
-70
-100 dBc/Hz
@ 100 KHz
-100
-110
-120
-120 dBc/Hz
@ 1 MHz
-130
-140
10 2
10 3
10 4
10 5
10 6
Frequency (Hz)
REFERENCE
DESIGNATOR
(Refer to Figure 7)
U1
DR1
C1
C2
C3
R1 (2 in parallel)
R2
R3
PCB1
CAVITY1
DESCRIPTION
APPROXIMATE COST in $
(100K QUANTITIES)
0.60
0.70
0.02
0.02
0.02
0.010
0.005
0.005
0.5
1.00
2.88
AN1035
SUMMARY
REFERENCE
[1] R. Muat, Choosing Devices for quiet oscillators, Microwave & RF, August 1984.
[2] California Eastern Laboratories, AN1034, Designing
VCOs and Buffer Using the UPA Family of Dual Transistors.
[3] D. B. Leeson, A Simple Model of Feedback Oscillator
Noise Spectrum, Proc. IEEE, vol. 54 p. 329, Feb. 1966.
[4] J.S. Sun, L. Wu, C.C. Wei, Network Analysis simplifies the design of Microwave DROs, Microwaves & RF,
May 1990.
[5] California Eastern Laboratories, AN1026, 1/f Noise characteristics influencing Phase Noise.
[6] Randall W. Rhea, Oscillator Design and Computer
Simulation, Noble Publishing, Atlanta, 1995.
[7] Trans-Tech, An introduction to Dielectric Resonators,
N0. 821
To contact Trans-Tech for a free Application notes on Dielectric Resonators, call (301) 695-7065.
[8] California Eastern Laboratories, AN1023, Converting
GaAs FET Models for Different Nonlinear Simulators.