A Highly-Efficient Multi-Band Multi-Mode Digital

Quadrature Transmitter with 2D Pre-Distortion

Hua Wang , C.-H. Peng , Chao Lu , Yaopei Chang , Richard Huang , Andy Chang , Genie Shih , Ray Hsu ,
Paul C. P. Liang , SangWon Son , Ali Niknejad , George Chien , CL Tsai , and HC Hwang

MediaTek USA Inc., San Jose, CA 95134

Inc., Hsinchu Science Park, Taiwan
University of California, Berkeley, CA

MediaTek

Abstract A novel highly-efficient multi-band multi-mode all

digital quadrature transmitter is presented. The all digital transmitter uses in-phase (I) codeword and quadrature (Q) codeword
to control a switching-mode power amplifier (PA) or digital PA
(DPA) consisting of in-phase PA (I-PA) and quadrature PA (QPA), where each of the power cells inside I-PA or Q-PA is either
on or off. Due to the load interaction between I-PA and Q-PA, a 2dimensional digital pre-distortion is applied to linearize DPA. The
total transmitter is implemented in 40nm CMOS LP process and
occupies a die area of 0.7mm2 . The digital quadrature transmitter
can support 20MHz, 40MHz, and 80MHz WiFi signals, Band
38 and Band 40 LTE signals with class 3 output power, and
Bluetooth BDR, EDR2, and EDR3 signals.

I. I NTRODUCTION
The geometry downscaling of advanced nano-meter CMOS
process reduces the available voltage swing, thus making the
conventional radio frequency (RF) design extremely challenging. Furthermore, the more bandwidth efficient modulation
schemes in modern communication systems possess high peak
to average power ratio (PAPR), which makes a conventional
RF transceiver even less efficient. The conventional direct conversion transmitter occupies a large area, which is translated
into high cost, and has very low efficiency, which is translated
into energy waste. The advanced nano-meter CMOS process
certainly favors digital-intensive RF transceiver architecture.
Digital power amplifier (DPA) based transmitter architecture
obviously fits in this design paradigm [1], [2]. Since more
complicated digital signal processing algorithms can be built
into the transceiver with relatively low power consumption
under advanced nano-meter CMOS process, these algorithms
can help alleviate non-idealities that are inherent in the DPA
based architecture.
A novel all digital transmitter that eliminates many conventional analog components is proposed. In Section II the
architecture of the proposed digital quadrature transmitter is
described in detail. In Section III delay mismatches among
control signals in DPA are explained as they are important in
specifying the DPA design parameters. Measurement results
of the proposed digital quadrature transmitter applied to WiFi,
LTE, and Bluetooth are shown in Section IV. Section V
concludes the discussion by pointing out the trend of digital
RF transmitter technology.

978-1-4673-5762-3/13/$31.00 2013 IEEE

II. A RCHITECTURE OF THE P ROPOSED D IGITAL

Q UADRATURE T RANSMITTER
The architecture of the proposed digital quadrature transmitter is composed of a digital front end (DFE), an RF-powerDAC, and a local oscillator (LO) chain, as shown in Fig. 1.
The LO chain provides the carrier frequency fc to the RFpower-DAC and a lower clock frequency at the output of the
divider to the DFE. The DFE consists of a first up-sampler,
a rate converter, a 2-dimensional digital pre-distortion (2DDPD) unit, a second up-sampler, and a sign and magnitude
(Sign and Mag.) unit converting 2s complement representation
to sign and magnitude representation. The RF-power-DAC
consists of a first set of latches, a decoder, a second set of
latches, and a DPA that is further composed of two identical
PAs, in-phase PA (I-PA) and quadrature PA (Q-PA). The DFE
takes in a digital baseband (DBB) signal and its associated
clocks CLK1 and CLK2, and provides the RF-power-DAC I
codeword and Q codeword in the format of 1 sign bit and
12 magnitude bits. The maximum and minimum codewords
are 4095 and -4095, respectively. The interface between DFE
and RF-power-DAC usually runs at a high clock frequency,
e.g., 800MHz to 900MHz. Since the characteristics of DPA
determine the algorithms that should be developed in the DFE,
the RF-power-DAC is described first, then the DFE.
Digital Front End (DFE)
DBB

Up-sampler

Rate Converter

CLK1

Up-sampler

Sign and Mag.

2D LUT
Clock Generator (Memory)

CLK2
LO Chain
2fc

2D-DPD

RF-power-DAC
RF

Divider
DCC

Fig. 1.

Latches

Decoder

Latches

DPA

Buffer

Architecture of the proposed digital quadrature transmitter.

A. RF-power-DAC
The RF-power-DAC consists of a first set of latches that
ensure all bits in the digital codeword from the DFE have
correct timing, a decoder that translates magnitude bits into
control signals for each of the power cells of a DPA, a second
set of latches that ensure the control signals reach the DPA
with correct timing, and the DPA that functions simultaneously

501

as a digital-to-analog converter, a mixer, and a power amplifier.

Fig. 2(a) shows the topology of the DPA, where both I-PA and
Q-PA are composed of current-mode Class-D power cells that
are ultimately controlled by the I codeword I-BB[12:0] and the
Q codeword Q-BB[12:0]. A multiplexer (MUX) controlled by
the sign bit I-BB[12] or Q-BB[12] is used to select the polarity
of the LO to avoid a wide-band phase modulator, while the
decoded signal from the magnitude bits I-BB[11:0] or QBB[11:0] is used to enable each of the power cells. A duty
cycle control (DCC) circuit is implemented in the LO chain as
shown in Fig. 1 to adjust timing overlap between the two legs
of a differential pair to improve power efficiency. In order
to reduce the differential non-linearity of digital-to-analog
conversion and not to introduce too much circuit complexity,
the power cells of I-PA or Q-PA are further partitioned into a
6-bit thermometer (unary) array and a 6-bit binary array. Floorplanning is designed carefully to reduce the systematic delay
mismatches among power cells. The digital nature of each
power cell is evident from the components used to construct
each power cell, such as switching, logical AND, and buffer
circuits.
The DPA exhibits high non-linearities, which can be observed from its equivalent baseband input-output relation that
is called a DPA profile. Fig. 2(b) shows the DPA output when
uniform I and Q codewords are applied to DPA. Obviously
there is more compression at the outer peripheral of the DPA
profile. Furthermore I-PA output is not only a function of I
codeword, but also a function of Q codeword.

2) Rate Converter: The rate converter converts the input

sampling frequency to a frequency that is integer related to the
RF carrier frequency, i.e., the RF carrier frequency is an integer
multiple of the output sampling frequency of the rate converter.
Since the carrier frequency can be any allowed number by
different radio standards, a fractional rate converter is needed.
A natural cubic spline [3] is used to interpolate from the 4
available controls points, say, x1 , x0 , x1 , x2 , at time -1, 0,
1, 2, the desired value y evaluated at t,

0
1
0
0
x1
2
4


 7 1
15
15
5
5
x0 ,
y(t) = 1 t t2 t3
4
9
6
1

1
5
5
5
5
1
x
31
1 1
2
3
(1)
where 0 < t < 1. Since the above equation is a polynomial
in terms of t, it can be implemented in Farrow structure [4]
with three general purpose multipliers.
3) 2D-DPD: Since there is a strong load interaction between I-PA and Q-PA, the conventional AM-AM/AM-PM
digital pre-distortion method cannot be applied in the proposed digital quadrature transmitter. An adaptive algorithm is
developed to build a 2D look-up table (LUT) based on both
input I and Q values, rather than AM alone. Fig. 3 shows
a simplified block diagram of 2D-DPD training, where a 2D
gradient search algorithm is used as the 2D adaptive algorithm
to obtain the 2D LUT.
DFE

I-PA
Vgb

Q-PA

Vgb

2
Q

Vgb

2D LUT
(Memory) Yk (m, n)

VDD

I-BB[0]

Training
Signal

Q-BB[0]
LO+

I-BB[12:0]

MUX

I-BB[12]

LO-

I-LO

En
LO-

LO+

Q-BB[12]

MUX

En

Q-LO

Q-BB[12:0]

(a) Current-mode Class-D topology.

Fig. 2.

X(m, n)

2D
Adaptive
Algorithm

B To RF

RF-power-DAC

Y (o) (m, n)

RFOut

Vgb

2D-DPD

DBB

A
A
Zk (m, n)

A: Training Mode
B: Normal Operation Mode
Internal Loopback Path

2
4

Fig. 3.

6
6 4 2 0
I

2D-DPD LUT training.

Suppose a 2D LUT of size M N is to be built. Let

X(m, n) be the input complex value corresponding to the table
entry (m, n), where m = 1, 2, , M and n = 1, 2, , N .
A complex codeword Y (o) (m, n) should be found such that
the output of DPA corresponding to this codeword represents
X(m, n). Initially set Y0 (m, n) = X(m, n), the update
algorithm at the (k + 1)-th iteration is

(b) DPA output profile.

DPA topology and its corresponding output profile.

B. Digital Front End

Each block of DFE is now described in detail. One of the
most important blocks is the 2D-DPD block.
1) Up-sampler: The up-sampler uses poly-phase filters to
change the sampling frequency of the input signal to a higher
sampling frequency. There are several up-sampling filters in
the DFE. The focuses of these up-sampling filters are different.
For example, in WiFi application, the design of the first upsampling filter has to guarantee the filtered signal can meet
the stringent IEEE mask, while later stage up-sampling filters
should have enough attenuation at the digital images caused
by interpolating zeros between the input samples.

Yk+1 (m, n) = Yk (m, n)+Ek (m, n), k = 0, , K 1, (2)

where K is the number of the total iterations, is a step size
(real value), Ek (m, n) is a complex error defined as
Ek (m, n) = X(m, n) Zk (m, n), k = 0, , K 1, (3)
where Zk (m, n) is the DPA output corresponding to input
Yk (m, n). After K iterations, a 2D LUT is generated with
Y (o) (m, n) = YK (m, n) being the value for the entry (m, n).
Because there are 13 bits in I-PA and Q-PA, ideally M =
8191 and N = 8191 are desired, i.e., a 2D LUT of size

502

81918191. However keeping such a large 2D LUT takes a lot

memory and the table look-up would consume a lot of power.
Therefore instead of a full 2D LUT calibration, M and N can
be set to a much smaller value, say M = 32 and N = 32,
to shorten calibration time, reduce memory size, and lower
power consumption in table look-up in normal operation mode
without any noticeable performance degradation. In normal
operation mode, a bi-linear interpolation is used to obtain the
2D-DPD codeword for the input that is not in the 2D LUT.
Like a conventional direct-conversion transmitter, the proposed digital quadrature transmitter architecture also suffers
from the IQ mismatch and DC offset. For the conventional
transmitter, the calibration of IQ mismatch and PA nonlinearity are often performed separately. However, for the proposed digital quadrature transmitter, 2D-DPD can compensate
IQ mismatch, DC offset, and DPA nonlinearity simultaneously.
III. D ELAY M ISMATCHES AMONG C ONTROL S IGNALS IN
DPA

c12 (Sign Bit)

Latch
b0

c11
Decoder

bm

c0

Phase
Selector

u0
un

Fig. 4.

Latch

s
bm

Power
Cell

Die photograph.

un

Power
Cell

b0

The performance of WiFi 11g, 11n, 11ac signals is measured. Fig. 6 shows the error vector magnitude (EVM) and
DPA efficiency versus output power of WiFi 11g 54Mbps
signal measured at the chip output. The highest power levels
of the tested WiFi signals that can meet both IEEE mask
and EVM requirements are listed in Table I. The measured
PSD of 11ac 80MHz MCS9 signal is shown in Fig. 7 as a
demonstration of the typical PSD of WiFi signal.

bm

Latch

Fig. 5.

DPA

A. WiFi

Latch

Latch

The proposed digital quadrature transmitter is implemented

in 40nm LP CMOS process and packaged in QFN as a test
chip. The sample rate converter was not included in the test
chip as it does not affect the verification of concept. Fig. 5
shows the die photograph of the test chip. The die area is
about 0.7mm2 , out of which DFE occupies about 0.18mm2
and consumes 22mW. Measurement results of the proposed
digital quadrature transmitter for different types of signals are
shown below.

LO Chain

LO

IV. M EASUREMENT R ESULTS

Digital
Front End

Since each power cell of I-PA or Q-PA is digitally controlled

by the combination of LO, sign bit, and magnitude bits, it
is important to model the delay mismatches among control
signals in DPA as they can not be captured in the DPA profile,
yet they are very important in specifying the DPA design
parameters. Fig. 4 shows the modeling of delay mismatches
among control signals in either I-PA or Q-PA. c12 , , c0 are
the bits in the codeword after the first set of latches (cf. Fig. 1),
but before the decoder. The sign bit c12 is used to select one
of the phases of LO, and the phase selector output experiences
a delay of s before reaching a power cell. The magnitude bits
c11 , , c0 are decoded into binary control signals bm , where
m = 0, 1, , 5, to control binary cells, and unary control
signals un , where n = 0, 1, , 62, to control unary cells.
The control signal bm experiences a systematic delay of bm
due to layout and a random delay bm due to device mismatch
before reaching a power cell. Similar delay modeling holds for
the control signal un .

delay mismatches also include a systematic delay from LO

to a power cell due to layout and a random delay from
LO to a power cell due to device mismatch. However these
delay mismatches are modeled by changing the DPA profile
accordingly.
Among the different delay mismatches, system-level simulation shows that LO random delay to binary power cells,
whose standard deviation is in the order of 1ps, and signbit delay s , whose value should be less than 50ps, are the
two most sensitive delay parameters that each can degrade the
power spectral density (PSD) at LTE Band 1 (2110-2170MHz)
by 2dB to 4dB if WiFi band (2401-2483.5MHz) is used for
transmission.

u0
un

TABLE I
P ERFORMANCE METRICS FOR W I F I SIGNALS .

Delay model of control signals in DPA.

In addition to the modeling of delay mismatches for sign

bit and decoded control signals from magnitude bits, the delay
mismatches of LO to all power cells are also modeled. These

503

Signal
11g 54Mbps
11n 40MHz MCS7
11ac 80MHz MCS9

Power (dBm)
18.8
17.1
15.7

EVM (dB)
-25
-30.8
-33

IEEE spec. (dB)

25
28
32

20

20
0.00
-10.0

EVM
Efficiency

-20.0

40

10

-30.0
-40.0
-50.0

Efficiency (%)

15

EVM (dB)

30

-60.0
-70.0
-80.0

(a) UTRA ACLR.

50
8

10

12
14
16
Power (dBm)

18

5
20
0.00
-10.0
-20.0

Fig. 6. EVM and DPA efficiency versus output power of WiFi 11g 54Mbps
signal.

-30.0
-40.0
-50.0
-60.0
-70.0
-80.0

-5.00
-15.0
-25.0
-35.0
-45.0

(b) E-UTRA ACLR.

-55.0
-65.0

Fig. 8. Measured UTRA ALCR and E-UTRA ACLR of 20MHz LTE signal
in Band 40.

-75.0
-85.0

Fig. 7.

TABLE III
P ERFORMANCE METRICS FOR B LUETOOTH SIGNALS .

Measured PSD of 11ac 80MHz MCS9 signal.

Signal
BDR
EDR2
EDR3

B. LTE
The measured LTE signal can reach 21dBm output power
while still meeting UTRA ACLR 1, UTRA ACLR 2, and EUTRA ACLR1 requirement. The performance of LTE signals
in Band 38 and Band 40 is listed in Table II, while the typical
UTRA ACLR and E-UTRA ACLR of LTE signal are shown
shown in Fig. 8(a) and Fig. 8(b), respectively.
TABLE II
P ERFORMANCE METRICS FOR LTE

Band
38
40

Power
(dBm)
21.1
21.2

UTRA
ACLR1
(dB)
-34.3
-33.9

UTRA
ACLR2
(dB)
-36.1
-36.1

Power (dBm)
10.1
7.3
7.3

favg /fmax ,DEVMrms

favg /fmax = 1.09
DEVMrms=1.64%
DEVMrms=1.61%

SIG spec.
favg /fmax 0.8
DEVMrms 20%
DEVMrms 13%

SIGNALS .

EUTRA
ACLR
(dB)
-30.1
-30.4

EVM
%
5.95
5.9

Fig. 9.

C. Bluetooth
The performance of Bluetooth BDR (GFSK), EDR2 (/4DQPSK), and EDR3 (8DPSK) signals is also measured. The
highest requested output power is 10.1dBm for BDR, and
7.3dBm for EDR2 and EDR3. Under such low power, 2D-DPD
can be safely turned off. The performance of Bluetooth signals
without 2D-DPD is shown in Table III, while the typical PSD
of Bluetooth EDR3 signal is shown in Fig. 9.
V. C ONCLUSION
A highly-efficient digital quadrature transmitter through the
utilization of digital algorithms and DPAs has been proposed.
The digital quadrature transmitter can support many signal
types, such as WiFi, LTE, Bluetooth, etc., in different RF

Measured PSD of Bluetooth EDR3 signal.

bands, with supported bandwidth up to 80MHz. As CMOS

process advances so rapidly, the size and current of digital
circuit will go down significantly, which should inevitably
push the RF transmitter toward digital-intensive design to
further reduce die area and improve efficiency.
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[1] R. B. Staszewski et. al., All-digital PLL and transmitter for mobile
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amplifier in 65-nm CMOS technology, IEEE Journal of Solid State
Circuits, vol. 46, no. 8, pp 1796-1809, Aug. 2011.
[3] F. B. Hildebrand, Introduction to numerical analysis, 2nd ed. Dover
Publications, Inc., 1987.
[4] C. W. Farrow, A continuously variable digital delay element, IEEE
International Symposium on Circuits and Systems, pp 2641-2645, Dec.
1988.

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