THE MC68000 INSTRUCTION SET

Most instructions involving the movement or manipulation of data

specify the data size with an extension on the mnemonic, .B for single
byte, .W for two-byte word, or .L for four-byte long word. The default
size is word. Figure shows how these options modify the effect of an
instruction which writes 0s into a data register.
Before:
D5 11A2B3C4D
Instruction:
CLR.B D5
After:
D5 1A2B3C00

D5 11A2B3C4D

D5 11A2B3C4D

CLR.W D5

CLR.L D5

D5 1A2B0000

D5 00000000

The MC68000 addressing modes are grouped into four classes

depending on the type of operand involved.
Data modes include those which refer to data operands as opposed to
address operands.
Memory modes refer to operands that are found in memory as
opposed to those found in registers.

Alterable modes are those referring to operands that may be modified

or written over during the execution of the program.
Control modes refer to operands that are addresses used in program
control (targets for subroutine calls or branches, for instance).
Addressing mode Data Mem Alt
Absolute short

Contr Assembly language

Operand format
X
XXXX

Absolute long

XXXXXX

Immediate

#XXX

Data register
direct
Address register
direct
Address register
indirect (ARI)
ARI with postincrement
ARI with predecrement
ARI with
displacement
ARI with index

Dn

An

(An)

(An)+

-(An)

d(An)

d(An,Rn)

d(PC)

d(PC,Rn)

PC Rel with
displacement
PC Rel with
index

4.1 The MC68000 Data Movement Instructions

Most of the data movement instructions have no effect on the
condition code bits.
The basic data movement instruction in the MC68000 is the move
instruction (MOVE). The MOVE instruction and its variations are used
primarily to initialize registers and to store results into memory. They
cause the data specified in the source to be moved to the place specified
in the destination.
The clear instruction (CLR) moves 0s into every bit of the byte,
word, or long word destination.
Exchange (EXG) interchanges the entire contents of two registers
(the allowed size is long only). The operands must be two registers from
the set Dl through D7 and Al through A7, for example EXG D1,A4.
SWAP is an instruction which interchanges the 16-bit halves of the
data register specified in the operand.
Load effective address (LEA) loads the destination address register
with the complete 32-bit effective address obtained from the address
calculation as required by the source. This instruction is often used when
repeated reference must be made to the data at the effective address. It
allows the programmer to call for the calculation of the address one time
only and to load it into an address register. Future references to data at
that address can then be made with the more efficient address register
indirect addressing mode.

MC68000 data movement instruction limitations

Instruction mnemonic

Allowed
op. size

Allowed modes/classes
Source
Destination

CCR bits
N Z V C X

EXG Rx,Ry

L only

Dn or An

Dn or An

- - - - -

CLR <ea>

B, W, L

Data alt

0 1 0 0 -

LEA <ea>,An

L only

Control

An

- - - - -

MOVE <ea>,<ea>

B, W, L

All

Data alt

* * 0 0 -

MOVE <ea>,CCR

W only

Data

CCR

* * * * *

MOVE <ea>,SR

W only

Data

SR

* * * * *

MOVE SR,<ea>

W only

SR

Data alt

- - - - -

Move An.USP

L only

An

USP

- - - - -

MOVE USP,An

L only

USP

An

- - - - -

MOVEA <ea>,An

W,L

All

An

- - - - -

MOVEM list,<ea>

W, L

Dn list

Control alt or -(An)

- - - - -

MOVEM <ea>,list

W, L

Control or (An)+

Dn list

- - - - -

MOVEP Dx,d(Av)

W,L

Dn

d(An)

- - - - -

MOVEP d(Ax),Dy

W,L

d(An)

Dn

- - - - -

MOVEQ #<data>,Dn

L only

Imm

Dn

* * 0 0 -

SWAP Dn

Wonly

Dn

* * 0 0 -

* bit is properly updated

- bit remains unchanged
4

4.2 The MC68000 Arithmetic Instructions

The primary function of the instructions in this section is to perform
arithmetic operations on the contents of registers or memory locations.
The add and subtract instructions (ADD and SUB) add or subtract the
source operand to or from the destination operand and store the result in
the destination. In order to make it possible to extend the precision of
arithmetic operations beyond 32 bits (long word), two instructions
include the extend bit (X) in the operation. The add-extended (ADDX)
and subtract-extended (SUBX) instructions add or subtract the operands.
(1) ADD.L D1,D3 ADD LOW HALVES
(2) ADDX.L D0,D2 ADD HIGH HALVES
The MC68000 includes several varieties of the add and subtract
instructions.
Add/subtract address (ADDA/SUBA, word or long word only)
allows any source operand but requires an address register for a
destination.
Add/subtract immediate (ADDI/SUBI) uses an immediate source
operand and any data-alterable destination. Add/subtract quick
(ADDQ/SUBQ) includes a small immediate operand (8 bits) and any
data-alterable destination.
Compare (CMP) is an instruction which subtracts the source operand
from the destination operand and discards the result after using it to
update the condition code bits CMPA should be used when the
destination is an address register, CMPI should be used when the source
is an immediate operand, and CMPM should be used for memory-tomemory comparisons. Many assemblers will automatically make the
appropriate selection.
Negate (NEG) changes the sign (2's complement) of the destination
value by subtracting it from 0 and storing the result in the destination
location. Negate with extend (NEGX) subtracts the value and the extend
bit from 0 and stores the result.

The test instruction (TST) subtracts 0 from the value of the operand.
This instruction is used to update CCR bits N and Z to reflect the value of
the operand, whether it is positive or negative, 0 or non-0. The related
instruction, test and set (TAS), operates only on a byte-sized operand in a
similar fashion but it also sets the highest bit in the operand byte. The test
and set operation is indivisible and may not be interrupted. It is used to
synchronize the operations of a multi-processor system.
Extend (EXT) sign extends the value of the operand in a designated
data register from 8 to 16 bits (.W) or from 16 to 32 bits (.L). This
instruction converts an 8-bit signed number into a 16-bit signed number
or a 16-bit signed number into a 32-bit signed number by copying the
sign bit from the original number into every extended bit position.

The instructions "arithmetic shift left" and "arithmetic shift right" can
be used to perform simple multiply and divide operations. Arithmetic
shift left (ASL) shifts the pattern in the destination to the left while
bringing 0s to the right end. The last bit shifted out shifts into the carry
and the extend flags.

Each bit-shift to the left doubles the weight of each position in the
original binary number, so the effect of this instruction is to multiply the
destination value by an integer power of 2.
Arithmetic shift right (ASR) shifts the pattern right while bringing a
copy of bit 7 (the sign bit) into the leftmost position. This operation
results in dividing the value by an integer power of 2 while preserving
the sign.
Decimal arithmetic is supported by two instructions, add and subtract
decimal extended (ABCD and SBCD). These instructions add or
subtract the (single-byte only) operands along with the extend bit, as in
the case of the extended binary operations. However, both operands
must be valid eight-bit BCD numbers and the BCD result is stored in the
destination location.
The sign of a single-byte BCD operand may be changed with the
instruction NBCD, negate decimal extended. The sign of the destination
operand is changed by subtracting it and the extend bit from 0 and
storing the result in the destination location.
Two versions each of the multiply and divide instructions provide
both signed and unsigned operations, word size only. The multiply
instructions (MULS and MULU) multiply two 16-bit operands and load
the 32-bit product into a destination data register. The divide instructions
(DIVS and DIVU) divide the 32-bit destination operand by the 16-bit
source operand and load the quotient into the lower half of a destination
data register and the remainder into the upper half.

MC68000 arithmetic instruction limitations

Instruction mnemonic Allowed
operand
size
ABCD Dx,Dy
B only

Allowed modes/classes CCR bits

Source Destination N Z V C X
Dn

Dn

? * *

ABCD -(Ax),-(Ay)
ADD <ea>,Dn
ADD Dn,<ea>
ADDA <ea>,An
ADDI #<data>,<ea>
ADDQ ^<data>,<ea>
ADDX Dx,Dy
ADDX -(Ax),-(Ay)
ASd Dx,Dy
ASd #<data>,Dn
ASd <ea>
CMP <ea>,Dn
CMPA <ea>,An
CMPI #<data>,<ea>
CMPM (Ax)+,(Ay)+
DIVS <ea>,Dn
DIVU <ea>,Dn
EXTDn
MULS <ea>,Dn
MULU <ea>,Dn
NBCD <ea>
NEG <ea>
NEGX <ea>
SBCD Dx,Dy
SBCD -(Ax),-(Ay)
SUB <ea>,Dn
SUB Dn, <ea>
SUBA <ea>,An
SUBI #<data>,<ea>
SUBQ #<data>,<ea>
SUBX Dx, Dy
SUBX -(Ax),-(Ay)
TAS <ea>
TST <ea>

-(An)
All
Dn
All
Imm
Imm
Dn
-(An)
Dn
Imm
All
All
Imm
(An)+
Data
Data
Data
Data
Dn
-(An)
All
Dn
All
Imm
Imm
Dn
-(An)

-(An)
Dn
Alt mem
An
Data alt
Alt
Dn
-(An)
Dn
Dn
Mem alt
Dn
An
Data alt
(An)+
Dn
Dn
Dn
Dn
Dn
Data alt
Data alt
Data alt
Dn
-(An)
Dn
Alt mem
An
Data alt
Alt
Dn
-(An)
Data alt
Data alt

?
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
?
*
*
?
?
*
*
*
*
*
*
*
*

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

?
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
0
0
?
*
*
?
?
*
*
*
*
*
*
0
0

B only
B, W, L
B, W, L
W, L
B, W, L
B, W, L
B, W, L
B, W, L
B, W, L
B, W, L
Wonly
B, W, L
W, L
B, W, L
B, W, L
Wonly
Wonly
W, L
Wonly
Wonly
B only
B, W, L
B, W, L
B only
B only
B, W, L
B, W, L
W, L
B, W, L
B, W, L
B,W,L
B,W,L
B only
B,W,L

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
0
0
0
0
*
*
*
*
*
*
*
*
*
*
*
0
0

*
*
*
*
*
*
*
*
*
*
*

*
*
*
*
*
*
*
*
*
*
*
-

4.3 The MC68000 Logic Instructions

This includes instructions whose primary functions are to perform logic
operations or other bit-level manipulations on the contents of registers or
memory locations. Three logic operations, AND, OR, and exclusive-OR,
may be performed between the individual bits of a source operand and
those of a destination operand. The result is loaded into the destination
location. The corresponding mnemonics are AND, OR and EOR.
Variations of these instructions include operations with an immediate
source and either a standard destination, the condition code register
(CCR), or the status register (SR). The mnemonics are ANDI, ORI, and
EORI.

The logic shift and rotate instructions are similar in format to the
arithmetic shift instructions. They shift the bits in the destination pattern
and the X and C bits in the CCR.

The logic shift left instruction (LSL) shifts the pattern left while
bringing a 0 in from the right. The bits shifted out from the most
significant position go to both the carry and the extend flags. The logic
shift right instruction (LSR) shifts the pattern right while bringing a 0 in
from the left. The rightmost bits shift into the carry and the extend.
The rotate left instruction (ROL) shifts the pattern left while bringing
the most significant bit into the carry and also back into the least
significant position, thus rotating the target data pattern.
The rotate with extend instructions (ROXL and ROXR) include the
extend bit in the rotation of the pattern, thus rotating a 9-, 17- or 33- bit
pattern. In other respects, including the shifting of the end bit into the
carry, these instructions are identical to the rotate instructions.
Four instructions allow the programmer to focus on an individual bit
in the destination operand. The instructions are: test a bit and clear it
(BCLR); test a bit and set it (BSET); test a bit and change it (BCHG),
which complements the bit; and test a bit (BTST), which leaves the bit
unchanged.
10

MC68000 logic instruction limitations

Instruction mnemonic Allowed
Allowed modes/classes
operand size 'Source
Destination
AND <ea>,Dn
B, W, L
Data
Dn
AND Dn,<ea>
B, W, L
Dn
Alt mem
ANDI #<data>,<ea> B, W, L
Imm
Data alt
ANDI #xxx,CCR
B only
Imm
CCR
ANDI #xxx,SR
W only
Imm
SR
BCHG Src,<ea>
B, L
Dn, Imm Data alt
BCLR Src,<ea>
B, L
Dn, Imm Data alt
BSET Src,<ea>
B, L
Dn, Imm Data alt
BTST Src,<ea>
B, L
Dn, Imm Data alt
EOR Dn,<ea>
B, W, L
Dn
Data alt
EORI #<data>,<ea> B, W, L
Imm
Data alt
EORI #xxx,CCR
B only
Imm
CCR
EORI #xxx,SR
Wonly
Imm
SR
LSd Dx,Dy
B, W, L
Dn
Dn
LSd #<data>,Dn
B, W, L
Imm
Dn
LSd <ea>
Wonly
Mem alt
NOT <ea>
B, W, L
Data alt
OR <ea>,Dn
B, W, L
Data
Dn
OR DN, <ea>
B, W, L
Dn
Alt mem
ORI #<data>,<ea>
B, W, L
Imm
Data alt
ORI #xxx,CCR
B only
Imm
CCR
ORI #xxx,SR
WE only
Imm
SR
ROd Dx.Dy
B, W, L
Dn
Dn
ROd #<data>,Dn
B, W, L
Imm
Dn
ROd <ea>
W only
Mem alt
ROXd Dx,Dy
B, W, L
Dn
Dn
ROXd #<data>,Dn
B, W, L
Imm
Dn
ROXd <ea>
W only
Mem alt

CCR bits
N Z V C
* * 0 0
* * 0 0
* * 0 0
* * * *
* * * *
- * - - * - - * - * - * * 0 0
* * 0 0
* * * *
* * * *
* * 0 *
* * 0 *
* * 0 *
* * 0 0
* * 0 0
* * 0 0
* * 0 0
* * * *
* * * *
* * 0 *
* * 0 *
* * 0 *
* * 0 *
* * 0 *
* * 0 *

X
*
*
*
*
*
*
*
*
*
*
*
*

11

4.4 The MC68000 Test/Branch Instructions

Two conditional branch instructions in the MC68000 use a special
addressing mode known as program counter relative. One of these will be
referred to as the branch instruction, with the generic mnemonic of Bcc.
The other is the test, decrement, and branch instruction, with the generic
mnemonic of DBcc.
The "cc" in the Bcc mnemonic represents the condition to be tested
by the processor. If the condition is satisfied at the time the instruction is
executed, the branch is taken by adding the offset to the content of the
program counter. If the condition is not satisfied then the next instruction
in memory after the Bcc is executed.
The result of the specified conditional test is based upon the value of
certain bits in the condition code register at the time the branch
instruction is executed.
Some of the numerical conditions (greater than, less than or equal,
and so forth.) refer to the result of a preceding subtraction (or compare)
instruction. For those cases, the letters s and m in Table 6.9 stand for
subtrahend and minuend (s - m). As noted in the table, some of these
conditions refer to signed (2's complement) results, while others
designate unsigned results.
The instruction "test condition, decrement, and branch" (DBcc) first
tests for the condition. If it is satisfied (true) then no further action is
taken. If the condition is false, then the lower word in the data register
specified in the instruction is decremented by 1, and if the resulting value
is 1 no further action is taken. If the resulting value is not 1 then the
branch is taken.

12

The MC6800 conditional tests

Instruction
mnemonic
CC
CS
EQ
F
GE
GT
HI
LE
LS
LT
MI
NE
PL
T
VC
VS

Word description
Do if:
carry bit is clear
carry bit is set
equal (to 0)
false (never do it)
greater than or equal
greater than
higher than
less than or equal
lower than or the same
less than
minus
not equal (to 0)
plus
true (always do it)
no overflow
overflow

Test
C=0
C=1
s = m (Z = 1)
always false
m > s (signed)
m > s (signed)
m > s (unsigned)
m < s (signed)
m < s (unsigned)
m < s (signed)
N=1
m s (Z = 0)
N=0
always true
V=0
V=1

4.5 The MC68000 Input/Output Instructions

MC68000 microprocessor has no input/output space to which I/O
instructions may refer. Instead, I/O devices must be included in the
system as if they were ordinary memory locations. Two MC68000
instructions used exclusively with I/O devices are the software reset and
the move peripheral data instructions (RESET and MOVEP). RESET
causes the reset line from the processor to be asserted, resetting all
external devices to predetermined internal states. MOVEP is used to
transfer data between the processor and eight-bit peripheral devices.

4.6 Miscellaneous MC68000 Instructions

Most microprocessors include an instruction which does nothing. In the
MC68000 it is the no-operation instruction (NOP). NOP instruction
causes no operation but it does occupy a word in the program, and
executing it takes some time (four cycles). The processor may be stopped
with the instruction "load status register and stop" (STOP).
13